139 lines
6.1 KiB
C
139 lines
6.1 KiB
C
/*
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* Copyright 2018 The OpenSSL Project Authors. All Rights Reserved.
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*
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* Licensed under the OpenSSL license (the "License"). You may not use
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* this file except in compliance with the License. You can obtain a copy
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* in the file LICENSE in the source distribution or at
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* https://www.openssl.org/source/license.html
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*/
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/*
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* Contemporary compilers implement lock-free atomic memory access
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* primitives that facilitate writing "thread-opportunistic" or even real
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* multi-threading low-overhead code. "Thread-opportunistic" is when
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* exact result is not required, e.g. some statistics, or execution flow
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* doesn't have to be unambiguous. Simplest example is lazy "constant"
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* initialization when one can synchronize on variable itself, e.g.
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*
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* if (var == NOT_YET_INITIALIZED)
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* var = function_returning_same_value();
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*
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* This does work provided that loads and stores are single-instuction
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* operations (and integer ones are on *all* supported platforms), but
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* it upsets Thread Sanitizer. Suggested solution is
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*
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* if (tsan_load(&var) == NOT_YET_INITIALIZED)
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* tsan_store(&var, function_returning_same_value());
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*
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* Production machine code would be the same, so one can wonder why
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* bother. Having Thread Sanitizer accept "thread-opportunistic" code
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* allows to move on trouble-shooting real bugs.
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*
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* Resolving Thread Sanitizer nits was the initial purpose for this module,
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* but it was later extended with more nuanced primitives that are useful
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* even in "non-opportunistic" scenarios. Most notably verifying if a shared
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* structure is fully initialized and bypassing the initialization lock.
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* It's suggested to view macros defined in this module as "annotations" for
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* thread-safe lock-free code, "Thread-Safe ANnotations"...
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*
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* It's assumed that ATOMIC_{LONG|INT}_LOCK_FREE are assigned same value as
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* ATOMIC_POINTER_LOCK_FREE. And check for >= 2 ensures that corresponding
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* code is inlined. It should be noted that statistics counters become
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* accurate in such case.
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*
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* Special note about TSAN_QUALIFIER. It might be undesired to use it in
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* a shared header. Because whether operation on specific variable or member
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* is atomic or not might be irrelevant in other modules. In such case one
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* can use TSAN_QUALIFIER in cast specifically when it has to count.
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*/
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#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L \
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&& !defined(__STDC_NO_ATOMICS__)
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# include <stdatomic.h>
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# if defined(ATOMIC_POINTER_LOCK_FREE) \
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&& ATOMIC_POINTER_LOCK_FREE >= 2
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# define TSAN_QUALIFIER _Atomic
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# define tsan_load(ptr) atomic_load_explicit((ptr), memory_order_relaxed)
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# define tsan_store(ptr, val) atomic_store_explicit((ptr), (val), memory_order_relaxed)
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# define tsan_counter(ptr) atomic_fetch_add_explicit((ptr), 1, memory_order_relaxed)
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# define tsan_ld_acq(ptr) atomic_load_explicit((ptr), memory_order_acquire)
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# define tsan_st_rel(ptr, val) atomic_store_explicit((ptr), (val), memory_order_release)
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# endif
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#elif defined(__GNUC__) && defined(__ATOMIC_RELAXED)
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# if defined(__GCC_ATOMIC_POINTER_LOCK_FREE) \
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&& __GCC_ATOMIC_POINTER_LOCK_FREE >= 2
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# define TSAN_QUALIFIER volatile
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# define tsan_load(ptr) __atomic_load_n((ptr), __ATOMIC_RELAXED)
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# define tsan_store(ptr, val) __atomic_store_n((ptr), (val), __ATOMIC_RELAXED)
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# define tsan_counter(ptr) __atomic_fetch_add((ptr), 1, __ATOMIC_RELAXED)
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# define tsan_ld_acq(ptr) __atomic_load_n((ptr), __ATOMIC_ACQUIRE)
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# define tsan_st_rel(ptr, val) __atomic_store_n((ptr), (val), __ATOMIC_RELEASE)
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# endif
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#elif defined(_MSC_VER) && _MSC_VER>=1200 \
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&& (defined(_M_IX86) || defined(_M_AMD64) || defined(_M_X64) || \
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defined(_M_ARM64) || (defined(_M_ARM) && _M_ARM >= 7))
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/*
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* There is subtle dependency on /volatile:<iso|ms> command-line option.
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* "ms" implies same semantic as memory_order_acquire for loads and
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* memory_order_release for stores, while "iso" - memory_order_relaxed for
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* either. Real complication is that defaults are different on x86 and ARM.
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* There is explanation for that, "ms" is backward compatible with earlier
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* compiler versions, while multi-processor ARM can be viewed as brand new
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* platform to MSC and its users, and with non-relaxed semantic taking toll
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* with additional instructions and penalties, it kind of makes sense to
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* default to "iso"...
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*/
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# define TSAN_QUALIFIER volatile
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# if defined(_M_ARM) || defined(_M_ARM64)
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# define _InterlockedExchangeAdd _InterlockedExchangeAdd_nf
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# pragma intrinsic(_InterlockedExchangeAdd_nf)
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# pragma intrinsic(__iso_volatile_load32, __iso_volatile_store32)
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# ifdef _WIN64
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# define _InterlockedExchangeAdd64 _InterlockedExchangeAdd64_nf
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# pragma intrinsic(_InterlockedExchangeAdd64_nf)
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# pragma intrinsic(__iso_volatile_load64, __iso_volatile_store64)
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# define tsan_load(ptr) (sizeof(*(ptr)) == 8 ? __iso_volatile_load64(ptr) \
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: __iso_volatile_load32(ptr))
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# define tsan_store(ptr, val) (sizeof(*(ptr)) == 8 ? __iso_volatile_store64((ptr), (val)) \
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: __iso_volatile_store32((ptr), (val)))
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# else
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# define tsan_load(ptr) __iso_volatile_load32(ptr)
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# define tsan_store(ptr, val) __iso_volatile_store32((ptr), (val))
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# endif
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# else
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# define tsan_load(ptr) (*(ptr))
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# define tsan_store(ptr, val) (*(ptr) = (val))
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# endif
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# pragma intrinsic(_InterlockedExchangeAdd)
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# ifdef _WIN64
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# pragma intrinsic(_InterlockedExchangeAdd64)
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# define tsan_counter(ptr) (sizeof(*(ptr)) == 8 ? _InterlockedExchangeAdd64((ptr), 1) \
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: _InterlockedExchangeAdd((ptr), 1))
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# else
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# define tsan_counter(ptr) _InterlockedExchangeAdd((ptr), 1)
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# endif
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# if !defined(_ISO_VOLATILE)
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# define tsan_ld_acq(ptr) (*(ptr))
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# define tsan_st_rel(ptr, val) (*(ptr) = (val))
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# endif
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#endif
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#ifndef TSAN_QUALIFIER
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# define TSAN_QUALIFIER volatile
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# define tsan_load(ptr) (*(ptr))
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# define tsan_store(ptr, val) (*(ptr) = (val))
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# define tsan_counter(ptr) ((*(ptr))++)
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/*
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* Lack of tsan_ld_acq and tsan_ld_rel means that compiler support is not
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* sophisticated enough to support them. Code that relies on them should be
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* protected with #ifdef tsan_ld_acq with locked fallback.
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*/
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#endif
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