96 lines
3.9 KiB
C
96 lines
3.9 KiB
C
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/* FIFOs */
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#define VIF0_FIFO (*(volatile uint128*)0x10004000)
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#define VIF1_FIFO (*(volatile uint128*)0x10005000)
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#define GIF_FIFO (*(volatile uint128*)0x10006000)
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#define IPU_out_FIFO (*(volatile uint128*)0x10007000)
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#define IPU_in_FIFO (*(volatile uint128*)0x10007010)
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/* DMA channels */
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// to VIF0
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#define D0_CHCR (*(volatile uint32*)0x10008000)
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#define D0_MADR (*(volatile uint32*)0x10008010)
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#define D0_QWC (*(volatile uint32*)0x10008020)
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#define D0_TADR (*(volatile uint32*)0x10008030)
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#define D0_ASR0 (*(volatile uint32*)0x10008040)
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#define D0_ASR1 (*(volatile uint32*)0x10008050)
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// VIF1
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#define D1_CHCR (*(volatile uint32*)0x10009000)
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#define D1_MADR (*(volatile uint32*)0x10009010)
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#define D1_QWC (*(volatile uint32*)0x10009020)
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#define D1_TADR (*(volatile uint32*)0x10009030)
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#define D1_ASR0 (*(volatile uint32*)0x10009040)
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#define D1_ASR1 (*(volatile uint32*)0x10009050)
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// to GIF
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#define D2_CHCR (*(volatile uint32*)0x1000a000)
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#define D2_MADR (*(volatile uint32*)0x1000a010)
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#define D2_QWC (*(volatile uint32*)0x1000a020)
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#define D2_TADR (*(volatile uint32*)0x1000a030)
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#define D2_ASR0 (*(volatile uint32*)0x1000a040)
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#define D2_ASR1 (*(volatile uint32*)0x1000a050)
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// fromIPU
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#define D3_CHCR (*(volatile uint32*)0x1000b000)
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#define D3_MADR (*(volatile uint32*)0x1000b010)
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#define D3_QWC (*(volatile uint32*)0x1000b020)
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// toIPU
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#define D4_CHCR (*(volatile uint32*)0x1000b400)
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#define D4_MADR (*(volatile uint32*)0x1000b410)
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#define D4_QWC (*(volatile uint32*)0x1000b420)
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#define D4_TADR (*(volatile uint32*)0x1000b430)
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// from SIF0
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#define D5_CHCR (*(volatile uint32*)0x1000c000)
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#define D5_MADR (*(volatile uint32*)0x1000c010)
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#define D5_QWC (*(volatile uint32*)0x1000c020)
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// to SIF1
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#define D6_CHCR (*(volatile uint32*)0x1000c400)
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#define D6_MADR (*(volatile uint32*)0x1000c410)
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#define D6_QWC (*(volatile uint32*)0x1000c420)
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#define D6_TADR (*(volatile uint32*)0x1000c430)
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// SIF2
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#define D7_CHCR (*(volatile uint32*)0x1000c800)
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#define D7_MADR (*(volatile uint32*)0x1000c810)
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#define D7_QWC (*(volatile uint32*)0x1000c820)
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// fromSPR
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#define D8_CHCR (*(volatile uint32*)0x1000d000)
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#define D8_MADR (*(volatile uint32*)0x1000d010)
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#define D8_QWC (*(volatile uint32*)0x1000d020)
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#define D8_SADR (*(volatile uint32*)0x1000d080)
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// toSPR
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#define D9_CHCR (*(volatile uint32*)0x1000d400)
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#define D9_MADR (*(volatile uint32*)0x1000d410)
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#define D9_QWC (*(volatile uint32*)0x1000d420)
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#define D9_TADR (*(volatile uint32*)0x1000d430)
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#define D9_SADR (*(volatile uint32*)0x1000d480)
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/* DMA controller */
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#define D_CTRL (*(volatile uint32*)0x1000e000)
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#define D_STAT (*(volatile uint32*)0x1000e010)
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#define D_PCR (*(volatile uint32*)0x1000e020)
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#define D_SQWC (*(volatile uint32*)0x1000e030)
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#define D_RBSR (*(volatile uint32*)0x1000e040)
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#define D_RBOR (*(volatile uint32*)0x1000e050)
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#define D_STADR (*(volatile uint32*)0x1000e060)
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#define D_ENABLER (*(volatile uint32*)0x1000f520)
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#define D_ENABLEW (*(volatile uint32*)0x1000f590)
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/* GS privileged registers */
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#define GS_PMODE (*(volatile uint64*)0x12000000)
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#define GS_SMODE1 (*(volatile uint64*)0x12000010)
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#define GS_SMODE2 (*(volatile uint64*)0x12000020)
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#define GS_SRFSH (*(volatile uint64*)0x12000030)
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#define GS_SYNCH1 (*(volatile uint64*)0x12000040)
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#define GS_SYNCH2 (*(volatile uint64*)0x12000050)
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#define GS_SYNCV (*(volatile uint64*)0x12000060)
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#define GS_DISPFB1 (*(volatile uint64*)0x12000070)
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#define GS_DISPLAY1 (*(volatile uint64*)0x12000080)
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#define GS_DISPFB2 (*(volatile uint64*)0x12000090)
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#define GS_DISPLAY2 (*(volatile uint64*)0x120000a0)
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#define GS_EXTBUF (*(volatile uint64*)0x120000b0)
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#define GS_EXTDATA (*(volatile uint64*)0x120000c0)
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#define GS_EXTWRITE (*(volatile uint64*)0x120000d0)
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#define GS_BGCOLOR (*(volatile uint64*)0x120000e0)
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#define GS_CSR (*(volatile uint64*)0x12001000)
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#define GS_IMR (*(volatile uint64*)0x12001010)
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#define GS_BUSDIR (*(volatile uint64*)0x12001040)
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#define GS_SIGLBLID (*(volatile uint64*)0x12001080)
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