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https://github.com/hanwckf/immortalwrt-mt798x.git
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176 lines
6.0 KiB
Diff
176 lines
6.0 KiB
Diff
From f12dcaf65b9a780f0cc72e3b86479e71a59116f1 Mon Sep 17 00:00:00 2001
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From: Tianling Shen <cnsztl@gmail.com>
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Date: Thu, 31 Aug 2023 11:05:11 +0800
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Subject: [PATCH] Revert "ASoC: fsl_sai: Refine enable/disable TE/RE sequence
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in trigger()"
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This reverts commit 1b3d751045425ec38e1e68cd1d64da1856772144.
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---
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sound/soc/fsl/fsl_sai.c | 126 +++++++++++++---------------------------
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1 file changed, 41 insertions(+), 85 deletions(-)
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--- a/sound/soc/fsl/fsl_sai.c
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+++ b/sound/soc/fsl/fsl_sai.c
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@@ -37,24 +37,6 @@ static const struct snd_pcm_hw_constrain
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.list = fsl_sai_rates,
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};
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-/**
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- * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
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- *
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- * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
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- * or Receiver's for both streams. This function is used to check if clocks of
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- * the stream's are synced by the opposite stream.
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- *
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- * @sai: SAI context
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- * @dir: stream direction
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- */
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-static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
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-{
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- int adir = (dir == TX) ? RX : TX;
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-
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- /* current dir in async mode while opposite dir in sync mode */
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- return !sai->synchronous[dir] && sai->synchronous[adir];
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-}
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-
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static irqreturn_t fsl_sai_isr(int irq, void *devid)
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{
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struct fsl_sai *sai = (struct fsl_sai *)devid;
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@@ -541,38 +523,6 @@ static int fsl_sai_hw_free(struct snd_pc
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return 0;
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}
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-static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
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-{
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- unsigned int ofs = sai->soc_data->reg_offset;
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- bool tx = dir == TX;
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- u32 xcsr, count = 100;
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-
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- regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
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- FSL_SAI_CSR_TERE, 0);
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-
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- /* TERE will remain set till the end of current frame */
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- do {
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- udelay(10);
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- regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
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- } while (--count && xcsr & FSL_SAI_CSR_TERE);
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-
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- regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
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- FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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-
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- /*
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- * For sai master mode, after several open/close sai,
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- * there will be no frame clock, and can't recover
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- * anymore. Add software reset to fix this issue.
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- * This is a hardware bug, and will be fix in the
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- * next sai version.
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- */
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- if (!sai->is_slave_mode) {
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- /* Software Reset */
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- regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
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- /* Clear SR bit to finish the reset */
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- regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
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- }
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-}
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static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *cpu_dai)
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@@ -581,9 +531,7 @@ static int fsl_sai_trigger(struct snd_pc
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unsigned int ofs = sai->soc_data->reg_offset;
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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- int adir = tx ? RX : TX;
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- int dir = tx ? TX : RX;
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- u32 xcsr;
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+ u32 xcsr, count = 100;
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/*
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* Asynchronous mode: Clear SYNC for both Tx and Rx.
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@@ -606,22 +554,10 @@ static int fsl_sai_trigger(struct snd_pc
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regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
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FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
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- regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
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+ regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
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+ FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
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+ regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
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FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
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- /*
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- * Enable the opposite direction for synchronous mode
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- * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
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- * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
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- *
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- * RM recommends to enable RE after TE for case 1 and to enable
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- * TE after RE for case 2, but we here may not always guarantee
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- * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
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- * TE after RE, which is against what RM recommends but should
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- * be safe to do, judging by years of testing results.
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- */
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- if (fsl_sai_dir_is_synced(sai, adir))
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- regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
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- FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
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regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
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FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
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@@ -636,23 +572,43 @@ static int fsl_sai_trigger(struct snd_pc
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/* Check if the opposite FRDE is also disabled */
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regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
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-
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- /*
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- * If opposite stream provides clocks for synchronous mode and
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- * it is inactive, disable it before disabling the current one
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- */
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- if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
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- fsl_sai_config_disable(sai, adir);
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-
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- /*
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- * Disable current stream if either of:
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- * 1. current stream doesn't provide clocks for synchronous mode
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- * 2. current stream provides clocks for synchronous mode but no
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- * more stream is active.
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- */
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- if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
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- fsl_sai_config_disable(sai, dir);
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-
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+ if (!(xcsr & FSL_SAI_CSR_FRDE)) {
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+ /* Disable both directions and reset their FIFOs */
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+ regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
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+ FSL_SAI_CSR_TERE, 0);
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+ regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
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+ FSL_SAI_CSR_TERE, 0);
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+
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+ /* TERE will remain set till the end of current frame */
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+ do {
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+ udelay(10);
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+ regmap_read(sai->regmap,
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+ FSL_SAI_xCSR(tx, ofs), &xcsr);
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+ } while (--count && xcsr & FSL_SAI_CSR_TERE);
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+
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+ regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
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+ FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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+ regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
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+ FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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+
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+ /*
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+ * For sai master mode, after several open/close sai,
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+ * there will be no frame clock, and can't recover
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+ * anymore. Add software reset to fix this issue.
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+ * This is a hardware bug, and will be fix in the
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+ * next sai version.
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+ */
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+ if (!sai->is_slave_mode) {
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+ /* Software Reset for both Tx and Rx */
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+ regmap_write(sai->regmap, FSL_SAI_TCSR(ofs),
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+ FSL_SAI_CSR_SR);
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+ regmap_write(sai->regmap, FSL_SAI_RCSR(ofs),
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+ FSL_SAI_CSR_SR);
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+ /* Clear SR bit to finish the reset */
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+ regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
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+ regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
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+ }
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+ }
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break;
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default:
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return -EINVAL;
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