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https://github.com/hanwckf/immortalwrt-mt798x.git
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129 lines
3.7 KiB
Diff
129 lines
3.7 KiB
Diff
From 7240598ba4e6c477c6809dc019505cf366fdb7c0 Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Sat, 18 Jul 2020 00:00:51 +0800
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Subject: [PATCH] arm64: dts: allwinner: h5: Add CPU Operating Performance
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Points table
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Add an OPP (Operating Performance Points) table for the CPU cores for
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boards to include to DVFS (Dynamic Voltage & Frequency Scaling) on the
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H5. The table originates from Armbian, but the maximum voltage is raised
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slightly to account for boards using slightly higher voltages.
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The table and tie in to the CPU cores are put in a separate dtsi file
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that board files can include to opt in. Or they can define their own
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tables if the standard one does not fit.
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This has been tested on the Libre Computer ALL-H3-CC-H5 and the Bananapi
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M2+ v1.2 H5, both with adequate cooling. The former has a fixed 1.2V
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regulator, while the latter has a GPIO controlled regulator switchable
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between 1.1V and 1.3V.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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Link: https://lore.kernel.org/r/20200717160053.31191-7-wens@kernel.org
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---
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.../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 79 +++++++++++++++++++
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1 file changed, 79 insertions(+)
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create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
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@@ -0,0 +1,97 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
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+
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+/ {
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+ cpu_opp_table: cpu-opp-table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-408000000 {
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+ opp-hz = /bits/ 64 <408000000>;
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+ opp-microvolt = <1000000 1000000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-648000000 {
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+ opp-hz = /bits/ 64 <648000000>;
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+ opp-microvolt = <1040000 1040000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-816000000 {
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+ opp-hz = /bits/ 64 <816000000>;
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+ opp-microvolt = <1080000 1080000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-912000000 {
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+ opp-hz = /bits/ 64 <912000000>;
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+ opp-microvolt = <1120000 1120000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-960000000 {
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+ opp-hz = /bits/ 64 <960000000>;
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+ opp-microvolt = <1160000 1160000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <1200000 1200000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1056000000 {
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+ opp-hz = /bits/ 64 <1056000000>;
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+ opp-microvolt = <1240000 1240000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <1260000 1260000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1152000000 {
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+ opp-hz = /bits/ 64 <1152000000>;
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+ opp-microvolt = <1300000 1300000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1300000 1300000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1248000000 {
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+ opp-hz = /bits/ 64 <1248000000>;
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+ opp-microvolt = <1300000 1300000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp-1296000000 {
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+ opp-hz = /bits/ 64 <1296000000>;
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+ opp-microvolt = <1300000 1300000 1310000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+};
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+
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+&cpu0 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu1 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu2 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu3 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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