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https://github.com/hanwckf/immortalwrt-mt798x.git
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91 lines
2.2 KiB
Diff
91 lines
2.2 KiB
Diff
From d04f7bc8842c0d9951a5740480f864a4f82d6b63 Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Sat, 18 Jul 2020 00:00:50 +0800
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Subject: [PATCH] arm64: dts: allwinner: h5: Add trip and cooling maps to CPU
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thermal zones
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This enables passive cooling by down-regulating CPU voltage and frequency.
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The trip points were copied from the H3.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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Link: https://lore.kernel.org/r/20200717160053.31191-6-wens@kernel.org
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---
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arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 30 ++++++++++++++++++++
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1 file changed, 30 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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@@ -42,6 +42,8 @@
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#include <arm/sunxi-h3-h5.dtsi>
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+#include <dt-bindings/thermal/thermal.h>
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+
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/ {
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cpus {
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#address-cells = <1>;
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@@ -54,6 +56,7 @@
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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@@ -63,6 +66,7 @@
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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@@ -72,6 +76,7 @@
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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@@ -81,6 +86,7 @@
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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+ #cooling-cells = <2>;
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};
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};
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@@ -201,6 +207,30 @@
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&ths 0>;
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+
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+ trips {
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+ cpu_hot_trip: cpu-hot {
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+ temperature = <80000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ cpu_very_hot_trip: cpu-very-hot {
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+ temperature = <100000>;
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+ hysteresis = <0>;
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+ type = "critical";
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+ };
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+ };
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+
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+ cooling-maps {
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+ cpu-hot-limit {
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+ trip = <&cpu_hot_trip>;
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+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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};
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gpu_thermal {
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