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80 lines
2.9 KiB
Diff
80 lines
2.9 KiB
Diff
From 0bc68af9137dc3f30b161de4ce546c7799f88d1e Mon Sep 17 00:00:00 2001
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From: Shivamurthy Shastri <sshivamurthy@micron.com>
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Date: Wed, 11 Mar 2020 18:57:33 +0100
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Subject: [PATCH] mtd: spinand: micron: identify SPI NAND device with
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Continuous Read mode
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Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
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the Continuous Read mode.
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Some of the Micron SPI NAND devices have the "Continuous Read" feature
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enabled by default, which does not fit the subsystem needs.
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In this mode, the READ CACHE command doesn't require the starting column
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address. The device always output the data starting from the first
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column of the cache register, and once the end of the cache register
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reached, the data output continues through the next page. With the
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continuous read mode, it is possible to read out the entire block using
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a single READ command, and once the end of the block reached, the output
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pins become High-Z state. However, during this mode the read command
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doesn't output the OOB area.
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Hence, we disable the feature at probe time.
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Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
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Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Link: https://lore.kernel.org/linux-mtd/20200311175735.2007-5-sshivamurthy@micron.com
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---
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drivers/mtd/nand/spi/micron.c | 16 ++++++++++++++++
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include/linux/mtd/spinand.h | 1 +
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2 files changed, 17 insertions(+)
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diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
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index 26925714a9fbac..956f7710aca263 100644
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--- a/drivers/mtd/nand/spi/micron.c
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+++ b/drivers/mtd/nand/spi/micron.c
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@@ -18,6 +18,8 @@
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#define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
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#define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4)
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+#define MICRON_CFG_CR BIT(0)
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+
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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@@ -137,7 +139,21 @@ static const struct spinand_info micron_spinand_table[] = {
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micron_8_ecc_get_status)),
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};
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+static int micron_spinand_init(struct spinand_device *spinand)
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+{
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+ /*
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+ * M70A device series enable Continuous Read feature at Power-up,
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+ * which is not supported. Disable this bit to avoid any possible
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+ * failure.
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+ */
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+ if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT)
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+ return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0);
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+
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+ return 0;
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+}
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+
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static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
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+ .init = micron_spinand_init,
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};
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const struct spinand_manufacturer micron_spinand_manufacturer = {
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diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
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index f4c4ae87181b27..1077c45721ff25 100644
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--- a/include/linux/mtd/spinand.h
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+++ b/include/linux/mtd/spinand.h
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@@ -284,6 +284,7 @@ struct spinand_ecc_info {
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};
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#define SPINAND_HAS_QE_BIT BIT(0)
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+#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
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/**
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* struct spinand_info - Structure used to describe SPI NAND chips
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