mirror of
https://github.com/hanwckf/immortalwrt-mt798x.git
synced 2025-01-10 11:09:57 +08:00
29 lines
1.0 KiB
Diff
29 lines
1.0 KiB
Diff
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
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index c3d6756..d84c45d 100644
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--- a/drivers/clk/mediatek/clk-mtk.h
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+++ b/drivers/clk/mediatek/clk-mtk.h
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@@ -231,6 +231,7 @@ struct mtk_pll_data {
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uint32_t pcw_reg;
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int pcw_shift;
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uint32_t pcw_chg_reg;
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+ int pcw_chg_shift;
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const struct mtk_pll_div_table *div_table;
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const char *parent_name;
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};
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diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
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index f440f2c..db318fe 100644
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--- a/drivers/clk/mediatek/clk-pll.c
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+++ b/drivers/clk/mediatek/clk-pll.c
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@@ -136,7 +136,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
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pll->data->pcw_shift);
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val |= pcw << pll->data->pcw_shift;
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writel(val, pll->pcw_addr);
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- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
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+ if (pll->data->pcw_chg_shift)
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+ chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
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+ else
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+ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
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writel(chg, pll->pcw_chg_addr);
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if (pll->tuner_addr)
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writel(val + 1, pll->tuner_addr);
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