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34 lines
1.2 KiB
Diff
34 lines
1.2 KiB
Diff
From cea0f76a483d1270ac6f6513964e3e75193dda48 Mon Sep 17 00:00:00 2001
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From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
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Date: Mon, 29 Jun 2020 15:00:52 +0300
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Subject: [PATCH 3/5] dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR
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PHY
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Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
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Processing System Gigabit Transceiver which provides PHY capabilities to
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USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
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Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
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Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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include/dt-bindings/phy/phy.h | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
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index 3727ef72138b..36e8c241cf48 100644
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--- a/include/dt-bindings/phy/phy.h
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+++ b/include/dt-bindings/phy/phy.h
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@@ -18,5 +18,6 @@
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#define PHY_TYPE_UFS 5
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#define PHY_TYPE_DP 6
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#define PHY_TYPE_XPCS 7
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+#define PHY_TYPE_SGMII 8
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#endif /* _DT_BINDINGS_PHY */
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--
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2.18.0
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