Enable the AP806's cpufreq driver. This driver is compatible with the
Armada 7K and 8K platforms.
Tested-by: Stijn Segers <foss@volatilesystems.org> (RB5009UG+S+IN)
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
(cherry picked from commit 6f88526fa4e0aa5f60834d181d04f8a9911887be)
Since kernel 5.5-rc1 [1], there are upstreamed DTS files related to ESPRESSObin
variants. Move these to files-5.4.
This helps if you want to use a newer kernel version than used
in OpenWrt 21.02 (= LTS kernel 5.4), you would end up with duplicate files
(one outdated, one up to date from newer Linux versions).
Fixes:
Error: arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts:19.1-7:
Label or path ports not found
FATAL ERROR: Syntax error parsing input tree
[1] 447b878935
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
(cherry picked from commit 7be8ab4f7b582924bca6594103735d888989d804)
Signed-off-by: Josef Schlehofer <pepe.schlehofer@gmail.com>
[reword commit subject and commit description]
This enables armv8 crypto extensions version of AES, GHASH, SHA1,
SHA256, and SHA512 algorithms in the kernel.
The choice of algorithms match the 32-bit versions that are enabled in
the target config-5.10 file, but were only used by the cortexa9
subtarget.
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
(cherry picked from commit 06bb5ac1f2b62c3e10f24d7096e86f6368aaf41d)
This enables armv8 crypto extensions version of AES, GHASH, SHA1,
SHA256, and SHA512 algorithms in the kernel.
The choice of algorithms match the 32-bit versions that are enabled in
the target config-5.10 file, but were only used by the cortexa9
subtarget.
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
(cherry picked from commit f5167e11bf7e0a1a3675f0563423254005d0eb2d)
CONFIG_BLK_DEV_NVME [1]:
- This is a kernel driver for SSD connected to PCI or PCIe bus [1].
By default, it is enabled for targets "ipq807x", "rockchip/armv8"
and "x86/64".
With miniPCIe adapter, there is a possibility to connect NVMe disk
to Turris Omnia (cortex-a9), Turris MOX (cortex-a53).
It allows to boot system from NVMe disk, because of that it can not
be kmod package as you can not access the disk to be able to boot from
it.
CONFIG_NVME_CORE [2]:
- This is selected by CONFIG_BLK_DEV_NVME
It does not need to be explicitly enabled, but it is done for "ipq807",
"x64_64" and rockchip/armv8", which has also enabled the previous config
option as well.
Kernel increase: ~28k KiB on mamba kernel
Reference:
[1] https://cateee.net/lkddb/web-lkddb/BLK_DEV_NVME.html
[2] https://cateee.net/lkddb/web-lkddb/NVME_CORE.html
Signed-off-by: Josef Schlehofer <pepe.schlehofer@gmail.com>
(cherry picked from commit 9d530ac4bf6b9804a06dbf5df4631ee86f1304c1)
[rebased for config-5.4]
uDPU has 2 LM75 compatible temperature sensors, so include the driver for
them by default in order to utilize them.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Petr Štetiar <ynezz@true.cz> [rebase]
(cherry picked from commit a8b2d3590329386d0ae6873460b2d5126f63ddaa)
(cherry picked from commit b9e90935db8e0c0166c80fc6e5e50755282e9e0b)
uDPU provides a FIT based initramfs, but currently gets stuck after U-boot
starts the kernel at "Starting kernel..".
It is due to the load address being too low, so increase it in order to get
the initramfs booting again.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
(cherry picked from commit 80f21e53360d52d493c51a4a263d9b7607b7494e)
(cherry picked from commit d65269a732d82ca9d084c89d6ca05d125d4ab629)
Many changes were done in drivers/pinctrl/bcm/pinctrl-bcm2835.c between
5.4.171 and 5.4.179.
The following 3 patches do not apply any more:
* target/linux/bcm27xx/patches-5.4/950-0316-pinctrl-bcm2835-Add-support-for-BCM2711-pull-up-func.patch
This was already integrated in kernel v5.4-rc1, it was never needed.
* target/linux/bcm27xx/patches-5.4/950-0328-Revert-pinctrl-bcm2835-Pass-irqchip-when-adding-gpio.patch
* target/linux/bcm27xx/patches-5.4/950-0362-pinctrl-bcm2835-Change-init-order-for-gpio-hogs.patch
I think these were done to fix the problem which was really fixed in
commit 75278f1aff5e ("pinctrl: bcm2835: Change init order for gpio
hogs") from v5.4.175
target/linux/generic/backport-5.4/716-v5.5-net-sfp-move-fwnode-parsing-into-sfp-bus-layer.patch
Move fwnode_device_is_available to the same position as in kernel 5.10.
target/linux/layerscape/patches-5.4/302-dts-0083-arm64-ls1028a-qds-correct-bus-of-rtc.patch
Applied in commit 65816c1034769e714edb70f59a33bc5472d9e55f ("arm64: dts:
ls1028a-qds: move rtc node to the correct i2c bus")
Compile-tested: lantiq/xrx200, bcm27xx/bcm2710
Run-tested: lantiq/xrx200
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The patch
PCI: aardvark: Don't touch PCIe registers if no card connected
was applied into Linux stable version 5.4.163.
Remove it from patches-5.4.
(It applied even though it was applied already, resulting in repeated
code.)
Fixes: 14940aee4566 ("kernel: bump 5.4 to 5.4.163")
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Fix default network configuration of the Puzzle-M902 so all LAN ports
are included in the LAN bridge.
Setup network LED to indicate WAN port link status, like vendor
firmware does as well.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit f9782f5bcd13e419abf9c84017ada27fa9764011)
While on Linux 5.10 this fixes Ethernet link status on all ports and
makes 2.5G ports usable in 2.5G and 1G full-duplex mode, when using
Linux 5.4 and backported Aquantia phy patches, only 1G mode works on
the 2.5G ports and link speed and duplex are not reported correctly
from the phy in case of 2.5G.
The reasons are probably trivial, but hard to find. As having all
ports work at least in 1G speed instead of having them not work at
all is still better, push this anyway for now.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit f81a06408eec28d479f699bd762b703ac65e2150)
Copy and refresh patch enabling AQR112 and AQR412 Ethernet PHY from
layerscape (5.4) target to mvebu (5.4) as AQR112 can also be found
in IEI Puzzle devices.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Wire up MCU driver for LEDs, fan and temperature sensor, and add
GPIO reset button just like on the M902 also on the Puzzle M901.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 3684b494ddd540b811de44497f0d11309bfd1911)
Add reset button to device tree so it has the function expected from
usual OpenWrt devices.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit ddad936fc60ced1783232af3eddee75347f0d08f)
Set blinking mode using scheduled work instead of blocking which may
result in deadlocks.
Add dynamic kprintf debugging hexdumps of all MCU rx and tx.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 7e4c1cca8a137ca4fe5132b8c058e52ba82defac)
Backport MFD driver for communicating with the on-board MCU found on
IEI World Puzzle appliances.
Improve the driver to support multiple LEDs, apply a default state and
let MCU take care of blinking if timing is within supported range.
Wire up LEDs and fan for Puzzle M902 in device tree.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit f0c0b18234418c6ed6d35fcf1c6e5b0cbdceed49
with commit 962c58558010bd302793ac24284c4f9db8fe287f squashed)
Follow the recommendations stated in the Turris Omnia DTS for eth2:
"In case SFP module is present, U-Boot has to enable the sfp node above,
remove phy-handle property, and add managed = "in-band-status" property."
The boot script is written in a way, that it works for all U-Boot
versions deployed by the vendor so far (2015.10-rc2, 2019.07).
Reviewed-by: Noci <noci@noci.work>
Reviewed-by: Justin van Steijn <jvs@fsfe.org>
Reviewed-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-by: Julius Schwartzenberg <julius.schwartzenberg@gmail.com>
Signed-off-by: Klaus Kudielka <klaus.kudielka@gmail.com>
(cherry picked from commit 23d2690e5a5410576b587bc96e2c2cf5fc693927)
Kernel 5.4 receives a reduced set, just to make the SFP cage work.
While we are at it, move the patches accepted upstream to the 0xx series.
Reviewed-by: Noci <noci@noci.work>
Reviewed-by: Justin van Steijn <jvs@fsfe.org>
Reviewed-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-by: Julius Schwartzenberg <julius.schwartzenberg@gmail.com>
Signed-off-by: Klaus Kudielka <klaus.kudielka@gmail.com>
(cherry picked from commit 8138cb8737d1475e6e8d57393500f30384e75a82)
All updated automatically.
Compile-tested on: lantiq/xrx200, armvirt/64
Runtime-tested on: lantiq/xrx200, armvirt/64
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Removed upstreamed:
target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch
target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch
target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch
target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch
target/linux/mvebu/patches-5.4/020-arm64-dts-marvell-armada-37xx-Set-pcie_reset_pin-to-.patch
The following patch does not apply to upstream any more and needs some
more work to make it work fully again. I am not sure if we are still
able to set the UART to a none standard baud rate.
target/linux/ath79/patches-5.4/921-serial-core-add-support-for-boot-console-with-arbitr.patch
These patches needed manually changes:
target/linux/generic/pending-5.4/110-ehci_hcd_ignore_oc.patch
target/linux/ipq806x/patches-5.4/0065-arm-override-compiler-flags.patch
target/linux/layerscape/patches-5.4/804-crypto-0016-MLKU-114-1-crypto-caam-reduce-page-0-regs-access-to-.patch
target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch
target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch
All others updated automatically.
Compile-tested on: malta/le, armvirt/64, lantiq/xrx200
Runtime-tested on: malta/le, armvirt/64, lantiq/xrx200
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
1. Add support for Marvell CN9130 SoC
2. Add support for CP115,and create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115
3. Add support for AP807/AP807-quad,AP807 is a major component of CN9130 SoC series
4. Drop PCIe I/O ranges from CP11x file and externalize PCIe macros from CP11x file
Signed-off-by: Ian Chang <ianchang@ieiworld.com>
(cherry picked from commit c98ddf0f019986bbb4c868bfcaf97e0d1f4ee2dc)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
