When the membase and pci_dev pointer were moved to a new struct in priv,
the actual membase users were left untouched, and they started reading
out arbitrary memory behind the struct instead of registers. This
unfortunately turned the RNG into a constant number generator, depending
on the content of what was at that offset.
To fix this, update geode_rng_data_{read,present}() to also get the
membase via amd_geode_priv, and properly read from the right addresses
again.
Closes#13417.
Reported-by: Timur I. Davletshin <timur.davletshin@gmail.com>
Tested-by: Timur I. Davletshin <timur.davletshin@gmail.com>
Suggested-by: Jo-Philipp Wich <jo@mein.io>
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
(cherry picked from commit 09d13cd8d87cc50fde67bbe81c6cca4b799b2724)
Add spinlock mechanism for mtk_rmw api.
1. When multiple threads operate on the same register resource
which include multiple pins, it will make the register resource
wrong to control. So we add spinlock to avoid this case.
[Release-log]
This patch adds spinlock mechanism to protect mtk_rmw. Without it,
you may suffer from some unexpected problems such as race conidtion
while interrupt occured. And this will lead to pin setting fail.
Hence, we strongly recommand you to merge this patch in your code
base.
Change-Id: I1128dc16cb683b89c2cd9f9138f32552abb00400
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7962757
Add solution of CH395, which is an ethernet IC chip
from WCH company, to dsa, gsw for mt7981, mt7986.
1. For dsa, CR will be written in mediatek_ge.c
2. For gsw, CR will be written in mt7531.c
3. Enable mt7986 mediatek_ge.c config
[Release-log]
This patch will adjust RX min/max gain. Without this patch,
it may cause a link up fail for CH395 chip under 100Mbps.
In order to enhance the stability of your products,
it's better to merge this patch in your codebase.
Change-Id: If07b4ffc060defb5460ecf98339c1cdd3520a128
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7858068
Fix the conditions for adding vlan info.
When eth1.x -> wifi, packets cannot be forwarded through the HW path.
(due to with wrong HNAT vlan info)
The patch fix it.
[Release-log]
N/A
Change-Id: Id9e02493157bfc2f3a4dbf046be127cd491f9b17
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7778652
[Description]
Fix log print level in foe_clear_entry.
There are too many logs when neighbor update,
the logs should be printed on debug level.
[Release-log]
N/A
Change-Id: Ic9b75aa5da33f1ab1f398408811487f72ba9f29b
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7709249
Those sort out BCM53573 Ethernet info finally.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
(cherry picked from commit ca8868a51127f6081a524d47eab937b90af0bf05)
It seems that DSA-based b53 driver never worked with BCM53573 SoCs and
BCM53125.
In case of swconfig-based b53 this fixes a regression. Switching bgmac
from using mdiobus_register() to of_mdiobus_register() resulted in MDIO
device (BCM53125) having of_node set (see of_mdiobus_register_phy()).
That made downstream b53 driver read invalid data from DT and broke
Ethernet support.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
(cherry picked from commit 79fd3e62b4910731c13692b2daa2083e0f95c023)
