Backups/immortalwrt-mt798x
1
0
Fork 0
mirror of https://github.com/hanwckf/immortalwrt-mt798x.git synced 2025-01-07 01:53:34 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

mediatek: mtk_eth_soc: change mt798x adma from v2 to v1

Browse Source
This commit is contained in:
hanwckf 2024-01-18 23:33:54 +08:00
parent f7aecec1da
commit fcbff49bcc
6 changed files with 84 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c
View File

@ -749,7 +749,7 @@ int rx_ring_read(struct seq_file *seq, void *v)
seq_printf(seq, "%d: %08x %08x %08x %08x", i,
*(int *)&rx_ring[i].rxd1, *(int *)&rx_ring[i].rxd2,
*(int *)&rx_ring[i].rxd3, *(int *)&rx_ring[i].rxd4);
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
seq_printf(seq, " %08x %08x %08x %08x",
*(int *)&rx_ring[i].rxd5, *(int *)&rx_ring[i].rxd6,
*(int *)&rx_ring[i].rxd7, *(int *)&rx_ring[i].rxd8);
@ -906,7 +906,7 @@ void hw_lro_stats_update(u32 ring_no, struct mtk_rx_dma *rxd)
{
u32 idx, agg_cnt, agg_size;
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
idx = ring_no - 4;
agg_cnt = RX_DMA_GET_AGG_CNT_V2(rxd->rxd6);
#else
@ -926,7 +926,7 @@ void hw_lro_flush_stats_update(u32 ring_no, struct mtk_rx_dma *rxd)
{
u32 idx, flush_reason;
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
idx = ring_no - 4;
flush_reason = RX_DMA_GET_FLUSH_RSN_V2(rxd->rxd6);
#else
@ -1173,7 +1173,7 @@ int hw_lro_stats_read_wrapper(struct seq_file *seq, void *v)
{
struct mtk_eth *eth = g_eth;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2))
hw_lro_stats_read_v2(seq, v);
else
hw_lro_stats_read_v1(seq, v);
@ -1444,7 +1444,7 @@ int hw_lro_auto_tlb_read(struct seq_file *seq, void *v)
seq_puts(seq, "[4] = hwlro_ring_enable_ctrl\n");
seq_puts(seq, "[5] = hwlro_stats_enable_ctrl\n\n");
if (MTK_HAS_CAPS(g_eth->soc->caps, MTK_NETSYS_V2)) {
if (MTK_HAS_CAPS(g_eth->soc->caps, MTK_NETSYS_RX_V2)) {
for (i = 1; i <= 8; i++)
hw_lro_auto_tlb_dump_v2(seq, i);
} else {
@ -1480,7 +1480,8 @@ int hw_lro_auto_tlb_read(struct seq_file *seq, void *v)
((reg_op1 >> MTK_LRO_RING_AGE_TIME_L_OFFSET) & 0x3ff);
seq_printf(seq,
"Ring[%d]: MAX_AGG_CNT=%d, AGG_TIME=%d, AGE_TIME=%d, Threshold=%d\n",
(MTK_HAS_CAPS(g_eth->soc->caps, MTK_NETSYS_V2))? i+3 : i,
(MTK_HAS_CAPS(g_eth->soc->caps, MTK_NETSYS_RX_V2)) ?
i : i+3,
agg_cnt, agg_time, age_time, reg_op4);
}

36
target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
View File

@ -834,7 +834,7 @@ static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd,
rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
#endif
@ -1403,8 +1403,8 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
mac = 0;
} else {
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2))
mac = RX_DMA_GET_SPORT(trxd.rxd5) - 1;
else
#endif
@ -1456,9 +1456,9 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
skb->dev = netdev;
skb_put(skb, pktlen);
if ((!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) &&
if ((!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2) &&
(trxd.rxd4 & eth->rx_dma_l4_valid)) ||
(MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) &&
(MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2) &&
(trxd.rxd3 & eth->rx_dma_l4_valid)))
skb->ip_summed = CHECKSUM_UNNECESSARY;
else
@ -1466,7 +1466,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
skb->protocol = eth_type_trans(skb, netdev);
if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2)) {
if (trxd.rxd3 & RX_DMA_VTAG_V2)
__vlan_hwaccel_put_tag(skb,
htons(RX_DMA_VPID_V2(trxd.rxd4)),
@ -1489,8 +1489,8 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
}
#if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE)
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2))
*(u32 *)(skb->head) = trxd.rxd5;
else
#endif
@ -1924,7 +1924,7 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
ring->dma[i].rxd3 = 0;
ring->dma[i].rxd4 = 0;
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
if (eth->soc->has_sram && ((sizeof(struct mtk_rx_dma)) > 16)) {
ring->dma[i].rxd5 = 0;
ring->dma[i].rxd6 = 0;
@ -2041,7 +2041,7 @@ static int mtk_hwlro_rx_init(struct mtk_eth *eth)
/* the minimal remaining room of SDL0 in RXD for lro aggregation */
lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2)) {
val = mtk_r32(eth, MTK_PDMA_RX_CFG);
mtk_w32(eth, val | (MTK_PDMA_LRO_SDL << MTK_RX_CFG_SDL_OFFSET),
MTK_PDMA_RX_CFG);
@ -2097,7 +2097,7 @@ static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
{
u32 reg_val;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2))
idx += 1;
reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
@ -2115,7 +2115,7 @@ static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
{
u32 reg_val;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2))
idx += 1;
reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
@ -2249,7 +2249,7 @@ static int mtk_rss_init(struct mtk_eth *eth)
{
u32 val;
if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2)) {
/* Set RSS rings to PSE modes */
val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(1));
val |= MTK_RING_PSE_MODE;
@ -2422,7 +2422,7 @@ static int mtk_dma_init(struct mtk_eth *eth)
return err;
if (eth->hwlro) {
i = (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ? 4 : 1;
i = (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2)) ? 4 : 1;
for (; i < MTK_MAX_RX_RING_NUM; i++) {
err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
if (err)
@ -2607,7 +2607,7 @@ static int mtk_start_dma(struct mtk_eth *eth)
MTK_PDMA_GLO_CFG);
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && eth->hwlro) {
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2) && eth->hwlro) {
val = mtk_r32(eth, MTK_PDMA_GLO_CFG);
mtk_w32(eth, val | MTK_RX_DMA_LRO_EN, MTK_PDMA_GLO_CFG);
}
@ -2891,7 +2891,7 @@ static int mtk_hw_init(struct mtk_eth *eth, u32 type)
else
mtk_eth_cold_reset(eth);
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2)) {
/* Set FE to PDMAv2 if necessary */
mtk_w32(eth, mtk_r32(eth, MTK_FE_GLO_MISC) | MTK_PDMA_V2, MTK_FE_GLO_MISC);
}
@ -3859,7 +3859,7 @@ static const struct mtk_soc_data mt7986_data = {
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7986_CLKS_BITMAP,
.required_pctl = false,
.has_sram = true,
.has_sram = false,
};
static const struct mtk_soc_data mt7981_data = {
@ -3868,7 +3868,7 @@ static const struct mtk_soc_data mt7981_data = {
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7981_CLKS_BITMAP,
.required_pctl = false,
.has_sram = true,
.has_sram = false,
};
static const struct mtk_soc_data rt5350_data = {

31
target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
View File

@ -143,7 +143,11 @@
#define MTK_PDMA_V2 BIT(4)
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
#define PDMA_BASE 0x6000
#else
#define PDMA_BASE 0x4000
#endif
#define QDMA_BASE 0x4400
#define WDMA_BASE(x) (0x4800 + ((x) * 0x400))
#define PPE_BASE(x) (0x2200 + ((x) * 0x400))
@ -171,7 +175,7 @@
/* PDMA HW LRO Control Registers */
#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
#define MTK_MAX_RX_RING_NUM (8)
#define MTK_HW_LRO_RING_NUM (4)
#define IS_HW_LRO_RING(ring_no) (((ring_no) > 3) && ((ring_no) < 8))
@ -215,14 +219,14 @@
#define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
/* PDMA RSS Control Registers */
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
#define MTK_PDMA_RSS_GLO_CFG (PDMA_BASE + 0x800)
#define MTK_RX_NAPI_NUM (2)
#define MTK_MAX_IRQ_NUM (4)
#else
#define MTK_PDMA_RSS_GLO_CFG 0x3000
#define MTK_RX_NAPI_NUM (1)
#define MTK_MAX_IRQ_NUM (3)
#define MTK_PDMA_RSS_GLO_CFG 0x2800
#define MTK_RX_NAPI_NUM (2)
#define MTK_MAX_IRQ_NUM (4)
#endif
#define MTK_RSS_RING1 (1)
#define MTK_RSS_EN BIT(0)
@ -274,7 +278,7 @@
/* PDMA Interrupt grouping registers */
#define MTK_PDMA_INT_GRP1 (PDMA_BASE + 0x250)
#define MTK_PDMA_INT_GRP2 (PDMA_BASE + 0x254)
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
#define MTK_PDMA_INT_GRP3 (PDMA_BASE + 0x258)
#else
#define MTK_PDMA_INT_GRP3 (PDMA_BASE + 0x22c)
@ -283,7 +287,7 @@
#define MTK_MAX_DELAY_INT 0x8f0f8f0f
/* PDMA HW LRO IP Setting Registers */
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
#define MTK_LRO_RX_RING0_DIP_DW0 (PDMA_BASE + 0x414)
#else
#define MTK_LRO_RX_RING0_DIP_DW0 (PDMA_BASE + 0x304)
@ -399,12 +403,13 @@
/* QDMA Interrupt Status Register */
#define MTK_QDMA_INT_STATUS (QDMA_BASE + 0x218)
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
#define MTK_RX_DONE_INT(ring_no) \
((ring_no)? BIT(16 + (ring_no)) : BIT(14))
#else
#define MTK_RX_DONE_INT(ring_no) \
((ring_no)? BIT(24 + (ring_no)) : BIT(30))
#define MTK_RX_DONE_INT(ring_no) \
(MTK_HAS_CAPS(eth->soc->caps, MTK_RSS) ? ((ring_no) ? BIT(24 + (ring_no)) : BIT(30)) : \
(BIT(16 + (ring_no))))
#endif
#define MTK_RX_DONE_INT3 BIT(19)
#define MTK_RX_DONE_INT2 BIT(18)
@ -501,7 +506,7 @@
#define MTK_TX_DMA_BUF_SHIFT 16
#endif
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
#define MTK_RX_DMA_BUF_LEN 0xffff
#define MTK_RX_DMA_BUF_SHIFT 8
#define RX_DMA_SPORT_SHIFT 26
@ -792,7 +797,7 @@ struct mtk_rx_dma {
unsigned int rxd2;
unsigned int rxd3;
unsigned int rxd4;
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
unsigned int rxd5;
unsigned int rxd6;
unsigned int rxd7;
@ -1041,6 +1046,7 @@ enum mkt_eth_capabilities {
MTK_TRGMII_MT7621_CLK_BIT,
MTK_QDMA_BIT,
MTK_NETSYS_V2_BIT,
MTK_NETSYS_RX_V2_BIT,
MTK_SOC_MT7628_BIT,
MTK_RSTCTRL_PPE1_BIT,
MTK_U3_COPHY_V2_BIT,
@ -1077,6 +1083,7 @@ enum mkt_eth_capabilities {
#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
#define MTK_QDMA BIT(MTK_QDMA_BIT)
#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
#define MTK_NETSYS_RX_V2 BIT(MTK_NETSYS_RX_V2_BIT)
#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)

24
target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_hnat/hnat.h
View File

@ -593,15 +593,6 @@ struct foe_entry {
};
};
/* If user wants to change default FOE entry number, both DEF_ETRY_NUM and
* DEF_ETRY_NUM_CFG need to be modified.
*/
#define DEF_ETRY_NUM 32768
/* feasible values : 32768, 16384, 8192, 4096, 2048, 1024 */
#define DEF_ETRY_NUM_CFG TABLE_32K
/* corresponding values : TABLE_32K, TABLE_16K, TABLE_8K, TABLE_4K, TABLE_2K,
* TABLE_1K
*/
#define MAX_EXT_DEVS (0x3fU)
#define MAX_IF_NUM 64
#define MAX_EXT_PREFIX_NUM 8
@ -743,6 +734,21 @@ enum FoeIpAct {
#define HASH_MODE_2 2
#define HASH_MODE_3 3
/* If user wants to change default FOE entry number, both DEF_ETRY_NUM and
* DEF_ETRY_NUM_CFG need to be modified.
*/
#define DEF_ETRY_NUM 16384
/* feasible values : 32768, 16384, 8192, 4096, 2048, 1024 */
#define DEF_ETRY_NUM_CFG TABLE_16K
/* corresponding values : TABLE_32K, TABLE_16K, TABLE_8K, TABLE_4K, TABLE_2K,
* TABLE_1K
*/
#if !defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
#if (DEF_ETRY_NUM > 16384) || (DEF_ETRY_NUM_CFG == TABLE_32K)
#error "ppe entry num cfg error"
#endif
#endif
/*PPE_FLOW_CFG*/
#define BIT_FUC_FOE BIT(2)
#define BIT_FMC_FOE BIT(1)

8
target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_hnat/nf_hnat_mtk.h
View File

@ -23,7 +23,7 @@ struct hnat_skb_cb2 {
__u32 magic;
};
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
struct hnat_desc {
u32 entry : 15;
u32 filled : 3;
@ -46,13 +46,13 @@ struct hnat_desc {
u32 crsn : 5;
u32 sport : 4;
u32 alg : 1;
u32 iface : 4;
u32 iface : 8;
u32 ppe : 1;
u32 filled : 3;
u32 resv : 1;
u32 magic_tag_protect : 16;
u32 wdmaid : 8;
u32 rxid : 2;
u32 wcid : 8;
u32 wcid : 10;
u32 bssid : 6;
} __packed;
#endif

23
target/linux/mediatek/files-5.4/include/net/ra_nat.h Executable file → Normal file
View File

@ -130,7 +130,7 @@ struct dmad_rx_descinfo4 {
uint16_t rsv2:7;
u16 MAGIC_TAG_PROTECT;
} __packed;
#else
#elif defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
struct dmad_rx_descinfo4 {
uint32_t foe_entry_num:15;
uint32_t rsv0:3;
@ -151,6 +151,25 @@ struct dmad_rx_descinfo4 {
uint16_t rsv4:4;
u16 MAGIC_TAG_PROTECT;
} __packed;
#else
struct dmad_rx_descinfo4 {
uint32_t foe_entry_num:14;
uint32_t CRSN:5;
uint32_t SPORT:4;
uint32_t ALG:1;
uint32_t IF:8;
uint32_t ppe:1;
uint32_t rsv2:3;
uint32_t MAGIC_TAG_PROTECT: 16;
uint32_t WDMAID:8;
uint32_t RXID:2;
uint32_t WCID:10;
uint32_t BSSID:6;
#if defined(CONFIG_RA_HW_NAT_PPTP_L2TP)
u16 SOURCE;
u16 DEST;
#endif
} __packed;
#endif
struct pdma_rx_desc_info4 {
@ -178,7 +197,7 @@ struct pdma_rx_desc_info4 {
#endif
} __packed;
#if defined(CONFIG_MEDIATEK_NETSYS_V2)
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2)
struct head_rx_descinfo4 {
uint32_t foe_entry_num:14;
uint32_t CRSN:5;