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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2022-04-22 09:16:00 +08:00
commit d7c98b6ebb
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
63 changed files with 543 additions and 318 deletions
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47
package/kernel/mac80211/patches/ath/580-ath9k_ar9561_fix_bias_level.patch Normal file
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@ -0,0 +1,47 @@
From 4509e523dba46f789377cfec6f20579adf743416 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thibaut=20VAR=C3=88NE?= <hacks+kernel@slashdirt.org>
Date: Sun, 17 Apr 2022 11:31:35 +0200
Subject: [PATCH v2] ath9k: fix QCA9561 PA bias level
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch fixes an invalid TX PA DC bias level on QCA9561, which
results in a very low output power and very low throughput as devices
are further away from the AP (compared to other 2.4GHz APs).
This patch was suggested by Felix Fietkau, who noted[1]:
"The value written to that register is wrong, because while the mask
definition AR_CH0_TOP2_XPABIASLVL uses a different value for 9561, the
shift definition AR_CH0_TOP2_XPABIASLVL_S is hardcoded to 12, which is
wrong for 9561."
In real life testing, without this patch the 2.4GHz throughput on
Yuncore XD3200 is around 10Mbps sitting next to the AP, and closer to
practical maximum with the patch applied.
[1] https://lore.kernel.org/all/91c58969-c60e-2f41-00ac-737786d435ae@nbd.name
Signed-off-by: Thibaut VARÈNE <hacks+kernel@slashdirt.org>
---
v2: Adjust #define per Felix's suggestion
---
drivers/net/wireless/ath/ath9k/ar9003_phy.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index a171dbb29..ad949eb02 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -720,7 +720,7 @@
#define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : \
(AR_SREV_9462(ah) ? 0x16290 : 0x16284))
#define AR_CH0_TOP2_XPABIASLVL (AR_SREV_9561(ah) ? 0x1e00 : 0xf000)
-#define AR_CH0_TOP2_XPABIASLVL_S 12
+#define AR_CH0_TOP2_XPABIASLVL_S (AR_SREV_9561(ah) ? 9 : 12)
#define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \
((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16298 : \
--
2.30.2

19
package/libs/wolfssl/patches/400-wolfcrypt-src-port-devcrypto-devcrypto_aes.c-remove-.patch Normal file
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@ -0,0 +1,19 @@
From 096889927d9528d4fbeb3aab56d1fe8225d2e7ec Mon Sep 17 00:00:00 2001
From: Daniel Pouzzner <douzzer@wolfssl.com>
Date: Thu, 14 Apr 2022 20:23:31 -0500
Subject: [PATCH] wolfcrypt/src/port/devcrypto/devcrypto_aes.c: remove
redundant "int ret" in wc_AesCtrEncrypt() (supersedes #5052).
diff --git a/wolfcrypt/src/port/devcrypto/devcrypto_aes.c b/wolfcrypt/src/port/devcrypto/devcrypto_aes.c
index 3bc1d5bb1..28e145e27 100644
--- a/wolfcrypt/src/port/devcrypto/devcrypto_aes.c
+++ b/wolfcrypt/src/port/devcrypto/devcrypto_aes.c
@@ -208,7 +208,6 @@ int wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
int ret;
struct crypt_op crt;
byte* tmp;
- int ret;
if (aes == NULL || out == NULL || in == NULL) {
return BAD_FUNC_ARG;

2
target/linux/generic/config-5.4
View File

@ -3148,6 +3148,8 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_MPL115_SPI is not set
# CONFIG_MPL3115 is not set
# CONFIG_MPLS is not set
# CONFIG_MPLS_IPTUNNEL is not set
# CONFIG_MPLS_ROUTING is not set
# CONFIG_MPU3050_I2C is not set
# CONFIG_MQ_IOSCHED_DEADLINE is not set
# CONFIG_MQ_IOSCHED_KYBER is not set

5
target/linux/mvebu/config-5.4
View File

@ -75,6 +75,7 @@ CONFIG_ATAGS=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NVME=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_SCSI_REQUEST=y
@ -361,6 +362,10 @@ CONFIG_NLS=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVME_CORE=y
# CONFIG_NVME_HWMON is not set
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_TCP is not set
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y

4
target/linux/ramips/dts/mt7620a_alfa-network_ac1200rm.dts
View File

@ -72,10 +72,6 @@
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};
&ohci {
status = "okay";
};

4
target/linux/ramips/dts/mt7620a_alfa-network_r36m-e4g.dts
View File

@ -141,10 +141,6 @@
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};
&i2c {
status = "okay";
};

4
target/linux/ramips/dts/mt7620a_alfa-network_tube-e4g.dts
View File

@ -114,10 +114,6 @@
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};
&ohci {
status = "okay";
};

3
target/linux/ramips/dts/mt7620a_asus_rp-n53.dts
View File

@ -153,8 +153,7 @@
};
};
&gsw {
mediatek,port4 = "ephy";
&ethernet {
pinctrl-names = "default";
pinctrl-0 = <&ephy_pins>;
};

4
target/linux/ramips/dts/mt7620a_buffalo_whr-1166d.dts
View File

@ -157,10 +157,6 @@
};
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

4
target/linux/ramips/dts/mt7620a_buffalo_whr-300hp2.dts
View File

@ -144,10 +144,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
pinctrl-names = "default";

4
target/linux/ramips/dts/mt7620a_buffalo_whr-600d.dts
View File

@ -144,10 +144,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

4
target/linux/ramips/dts/mt7620a_cameo_810.dtsi
View File

@ -132,10 +132,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&gpio2 {
status = "okay";
};

4
target/linux/ramips/dts/mt7620a_dlink_dch-m225.dts
View File

@ -171,10 +171,6 @@
mtd-mac-address = <&factory 0x4>;
};
&gsw {
ralink,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
pinctrl-names = "default";

4
target/linux/ramips/dts/mt7620a_dlink_dir-510l.dts
View File

@ -120,10 +120,6 @@
};
};
&gsw {
mediatek,port4 = "ephy";
};
&state_default {
default {
groups = "i2c", "uartf";

3
target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts
View File

@ -185,5 +185,6 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};

4
target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts
View File

@ -173,6 +173,6 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,ephy-base-address = /bits/ 16 < 2 >;
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <2>;
};

3
target/linux/ramips/dts/mt7620a_dovado_tiny-ac.dts
View File

@ -135,7 +135,8 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&pcie {

2
target/linux/ramips/dts/mt7620a_edimax_br-6478ac-v2.dts
View File

@ -178,7 +178,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,ephy-base = /bits/ 8 <12>;
};
&wmac {

2
target/linux/ramips/dts/mt7620a_edimax_ew-7478apc.dts
View File

@ -170,7 +170,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,ephy-base = /bits/ 8 <12>;
};
&wmac {

4
target/linux/ramips/dts/mt7620a_edimax_ew-747x.dtsi
View File

@ -155,8 +155,6 @@
mtd-mac-address = <&factory 0x4>;
mediatek,mdio-mode = <1>;
phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
phy-reset-duration = <30>;
@ -202,7 +200,7 @@
};
&gsw {
mediatek,port5 = "gmac";
mediatek,ephy-base = /bits/ 8 <8>;
};
&wmac {

7
target/linux/ramips/dts/mt7620a_engenius_esr600.dts
View File

@ -144,7 +144,6 @@
mdio-bus {
status = "okay";
mediatek,mdio-mode;
ethernet-phy@0 {
reg = <0>;
@ -155,11 +154,15 @@
0x7c 0x0000007e /* PORT0 STATUS */
0x0c 0x05600000 /* PORT6 PAD MODE CTRL */
0x94 0x0000007e /* PORT6 STATUS */
>;
>;
};
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <8>;
};
&state_default {
gpio {
groups = "i2c", "uartf", "nd_sd", "wled";

3
target/linux/ramips/dts/mt7620a_fon_fon2601.dts
View File

@ -136,7 +136,8 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&wmac {

5
target/linux/ramips/dts/mt7620a_head-weblink_hdrm200.dts
View File

@ -149,6 +149,11 @@
};
};
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

4
target/linux/ramips/dts/mt7620a_iodata_wn-ac1167gr.dts
View File

@ -184,6 +184,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&state_default {
gpio {
groups = "i2c", "uartf";

4
target/linux/ramips/dts/mt7620a_iptime_a1004ns.dts
View File

@ -101,3 +101,7 @@
};
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};

27
target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts
View File

@ -115,9 +115,8 @@
mdio-bus {
status = "okay";
mediatek,mdio-mode = <1>;
phy0: ethernet-phy@0 {
ethernet-phy@0 {
reg = <0>;
phy-mode = "rgmii";
qca,ar8327-initvals = <
@ -127,29 +126,13 @@
0x94 0x00000000 /* PORT6_STATUS */
>;
};
phy1: ethernet-phy@1 {
reg = <1>;
phy-mode = "rgmii";
};
phy2: ethernet-phy@2 {
reg = <2>;
phy-mode = "rgmii";
};
phy3: ethernet-phy@3 {
reg = <3>;
phy-mode = "rgmii";
};
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii";
};
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <8>;
};
&pcie {
status = "okay";
};

4
target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts
View File

@ -135,6 +135,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

3
target/linux/ramips/dts/mt7620a_lenovo_newifi-y1s.dts
View File

@ -111,5 +111,6 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};

2
target/linux/ramips/dts/mt7620a_linksys_e1700.dts
View File

@ -145,7 +145,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,ephy-base = /bits/ 8 <12>;
};
&wmac {

4
target/linux/ramips/dts/mt7620a_netis_wf2770.dts
View File

@ -142,6 +142,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&pcie {
status = "okay";
};

4
target/linux/ramips/dts/mt7620a_ohyeah_oy-0001.dts
View File

@ -103,10 +103,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

4
target/linux/ramips/dts/mt7620a_planex_cs-qr10.dts
View File

@ -122,10 +122,6 @@
mediatek,portmap = "llllw";
};
&gsw {
ralink,port4 = "ephy";
};
&sdhci {
status = "okay";
};

4
target/linux/ramips/dts/mt7620a_planex_db-wrt01.dts
View File

@ -94,10 +94,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

4
target/linux/ramips/dts/mt7620a_planex_mzk-750dhp.dts
View File

@ -114,10 +114,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

3
target/linux/ramips/dts/mt7620a_ralink_mt7620a-evb.dts
View File

@ -105,7 +105,8 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&sdhci {

2
target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7530-evb.dts
View File

@ -100,7 +100,7 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,ephy-base = /bits/ 8 <12>;
};
&pcie {

4
target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7610e-evb.dts
View File

@ -71,10 +71,6 @@
mediatek,portmap = "llllw";
};
&gsw {
mediatek,port4 = "ephy";
};
&sdhci {
status = "okay";
};

3
target/linux/ramips/dts/mt7620a_ralink_mt7620a-v22sg-evb.dts
View File

@ -99,7 +99,8 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&pcie {

3
target/linux/ramips/dts/mt7620a_sercomm_na930.dts
View File

@ -166,7 +166,8 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&ehci {

4
target/linux/ramips/dts/mt7620a_tplink_archer-mr200.dts
View File

@ -178,10 +178,6 @@
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&radio 0x0>;
};

4
target/linux/ramips/dts/mt7620a_tplink_archer.dtsi
View File

@ -105,10 +105,6 @@
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&radio 0x0>;
};

3
target/linux/ramips/dts/mt7620a_tplink_re210-v1.dts
View File

@ -61,7 +61,8 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&ethernet {

211
target/linux/ramips/dts/mt7620a_wavlink_wl-wn579x3.dts Normal file
View File

@ -0,0 +1,211 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "mt7620a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "wavlink,wl-wn579x3", "ralink,mt7620a-soc";
model = "Wavlink WL-WN579X3";
aliases {
led-boot = &led_wps;
led-failsafe = &led_wps;
led-running = &led_wps;
led-upgrade = &led_wps;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
switch_aps {
label = "mode_aps";
gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
linux,code = <BTN_1>;
linux,input-type = <EV_SW>;
};
switch_repeater {
label = "mode_repeater";
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
};
};
leds {
compatible = "gpio-leds";
led_wps: wps {
label = "blue:wps";
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
};
lan {
label = "blue:lan";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
};
wan {
label = "blue:wan";
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
};
wifi {
label = "blue:wifi";
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
};
/* These three form the signal wifi strength segments */
wifi_high {
label = "blue:wifi_high";
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
};
wifi_medium {
label = "blue:wifi_medium";
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
};
wifi_low {
label = "blue:wifi_low";
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
};
};
};
&gpio2 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "config";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0x790000>;
};
partition@7e0000 {
label = "board_data";
reg = <0x7e0000 0x10000>;
read-only;
};
partition@7f0000 {
label = "nvram";
reg = <0x7f0000 0x10000>;
read-only;
};
};
};
};
&pcie {
status = "okay";
};
&pcie0 {
wifi@0,0 {
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x8000>;
ieee80211-freq-limit = <5000000 6000000>;
};
};
&ethernet {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
mtd-mac-address = <&factory 0x28>;
mediatek,portmap = "llllw";
port@4 {
status = "okay";
phy-handle = <&phy4>;
phy-mode = "rgmii";
};
port@5 {
status = "okay";
phy-handle = <&phy5>;
phy-mode = "rgmii";
};
mdio-bus {
status = "okay";
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii";
};
phy5: ethernet-phy@5 {
reg = <5>;
phy-mode = "rgmii";
};
};
};
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};
&state_default {
gpio {
groups = "ephy", "i2c", "wled", "uartf";
function = "gpio";
};
};

12
target/linux/ramips/dts/mt7620a_youku_yk-l1.dts Normal file
View File

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "mt7620a_youku_yk-l1.dtsi"
/ {
compatible = "youku,yk-l1", "ralink,mt7620a-soc";
model = "Youku YK-L1";
};
&firmware {
reg = <0x50000 0x1fb0000>;
};

27
target/linux/ramips/dts/mt7620a_youku_yk1.dts → target/linux/ramips/dts/mt7620a_youku_yk-l1.dtsi
View File

@ -4,9 +4,6 @@
#include <dt-bindings/input/input.h>
/ {
compatible = "youku,yk1", "ralink,mt7620a-soc";
model = "YOUKU YK1";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
@ -18,14 +15,10 @@
leds {
compatible = "gpio-leds";
wan {
label = "blue:wan";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
};
air {
label = "blue:air";
wlan {
label = "blue:wlan";
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
usb {
@ -56,10 +49,6 @@
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpio3 {
status = "okay";
};
@ -68,9 +57,9 @@
status = "okay";
flash@0 {
compatible = "mx25l25635f", "jedec,spi-nor";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
spi-max-frequency = <80000000>;
m25p,fast-read;
partitions {
@ -96,10 +85,10 @@
read-only;
};
partition@50000 {
firmware: partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0x1fb0000>;
/* reg property is set based on flash size in DTS files */
};
};
};
@ -107,7 +96,7 @@
&state_default {
default {
groups = "i2c", "rgmii1", "ephy", "wled";
groups = "i2c", "rgmii1", "wled";
function = "gpio";
};
};

12
target/linux/ramips/dts/mt7620a_youku_yk-l1c.dts Normal file
View File

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "mt7620a_youku_yk-l1.dtsi"
/ {
compatible = "youku,yk-l1c", "ralink,mt7620a-soc";
model = "Youku YK-L1c";
};
&firmware {
reg = <0x50000 0xfb0000>;
};

4
target/linux/ramips/dts/mt7620a_yukai_bocco.dts
View File

@ -141,10 +141,6 @@
mediatek,portmap = "llllw";
};
&gsw {
ralink,port4 = "ephy";
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

4
target/linux/ramips/dts/mt7620a_zte_q7.dts
View File

@ -111,7 +111,3 @@
&ohci {
status = "okay";
};
&gsw {
mediatek,port4 = "ephy";
};

3
target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts
View File

@ -157,7 +157,8 @@
};
&gsw {
mediatek,port4 = "gmac";
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&wmac {

15
target/linux/ramips/dts/mt7620n.dtsi
View File

@ -322,20 +322,6 @@
reset-names = "fe", "esw";
mediatek,switch = <&gsw>;
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
port@4 {
compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
reg = <4>;
status = "disabled";
};
};
gsw: gsw@10110000 {
@ -347,7 +333,6 @@
interrupt-parent = <&intc>;
interrupts = <17>;
mediatek,port4 = "ephy";
};
ehci: ehci@101c0000 {

6
target/linux/ramips/dts/mt7620n_dlink_dwr-921-c1.dts
View File

@ -133,12 +133,6 @@
status = "okay";
};
&ethernet {
port@4 {
status = "okay";
};
};
&state_default {
default {
groups = "spi refclk", "i2c", "ephy", "wled";

6
target/linux/ramips/dts/mt7620n_dlink_dwr-922-e2.dts
View File

@ -136,12 +136,6 @@
status = "okay";
};
&ethernet {
port@4 {
status = "okay";
};
};
&state_default {
default {
groups = "spi refclk", "i2c", "ephy", "wled";

2
target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts
View File

@ -65,7 +65,7 @@
status = "okay";
flash@0 {
compatible = "mx25l25635f", "jedec,spi-nor";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
m25p,fast-read;

2
target/linux/ramips/dts/mt7621_ubnt_unifi-6-lite.dts
View File

@ -15,7 +15,7 @@
status = "okay";
flash@0 {
compatible = "mx25l25635f", "jedec,spi-nor";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;

2
target/linux/ramips/dts/mt7621_ubnt_unifi-nanohd.dts
View File

@ -11,7 +11,7 @@
status = "okay";
flash@0 {
compatible = "mx25l25635f", "jedec,spi-nor";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;

211
target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
View File

@ -13,6 +13,7 @@
*/
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
@ -39,7 +40,7 @@ static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
struct fe_priv *priv = (struct fe_priv *)_priv;
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
u32 status;
int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
int i, max = (gsw->port4_ephy) ? (4) : (3);
status = mtk_switch_r32(gsw, GSW_REG_ISR);
if (status & PORT_IRQ_ST_CHG)
@ -60,118 +61,82 @@ static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
return IRQ_HANDLED;
}
static int mt7620_mdio_mode(struct device_node *eth_node)
{
struct device_node *phy_node, *mdiobus_node;
const __be32 *id;
int ret = 0;
mdiobus_node = of_get_child_by_name(eth_node, "mdio-bus");
if (mdiobus_node) {
if (of_property_read_bool(mdiobus_node, "mediatek,mdio-mode"))
ret = 1;
for_each_child_of_node(mdiobus_node, phy_node) {
id = of_get_property(phy_node, "reg", NULL);
if (id && (be32_to_cpu(*id) == 0x1f))
ret = 1;
}
of_node_put(mdiobus_node);
}
return ret;
}
static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
static void mt7620_hw_init(struct mt7620_gsw *gsw)
{
u32 i;
u32 val;
u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
u32 is_BGA = (rt_sysc_r32(SYSC_REG_CHIP_REV_ID) >> 16) & 1;
/* Internal ethernet requires PCIe RC mode */
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1);
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
/* Enable MIB stats */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
if (mdio_mode) {
u32 val;
/* turn off ephy and set phy base addr to 12 */
if (gsw->ephy_disable) {
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(0x1f << 24) | (0xc << 16),
(gsw->ephy_base << 16) | (0x1f << 24),
GSW_REG_GPC1);
/* set MT7530 central align */
val = mt7530_mdio_r32(gsw, 0x7830);
val &= ~BIT(0);
val |= BIT(1);
mt7530_mdio_w32(gsw, 0x7830, val);
pr_info("gsw: internal ephy disabled\n");
} else if (gsw->ephy_base) {
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16),
GSW_REG_GPC1);
fe_reset(MT7620A_RESET_EPHY);
val = mt7530_mdio_r32(gsw, 0x7a40);
val &= ~BIT(30);
mt7530_mdio_w32(gsw, 0x7a40, val);
pr_info("gsw: ephy base address: %d\n", gsw->ephy_base);
}
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
/* global page 4 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
if (is_BGA)
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
else
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
/* global page 3 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
/* global page 2 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
if (is_BGA) {
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
} else {
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
}
/* global page 1 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
if (gsw->ephy_base) {
/* set phy base addr to ephy_base */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16),
GSW_REG_GPC1);
fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
}
/* global page 4 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
if (is_BGA)
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
else
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
/* global page 3 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
/* global page 2 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
if (is_BGA) {
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
} else {
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
}
/* global page 1 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
/* turn on all PHYs */
for (i = 0; i <= 4; i++) {
val = _mt7620_mii_read(gsw, gsw->ephy_base + i, 0);
val &= ~BIT(11);
_mt7620_mii_write(gsw, gsw->ephy_base + i, 0, val);
}
/* turn on all PHYs */
for (i = 0; i <= 4; i++) {
val = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR);
val &= ~BMCR_PDOWN;
val |= BMCR_ANRESTART | BMCR_ANENABLE | BMCR_SPEED100;
_mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val);
}
/* global page 0 */
@ -200,8 +165,8 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
/* setup port 4 */
if (gsw->port4 == PORT4_EPHY) {
u32 val = rt_sysc_r32(SYSC_REG_CFG1);
if (gsw->port4_ephy) {
val = rt_sysc_r32(SYSC_REG_CFG1);
val |= 3 << 14;
rt_sysc_w32(val, SYSC_REG_CFG1);
@ -209,12 +174,6 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
_mt7620_mii_write(gsw, gsw->ephy_base + 4, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 4, 16, 0x1313);
pr_info("gsw: setting port4 to ephy mode\n");
} else if (!mdio_mode) {
u32 val = rt_sysc_r32(SYSC_REG_CFG1);
val &= ~(3 << 14);
rt_sysc_w32(val, SYSC_REG_CFG1);
pr_info("gsw: setting port4 to gmac mode\n");
}
}
@ -226,9 +185,13 @@ MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
int mtk_gsw_init(struct fe_priv *priv)
{
struct device_node *eth_node = priv->dev->of_node;
struct device_node *phy_node, *mdiobus_node;
struct device_node *np = priv->switch_np;
struct platform_device *pdev = of_find_device_by_node(np);
struct mt7620_gsw *gsw;
const __be32 *id;
u8 val;
if (!pdev)
return -ENODEV;
@ -239,7 +202,27 @@ int mtk_gsw_init(struct fe_priv *priv)
gsw = platform_get_drvdata(pdev);
priv->soc->swpriv = gsw;
mt7620_hw_init(gsw, mt7620_mdio_mode(priv->dev->of_node));
gsw->ephy_disable = of_property_read_bool(np, "mediatek,ephy-disable");
mdiobus_node = of_get_child_by_name(eth_node, "mdio-bus");
if (mdiobus_node) {
for_each_child_of_node(mdiobus_node, phy_node) {
id = of_get_property(phy_node, "reg", NULL);
if (id && (be32_to_cpu(*id) == 0x1f))
gsw->ephy_disable = true;
}
of_node_put(mdiobus_node);
}
gsw->port4_ephy = !of_property_read_bool(np, "mediatek,port4-gmac");
if (of_property_read_u8(np, "mediatek,ephy-base", &val) == 0)
gsw->ephy_base = val;
else
gsw->ephy_base = 0;
mt7620_hw_init(gsw);
if (gsw->irq) {
request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
@ -253,10 +236,7 @@ int mtk_gsw_init(struct fe_priv *priv)
static int mt7620_gsw_probe(struct platform_device *pdev)
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
const char *port4 = NULL;
struct mt7620_gsw *gsw;
struct device_node *np = pdev->dev.of_node;
u16 val;
gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
if (!gsw)
@ -268,19 +248,6 @@ static int mt7620_gsw_probe(struct platform_device *pdev)
gsw->dev = &pdev->dev;
of_property_read_string(np, "mediatek,port4", &port4);
if (port4 && !strcmp(port4, "ephy"))
gsw->port4 = PORT4_EPHY;
else if (port4 && !strcmp(port4, "gmac"))
gsw->port4 = PORT4_EXT;
else
gsw->port4 = PORT4_EPHY;
if (of_property_read_u16(np, "mediatek,ephy-base-address", &val) == 0)
gsw->ephy_base = val;
else
gsw->ephy_base = 0;
gsw->irq = platform_get_irq(pdev, 0);
platform_set_drvdata(pdev, gsw);

10
target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.h
View File

@ -55,7 +55,7 @@
#define SYSC_REG_CHIP_REV_ID 0x0c
#define SYSC_REG_CFG1 0x14
#define RST_CTRL_MCM BIT(2)
#define PCIE_RC_MODE BIT(8)
#define SYSC_PAD_RGMII2_MDIO 0x58
#define SYSC_GPIO_MODE 0x60
@ -88,16 +88,12 @@ enum {
GSW_ATTR_PORT_UNTAG,
};
enum {
PORT4_EPHY = 0,
PORT4_EXT,
};
struct mt7620_gsw {
struct device *dev;
void __iomem *base;
int irq;
int port4;
bool ephy_disable;
bool port4_ephy;
unsigned long int autopoll;
u16 ephy_base;
};

5
target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c
View File

@ -223,7 +223,8 @@ int fe_mdio_init(struct fe_priv *priv)
mii_np = of_get_child_by_name(priv->dev->of_node, "mdio-bus");
if (!mii_np) {
dev_err(priv->dev, "no %s child node found", "mdio-bus");
return -ENODEV;
err = 0;
goto err_no_bus;
}
if (!of_device_is_available(mii_np)) {
@ -255,6 +256,8 @@ err_free_bus:
kfree(priv->mii_bus);
err_put_node:
of_node_put(mii_np);
err_no_bus:
dev_err(priv->dev, "%s disabled", "mdio-bus");
priv->mii_bus = NULL;
return err;
}

6
target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
View File

@ -49,7 +49,7 @@ enum fe_work_flag {
FE_FLAG_MAX
};
#define MTK_FE_DRV_VERSION "0.1.2"
#define MTK_FE_DRV_VERSION "0.2"
/* power of 2 to let NEXT_TX_DESP_IDX work */
#define NUM_DMA_DESC BIT(10)
@ -157,6 +157,10 @@ enum fe_work_flag {
#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
#define MT7620A_RESET_FE BIT(21)
#define MT7620A_RESET_ESW BIT(23)
#define MT7620A_RESET_EPHY BIT(24)
#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)

39
target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
View File

@ -27,8 +27,6 @@
#define MT7620A_CDMA_CSG_CFG 0x400
#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
#define MT7620A_RESET_FE BIT(21)
#define MT7620A_RESET_ESW BIT(23)
#define MT7620_L4_VALID BIT(23)
#define MT7620_TX_DMA_UDF BIT(15)
@ -82,11 +80,26 @@ static const u16 mt7620_reg_table[FE_REG_COUNT] = {
static int mt7620_gsw_config(struct fe_priv *priv)
{
struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
u32 val;
/* is the mt7530 internal or external */
if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) {
mt7530_probe(priv->dev, gsw->base, NULL, 0);
mt7530_probe(priv->dev, NULL, priv->mii_bus, 1);
/* magic values from original SDK */
val = mt7530_mdio_r32(gsw, 0x7830);
val &= ~BIT(0);
val |= BIT(1);
mt7530_mdio_w32(gsw, 0x7830, val);
val = mt7530_mdio_r32(gsw, 0x7a40);
val &= ~BIT(30);
mt7530_mdio_w32(gsw, 0x7a40, val);
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
pr_info("mt7530: mdio central align\n");
} else {
mt7530_probe(priv->dev, gsw->base, NULL, 1);
}
@ -136,7 +149,7 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
u32 val, mask = 0;
u32 val_delay = 0;
u32 mask_delay = GSW_REG_GPCx_TXDELAY | GSW_REG_GPCx_RXDELAY;
int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
int min = (gsw->port4_ephy) ? (5) : (4);
if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
if (_id)
@ -158,7 +171,6 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
(size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
pr_err("%s: invalid fixed link property\n", np->name);
priv->phy->phy_fixed[id] = NULL;
return;
}
phy_mode = of_get_phy_mode(np);
@ -182,7 +194,7 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
break;
case PHY_INTERFACE_MODE_RGMII_TXID:
mask = 0;
val_delay &= ~GSW_REG_GPCx_TXDELAY;
val_delay |= GSW_REG_GPCx_TXDELAY;
val_delay |= GSW_REG_GPCx_RXDELAY;
break;
case PHY_INTERFACE_MODE_MII:
@ -196,10 +208,6 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
return;
}
priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
return;
val = rt_sysc_r32(SYSC_REG_CFG1);
val &= ~(3 << shift);
val |= mask << shift;
@ -240,8 +248,8 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
val = 2;
break;
default:
dev_err(priv->dev, "invalid link speed: %d\n",
priv->phy->speed[id]);
dev_err(priv->dev, "port %d - invalid link speed: %d\n",
id, priv->phy->speed[id]);
priv->phy->phy_fixed[id] = 0;
return;
}
@ -255,7 +263,13 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
if (priv->phy->duplex[id])
val |= PMCR_DUPLEX;
mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
dev_info(priv->dev, "using fixed link parameters\n");
dev_info(priv->dev, "port %d - using fixed link parameters\n", id);
return;
}
priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
if (!priv->phy->phy_node[id]) {
dev_err(priv->dev, "port %d - missing phy handle\n", id);
return;
}
@ -268,7 +282,6 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
fe_connect_phy_node(priv, priv->phy->phy_node[id], id);
gsw->autopoll |= BIT(be32_to_cpup(phy_addr));
mt7620_auto_poll(gsw,id);
return;
}
}

29
target/linux/ramips/image/mt7620.mk
View File

@ -1105,6 +1105,15 @@ define Device/wavlink_wl-wn530hg4
endef
TARGET_DEVICES += wavlink_wl-wn530hg4
define Device/wavlink_wl-wn579x3
SOC := mt7620a
IMAGE_SIZE := 7744k
DEVICE_VENDOR := Wavlink
DEVICE_MODEL := WL-WN579X3
DEVICE_PACKAGES := kmod-mt76x2 kmod-phy-realtek
endef
TARGET_DEVICES += wavlink_wl-wn579x3
define Device/wrtnode_wrtnode
SOC := mt7620n
IMAGE_SIZE := 16064k
@ -1125,16 +1134,26 @@ define Device/xiaomi_miwifi-mini
endef
TARGET_DEVICES += xiaomi_miwifi-mini
define Device/youku_yk1
define Device/youku_yk-l1
SOC := mt7620a
IMAGE_SIZE := 32448k
DEVICE_VENDOR := YOUKU
DEVICE_MODEL := YK1
DEVICE_VENDOR := Youku
DEVICE_MODEL := YK-L1
DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620 \
kmod-usb-ledtrig-usbport
SUPPORTED_DEVICES += youku-yk1
SUPPORTED_DEVICES += youku-yk1 youku,yk1
endef
TARGET_DEVICES += youku_yk1
TARGET_DEVICES += youku_yk-l1
define Device/youku_yk-l1c
SOC := mt7620a
IMAGE_SIZE := 16064k
DEVICE_VENDOR := Youku
DEVICE_MODEL := YK-L1c
DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620 \
kmod-usb-ledtrig-usbport
endef
TARGET_DEVICES += youku_yk-l1c
define Device/yukai_bocco
SOC := mt7620a

4
target/linux/ramips/mt7620/base-files/etc/board.d/01_leds
View File

@ -195,9 +195,9 @@ tplink,archer-mr200)
tplink,re200-v1)
ucidef_set_led_netdev "lan" "lan" "green:lan" "eth0"
;;
youku,yk1)
wavlink,wl-wn579x3)
ucidef_set_led_switch "lan" "lan" "blue:lan" "switch0" "0x20"
ucidef_set_led_switch "wan" "wan" "blue:wan" "switch0" "0x10"
ucidef_set_led_netdev "wifi_led" "wifi" "blue:air" "wlan0"
;;
zbtlink,zbt-ape522ii)
ucidef_set_led_netdev "wlan2g4" "wlan1-link" "green:wlan2g4" "wlan1"

16
target/linux/ramips/mt7620/base-files/etc/board.d/02_network
View File

@ -137,6 +137,9 @@ ramips_setup_interfaces()
engenius,esr600)
ucidef_add_switch "switch0" \
"1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5:wan" "0@eth0"
ucidef_add_switch "switch1" \
"5:lan" "6@eth0"
ucidef_add_switch_attr "switch1" "enable" "false"
;;
fon,fon2601)
ucidef_add_switch "switch0" \
@ -169,6 +172,9 @@ ramips_setup_interfaces()
lava,lr-25g001)
ucidef_add_switch "switch0" \
"1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "0@eth0"
ucidef_add_switch "switch1" \
"5:lan" "6@eth0"
ucidef_add_switch_attr "switch1" "enable" "false"
;;
lenovo,newifi-y1|\
xiaomi,miwifi-mini)
@ -216,7 +222,12 @@ ramips_setup_interfaces()
ucidef_add_switch "switch0" \
"0:lan" "4:wan" "6@eth0"
;;
youku,yk1)
wavlink,wl-wn579x3)
ucidef_add_switch "switch0" \
"5:lan" "4:wan" "6@eth0"
;;
youku,yk-l1|\
youku,yk-l1c)
ucidef_add_switch "switch0" \
"0:lan" "1:lan" "4:wan" "6@eth0"
;;
@ -339,7 +350,8 @@ ramips_setup_macs()
lenovo,newifi-y1s|\
ohyeah,oy-0001|\
wavlink,wl-wn530hg4|\
youku,yk1)
youku,yk-l1|\
youku,yk-l1c)
wan_mac=$(mtd_get_mac_binary factory 0x2e)
;;
linksys,e1700)