mirror of
https://github.com/hanwckf/immortalwrt-mt798x.git
synced 2025-01-07 01:53:34 +08:00
mediatek:add support for rtl8221x
This commit is contained in:
padavanonly
hanwckf
parent
a5c5eef119
commit
bcd46e3b1d
@ -4,5 +4,6 @@
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#
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obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
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mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_eth_dbg.o mtk_eth_reset.o
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mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_eth_dbg.o mtk_eth_reset.o mtk_eth_rtl822x.o
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obj-$(CONFIG_NET_MEDIATEK_SOC) += rtl822x/
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obj-$(CONFIG_NET_MEDIATEK_HNAT) += mtk_hnat/
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246
target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_rtl822x.c
Executable file
246
target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_rtl822x.c
Executable file
@ -0,0 +1,246 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
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*/
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#include <linux/of_device.h>
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#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/if_vlan.h>
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#include <linux/reset.h>
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#include <linux/tcp.h>
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#include <linux/interrupt.h>
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#include <linux/pinctrl/devinfo.h>
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#include <linux/phylink.h>
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#include <net/dsa.h>
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#include <linux/of_platform.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include "mtk_eth_soc.h"
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#include "mtk_eth_dbg.h"
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#include "mtk_eth_reset.h"
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#include "mtk_hnat/nf_hnat_mtk.h"
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#include "rtl822x/rtl_adapter.h"
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#include "rtl822x/rtl8226_typedef.h"
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#include "rtl822x/nic_rtl8226b_init.h"
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static struct mtk_eth *sg_eth;
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int mtk_mii_rw(struct mtk_eth *eth, int phy, int reg, u16 data,
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u32 cmd, u32 st)
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{
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#define PHY_IAC MTK_PHY_IAC
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#define PHY_ACS_ST BIT(31)
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#define MDIO_REG_ADDR_S 25
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#define MDIO_REG_ADDR_M 0x3e000000
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#define MDIO_PHY_ADDR_S 20
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#define MDIO_PHY_ADDR_M 0x1f00000
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#define MDIO_CMD_S 18
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#define MDIO_CMD_M 0xc0000
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#define MDIO_ST_S 16
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#define MDIO_ST_M 0x30000
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#define MDIO_RW_DATA_S 0
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#define MDIO_RW_DATA_M 0xffff
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#define MDIO_CMD_ADDR 0
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#define MDIO_CMD_WRITE 1
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#define MDIO_CMD_READ 2
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#define MDIO_CMD_READ_C45 3
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#define MDIO_ST_C45 0
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#define MDIO_ST_C22 1
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u32 val = 0;
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int ret = 0;
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if (mtk_mdio_busy_wait(eth))
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return -1;
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val = (st << MDIO_ST_S) |
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((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
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((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
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((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
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if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
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val |= data & MDIO_RW_DATA_M;
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mtk_w32(eth, val | PHY_ACS_ST, PHY_IAC);
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if (mtk_mdio_busy_wait(eth))
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return -1;
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if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
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val = mtk_r32(eth, PHY_IAC);
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ret = val & MDIO_RW_DATA_M;
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}
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return ret;
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}
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int mtk_mmd_read(struct mtk_eth *eth, int addr, int devad, u16 reg)
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{
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int val;
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mutex_lock(ð->mii_bus->mdio_lock);
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mtk_mii_rw(eth, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
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val = mtk_mii_rw(eth, addr, devad, 0, MDIO_CMD_READ_C45,
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MDIO_ST_C45);
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mutex_unlock(ð->mii_bus->mdio_lock);
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return val;
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}
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void mtk_mmd_write(struct mtk_eth *eth, int addr, int devad, u16 reg,
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u16 val)
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{
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mutex_lock(ð->mii_bus->mdio_lock);
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mtk_mii_rw(eth, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
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mtk_mii_rw(eth, addr, devad, val, MDIO_CMD_WRITE, MDIO_ST_C45);
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mutex_unlock(ð->mii_bus->mdio_lock);
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}
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u32 mtk_cl45_ind_read(struct mtk_eth *eth, u16 port, u16 devad, u16 reg, u16 *data)
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{
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mutex_lock(ð->mii_bus->mdio_lock);
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_mtk_mdio_write(eth, port, MII_MMD_ACC_CTL_REG, devad);
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_mtk_mdio_write(eth, port, MII_MMD_ADDR_DATA_REG, reg);
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_mtk_mdio_write(eth, port, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
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*data = _mtk_mdio_read(eth, port, MII_MMD_ADDR_DATA_REG);
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mutex_unlock(ð->mii_bus->mdio_lock);
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return 0;
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}
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u32 mtk_cl45_ind_write(struct mtk_eth *eth, u16 port, u16 devad, u16 reg, u16 data)
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{
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mutex_lock(ð->mii_bus->mdio_lock);
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_mtk_mdio_write(eth, port, MII_MMD_ACC_CTL_REG, devad);
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_mtk_mdio_write(eth, port, MII_MMD_ADDR_DATA_REG, reg);
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_mtk_mdio_write(eth, port, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
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_mtk_mdio_write(eth, port, MII_MMD_ADDR_DATA_REG, data);
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mutex_unlock(ð->mii_bus->mdio_lock);
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return 0;
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}
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int mtk_soc_mmd_read(int phyad, int devad, int regad)
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{
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struct mtk_eth *eth = sg_eth;
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return mtk_mmd_read(eth, phyad, devad, regad);
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}
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void mtk_soc_mmd_write(int phyad, int devad, int regad, int val)
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{
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struct mtk_eth *eth = sg_eth;
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mtk_mmd_write(eth, phyad, devad, regad, val);
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}
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static int rtl822x_init(struct mtk_eth *eth, int addr)
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{
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u32 val;
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val = mtk_mmd_read(eth, addr, 30, 0x75F3);
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val &= ~(1 << 0);
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mtk_mmd_write(eth, addr, 30, 0x75F3, val);
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val = mtk_mmd_read(eth, addr, 30, 0x697A);
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val &= ~(0x3F);
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val |= 0x2;
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val |= (1 << 15);
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mtk_mmd_write(eth, addr, 30, 0x697A, val);
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msleep(500);
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val = mtk_mmd_read(eth, addr, 7, 0);
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val |= (1 << 9);
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mtk_mmd_write(eth, addr, 7, 0, val);
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msleep(500);
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dev_info(eth->dev, "RTL822x init success!\n");
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Rtl8226b_phy_init((HANDLE){eth, addr}, NULL, 1);
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return 0;
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}
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static struct mtk_extphy_id extphy_tbl[] = {
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{0x001CC840, 0x0fffffff0, 1, rtl822x_init},
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};
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static u32 get_cl22_phy_id(struct mtk_eth *eth, int addr)
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{
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int phy_reg;
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u32 phy_id = 0;
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phy_reg = _mtk_mdio_read(eth, addr, MII_PHYSID1);
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if (phy_reg < 0)
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return 0;
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phy_id = (phy_reg & 0xffff) << 16;
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/* Grab the bits from PHYIR2, and put them in the lower half */
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phy_reg = _mtk_mdio_read(eth, addr, MII_PHYSID2);
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if (phy_reg < 0)
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return 0;
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phy_id |= (phy_reg & 0xffff);
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return phy_id;
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}
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static u32 get_cl45_phy_id(struct mtk_eth *eth, int addr)
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{
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u16 phy_reg;
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u32 phy_id = 0;
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mtk_cl45_ind_read(eth, addr, 1, MII_PHYSID1, &phy_reg);
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if (phy_reg < 0)
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return 0;
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phy_id = (phy_reg & 0xffff) << 16;
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/* Grab the bits from PHYIR2, and put them in the lower half */
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mtk_cl45_ind_read(eth, addr, 1, MII_PHYSID2, &phy_reg);
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if (phy_reg < 0)
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return 0;
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phy_id |= (phy_reg & 0xffff);
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return phy_id;
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}
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static inline bool phy_id_is_match(u32 id, struct mtk_extphy_id *phy)
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{
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return ((id & phy->phy_id_mask) == (phy->phy_id & phy->phy_id_mask));
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}
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int mtk_soc_extphy_init(struct mtk_eth *eth, int addr)
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{
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int i;
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u32 phy_id;
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struct mtk_extphy_id *extphy;
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for (i = 0; i < ARRAY_SIZE(extphy_tbl); i++)
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{
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extphy = &extphy_tbl[i];
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if (extphy->is_c45)
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{
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phy_id = get_cl45_phy_id(eth, addr);
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}
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else
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{
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phy_id = get_cl22_phy_id(eth, addr);
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}
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if (phy_id_is_match(phy_id, extphy))
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{extphy->init(eth, addr);}
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}
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return 0;
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}
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@ -20,7 +20,9 @@
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#include <linux/pinctrl/devinfo.h>
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#include <linux/phylink.h>
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#include <net/dsa.h>
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#include <linux/of_platform.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include "mtk_eth_soc.h"
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#include "mtk_eth_dbg.h"
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#include "mtk_eth_reset.h"
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@ -28,7 +30,7 @@
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#if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE)
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#include "mtk_hnat/nf_hnat_mtk.h"
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#endif
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static struct mtk_eth *sg_eth;
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static int mtk_msg_level = -1;
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atomic_t reset_lock = ATOMIC_INIT(0);
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atomic_t force = ATOMIC_INIT(0);
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@ -87,7 +89,7 @@ u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
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return reg;
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}
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static int mtk_mdio_busy_wait(struct mtk_eth *eth)
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int mtk_mdio_busy_wait(struct mtk_eth *eth)
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{
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unsigned long t_start = jiffies;
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@ -3495,11 +3497,11 @@ static int mtk_probe(struct platform_device *pdev)
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struct device_node *mac_np;
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struct mtk_eth *eth;
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int err, i;
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static int ext_init = 0;
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eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
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if (!eth)
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return -ENOMEM;
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sg_eth = eth;
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eth->soc = of_device_get_match_data(&pdev->dev);
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eth->dev = &pdev->dev;
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@ -3614,6 +3616,8 @@ static int mtk_probe(struct platform_device *pdev)
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eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
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for_each_child_of_node(pdev->dev.of_node, mac_np) {
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int ext_reset_pin = -1;
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int ret = -1;
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if (!of_device_is_compatible(mac_np,
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"mediatek,eth-mac"))
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continue;
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@ -3625,7 +3629,22 @@ static int mtk_probe(struct platform_device *pdev)
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if (err) {
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of_node_put(mac_np);
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goto err_deinit_hw;
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}
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ext_reset_pin = of_get_named_gpio(mac_np, "ext-phy-reset-gpios", 0);
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if (ext_reset_pin >= 0){
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dev_info(&pdev->dev, "Ext-phy gpio : %d\n", ext_reset_pin);
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ret = devm_gpio_request(&pdev->dev, ext_reset_pin, "mt753x-reset");
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if (!ret)
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{
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gpio_direction_output(ext_reset_pin, 0);
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msleep(300);
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gpio_set_value(ext_reset_pin, 1);
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msleep(500);
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}
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}
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}
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err = mtk_napi_init(eth);
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@ -3721,6 +3740,19 @@ static int mtk_probe(struct platform_device *pdev)
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add_timer(ð->mtk_dma_monitor_timer);
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#endif
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if (!ext_init){
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for_each_child_of_node(pdev->dev.of_node, mac_np) {
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unsigned int ext_phy_reg = 0;
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int err = -1;
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err = of_property_read_u32_index(mac_np, "ext-phy-reg", 0, &ext_phy_reg);
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if (err >= 0){
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dev_info(&pdev->dev, "Ext-phy reg : %d\n", ext_phy_reg);
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mtk_soc_extphy_init(eth, ext_phy_reg);
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}
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}
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ext_init = 1;
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}
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return 0;
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err_deinit_mdio:
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@ -768,6 +768,25 @@
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#define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
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#define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
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/*MDIO control*/
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#define MII_MMD_ACC_CTL_REG 0x0d
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#define MII_MMD_ADDR_DATA_REG 0x0e
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#define MMD_OP_MODE_DATA BIT(14)
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struct mtk_eth;
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/* mmd */
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int mtk_mmd_read(struct mtk_eth *eth, int addr, int devad, u16 reg);
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void mtk_mmd_write(struct mtk_eth *eth, int addr, int devad, u16 reg,
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u16 val);
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struct mtk_extphy_id
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{
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u32 phy_id;
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u32 phy_id_mask;
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u32 is_c45;
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int (*init)(struct mtk_eth *, int addr);
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};
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struct mtk_rx_dma {
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unsigned int rxd1;
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unsigned int rxd2;
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@ -1318,5 +1337,6 @@ int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
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int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
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void mtk_gdm_config(struct mtk_eth *eth, u32 id, u32 config);
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void ethsys_reset(struct mtk_eth *eth, u32 reset_bits);
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int mtk_soc_extphy_init(struct mtk_eth *eth, int addr);
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int mtk_mdio_busy_wait(struct mtk_eth *eth);
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#endif /* MTK_ETH_H */
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@ -299,7 +299,7 @@ void foe_clear_entry(struct neighbour *neigh)
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*((u32 *)h_dest) = swab32(entry->ipv4_hnapt.dmac_hi);
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*((u16 *)&h_dest[4]) =
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swab16(entry->ipv4_hnapt.dmac_lo);
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if (memcmp(h_dest, neigh->ha, ETH_ALEN) != 0) {
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if (!ether_addr_equal(h_dest, neigh->ha)) {
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cr_set_field(hnat_priv->ppe_base[i] + PPE_TB_CFG,
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SMA, SMA_ONLY_FWD_CPU);
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@ -0,0 +1,4 @@
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ccflags-y=-Wall
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obj-y += rtl822x_phy.o
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rtl822x_phy-objs := rtl_adapter.o nic_rtl8226b_init.o
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2699
target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/rtl822x/nic_rtl8226b.c
Executable file
2699
target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/rtl822x/nic_rtl8226b.c
Executable file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,336 @@
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/*
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* Copyright (C) 2019 Realtek Semiconductor Corp.
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* All Rights Reserved.
|
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*
|
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* This program is the proprietary software of Realtek Semiconductor
|
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* Corporation and/or its licensors, and only be used, duplicated,
|
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* modified or distributed under the authorized license from Realtek.
|
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*
|
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* ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
|
||||
* THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
|
||||
*
|
||||
* Purpose : PHY 8226 Driver
|
||||
*
|
||||
* Feature : PHY 8226 Driver
|
||||
*
|
||||
*/
|
||||
#ifndef __NIC_RTL8226B_H__
|
||||
#define __NIC_RTL8226B_H__
|
||||
|
||||
#include <hal/phy/nic_rtl8226/rtl8226_typedef.h>
|
||||
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_ThermalSensor_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT PHY_THERMAL_RESULT *pTsResult
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_ThermalSensor_resume_2P5G(
|
||||
IN HANDLE hDevice
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_wol_set(
|
||||
IN HANDLE hDevice,
|
||||
IN PHY_WOL_EVENT *pwolevent
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_wol_exit(
|
||||
IN HANDLE hDevice
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_phy_reset(
|
||||
IN HANDLE hDevice
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_autoNegoEnable_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *pEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_autoNegoEnable_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_autoNegoAbility_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT PHY_LINK_ABILITY *pPhyAbility
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_autoNegoAbility_set(
|
||||
IN HANDLE hDevice,
|
||||
IN PHY_LINK_ABILITY *pPhyAbility
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_duplex_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *pEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_duplex_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_is_link(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *plinkok
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_speed_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT UINT16 *pSpeed
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_force_speed_set(
|
||||
IN HANDLE hDevice,
|
||||
IN UINT16 Speed
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_force_speed_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT UINT16 *force_speed
|
||||
);
|
||||
|
||||
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_enable_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_greenEnable_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *pEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_greenEnable_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_eeeEnable_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT PHY_EEE_ENABLE *pEeeEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_eeeEnable_set(
|
||||
IN HANDLE hDevice,
|
||||
IN PHY_EEE_ENABLE *pEeeEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_PHYmodeEEE_set(
|
||||
IN HANDLE hDevice,
|
||||
int on_off
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_10M_PHYmodeEEEP_set(
|
||||
IN HANDLE hDevice,
|
||||
int on_off
|
||||
);
|
||||
|
||||
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_crossOverMode_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT PHY_CROSSPVER_MODE *CrossOverMode
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_crossOverMode_set(
|
||||
IN HANDLE hDevice,
|
||||
IN PHY_CROSSPVER_MODE CrossOverMode
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_crossOverStatus_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT PHY_CROSSPVER_STATUS *pCrossOverStatus
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_masterSlave_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT PHY_MASTERSLAVE_MODE *MasterSlaveMode
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_masterSlave_set(
|
||||
IN HANDLE hDevice,
|
||||
IN PHY_MASTERSLAVE_MODE MasterSlaveMode
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_loopback_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *pEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_loopback_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_downSpeedEnable_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *pEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_downSpeedEnable_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_gigaLiteEnable_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *pEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_gigaLiteEnable_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_mdiSwapEnable_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *pEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_mdiSwapEnable_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_rtct_start(
|
||||
IN HANDLE hDevice
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_rtctResult_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT PHY_RTCT_RESULT *pRtctResult
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_rtctdone_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *prtct_done
|
||||
);
|
||||
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_linkDownPowerSavingEnable_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *pEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_linkDownPowerSavingEnable_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_2p5gLiteEnable_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *pEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_2p5gLiteEnable_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_ThermalSensorEnable_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *pEnable
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_ThermalSensorEnable_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable,
|
||||
IN UINT16 threshold
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_ieeeTestMode_set(
|
||||
IN HANDLE hDevice,
|
||||
IN UINT16 Speed,
|
||||
IN PHY_IEEE_TEST_MODE *pIEEEtestmode
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_serdes_rst(
|
||||
IN HANDLE hDevice
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_serdes_link_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT BOOL *perdesLink,
|
||||
OUT PHY_SERDES_MODE *SerdesMode
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_serdes_option_set(
|
||||
IN HANDLE hDevice,
|
||||
IN UINT8 functioninput
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_serdes_option_get(
|
||||
IN HANDLE hDevice,
|
||||
OUT PHY_SERDES_OPTION *SerdesOption
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_serdes_polarity_swap(
|
||||
IN HANDLE hDevice,
|
||||
IN PHY_SERDES_POLARITY_SWAP *ppolarityswap
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_serdes_autoNego_set(
|
||||
IN HANDLE hDevice,
|
||||
IN BOOL Enable
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* __NIC_RTL8226_H__ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,16 @@
|
||||
|
||||
#ifndef __NIC_RTL8226B_INIT_H__
|
||||
#define __NIC_RTL8226B_INIT_H__
|
||||
|
||||
BOOLEAN
|
||||
Rtl8226b_phy_init(
|
||||
IN HANDLE hDevice,
|
||||
IN PHY_LINK_ABILITY *pphylinkability,
|
||||
IN BOOL singlephy
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,302 @@
|
||||
/*
|
||||
* Copyright (C) 2019 Realtek Semiconductor Corp.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is the proprietary software of Realtek Semiconductor
|
||||
* Corporation and/or its licensors, and only be used, duplicated,
|
||||
* modified or distributed under the authorized license from Realtek.
|
||||
*
|
||||
* ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
|
||||
* THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
|
||||
*
|
||||
* Purpose : PHY 8226 Driver
|
||||
*
|
||||
* Feature : PHY 8226 Driver
|
||||
*
|
||||
*/
|
||||
#ifndef __NIC_RTL8226_TYPEDEF_H__
|
||||
#define __NIC_RTL8226_TYPEDEF_H__
|
||||
|
||||
#include <linux/phy.h>
|
||||
|
||||
/* from typedef.h and rtl8156_mmd.h */
|
||||
|
||||
#define BIT_0 0x0001
|
||||
#define BIT_1 0x0002
|
||||
#define BIT_2 0x0004
|
||||
#define BIT_3 0x0008
|
||||
#define BIT_4 0x0010
|
||||
#define BIT_5 0x0020
|
||||
#define BIT_6 0x0040
|
||||
#define BIT_7 0x0080
|
||||
#define BIT_8 0x0100
|
||||
#define BIT_9 0x0200
|
||||
#define BIT_10 0x0400
|
||||
#define BIT_11 0x0800
|
||||
#define BIT_12 0x1000
|
||||
#define BIT_13 0x2000
|
||||
#define BIT_14 0x4000
|
||||
#define BIT_15 0x8000
|
||||
|
||||
#define SUCCESS TRUE
|
||||
#define FAILURE FALSE
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
struct mtk_eth *eth;
|
||||
int addr;
|
||||
} HANDLE;
|
||||
|
||||
#define BOOLEAN bool
|
||||
#define BOOL uint32
|
||||
#define UINT32 uint32
|
||||
#define UINT16 uint16
|
||||
#define UINT8 uint8
|
||||
#define Sleep(_t) osal_time_udelay(_t*1000)
|
||||
#define IN
|
||||
#define OUT
|
||||
|
||||
|
||||
#define MMD_PMAPMD 1
|
||||
#define MMD_PCS 3
|
||||
#define MMD_AN 7
|
||||
#define MMD_VEND1 30 /* Vendor specific 2 */
|
||||
#define MMD_VEND2 31 /* Vendor specific 2 */
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT16 dev;
|
||||
UINT16 addr;
|
||||
UINT16 value;
|
||||
} MMD_REG;
|
||||
|
||||
|
||||
#define NO_LINK 0
|
||||
#define LINK_SPEED_10M 10
|
||||
#define LINK_SPEED_100M 100
|
||||
#define LINK_SPEED_500M 500
|
||||
#define LINK_SPEED_1G 1000
|
||||
#define LINK_SPEED_2P5G 2500
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PHY_CROSSPVER_MODE_AUTO = 0,
|
||||
PHY_CROSSPVER_MODE_MDI,
|
||||
PHY_CROSSPVER_MODE_MDIX,
|
||||
PHY_CROSSPVER_MODE_END
|
||||
} PHY_CROSSPVER_MODE;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PHY_CROSSPVER_STATUS_MDI = 0,
|
||||
PHY_CROSSPVER_STATUS_MDIX,
|
||||
PHY_CROSSPVER_STATUS_END
|
||||
} PHY_CROSSPVER_STATUS;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PHY_AUTO_MODE = 0,
|
||||
PHY_SLAVE_MODE,
|
||||
PHY_MASTER_MODE,
|
||||
PHY_MASTER_SLAVE_END
|
||||
} PHY_MASTERSLAVE_MODE;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT32 Half_10:1;
|
||||
UINT32 Full_10:1;
|
||||
|
||||
UINT32 Half_100:1;
|
||||
UINT32 Full_100:1;
|
||||
|
||||
UINT32 Full_1000:1;
|
||||
|
||||
UINT32 adv_2_5G:1;
|
||||
|
||||
UINT32 FC:1;
|
||||
UINT32 AsyFC:1;
|
||||
} PHY_LINK_ABILITY;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT8 EEE_100:1;
|
||||
UINT8 EEE_1000:1;
|
||||
UINT8 EEE_2_5G:1;
|
||||
} PHY_EEE_ENABLE;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT8 TX_SWAP:1;
|
||||
UINT8 RX_SWAP:1;
|
||||
} PHY_SERDES_POLARITY_SWAP;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
TESTMODE_CHANNEL_NONE = 0,
|
||||
TESTMODE_CHANNEL_A,
|
||||
TESTMODE_CHANNEL_B,
|
||||
TESTMODE_CHANNEL_C,
|
||||
TESTMODE_CHANNEL_D,
|
||||
TESTMODE_CHANNEL_END
|
||||
} PHY_TESTMODE_CHANNEL;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT32 TM1:1;
|
||||
UINT32 TM2:1;
|
||||
UINT32 TM3:1;
|
||||
UINT32 TM4:1;
|
||||
UINT32 TM5:1;
|
||||
UINT32 TM6:1;
|
||||
|
||||
UINT32 TONE1:1;
|
||||
UINT32 TONE2:1;
|
||||
UINT32 TONE3:1;
|
||||
UINT32 TONE4:1;
|
||||
UINT32 TONE5:1;
|
||||
|
||||
UINT32 TMFINISH:1;
|
||||
|
||||
UINT32 NORMAL:1;
|
||||
UINT32 HARMONIC:1;
|
||||
UINT32 LINKPLUSE:1;
|
||||
|
||||
PHY_TESTMODE_CHANNEL channel:3;
|
||||
} PHY_IEEE_TEST_MODE;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MIS_MATCH_OPEN = 1, // Mis-Match_Open, larger_than_130ohm
|
||||
MIS_MATCH_SHORT = 2, // Mis-Match_short, less_than_77ohm
|
||||
} PHY_RTCT_STATUS_MISMATCH;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BOOL Open;
|
||||
BOOL Short;
|
||||
PHY_RTCT_STATUS_MISMATCH Mismatch;
|
||||
} PHY_RTCT_STATUS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
UINT16 linkType;
|
||||
|
||||
UINT32 rxLen;
|
||||
UINT32 txLen;
|
||||
|
||||
UINT32 channelALen;
|
||||
UINT32 channelBLen;
|
||||
UINT32 channelCLen;
|
||||
UINT32 channelDLen;
|
||||
|
||||
PHY_RTCT_STATUS channelAStatus;
|
||||
PHY_RTCT_STATUS channelBStatus;
|
||||
PHY_RTCT_STATUS channelCStatus;
|
||||
PHY_RTCT_STATUS channelDStatus;
|
||||
} PHY_RTCT_RESULT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PHY_SERDES_MODE_OTHER = 0,
|
||||
PHY_SERDES_MODE_SGMII,
|
||||
PHY_SERDES_MODE_HiSGMII,
|
||||
PHY_SERDES_MODE_2500BASEX,
|
||||
PHY_SERDES_MODE_USXGMII,
|
||||
PHY_SERDES_MODE_NO_SDS,
|
||||
PHY_SERDES_MODE_END
|
||||
} PHY_SERDES_MODE;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PHY_SERDES_OPTION_2500BASEX_SGMII = 0,
|
||||
PHY_SERDES_OPTION_HiSGMII_SGMII,
|
||||
PHY_SERDES_OPTION_2500BASEX,
|
||||
PHY_SERDES_OPTION_HiSGMII,
|
||||
PHY_SERDES_OPTION_OTHER,
|
||||
} PHY_SERDES_OPTION;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT16 MASK15_0;
|
||||
UINT16 MASK31_16;
|
||||
UINT16 MASK47_32;
|
||||
UINT16 MASK63_48;
|
||||
UINT16 MASK79_64;
|
||||
UINT16 MASK95_80;
|
||||
UINT16 MASK111_96;
|
||||
UINT16 MASK127_112;
|
||||
UINT16 CRC;
|
||||
} PHY_WAKEUP_FRAME;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT16 REG15_0;
|
||||
UINT16 REG31_16;
|
||||
UINT16 REG47_32;
|
||||
UINT16 REG63_48;
|
||||
} PHY_MULTICAST_REG;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT16 ADDR15_0;
|
||||
UINT16 ADDR31_16;
|
||||
UINT16 ADDR47_32;
|
||||
} PHY_MAC_ADDRESS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT32 LINKCHG:1;
|
||||
UINT32 MAGIC:1;
|
||||
UINT32 ARBITRARY:1;
|
||||
UINT32 UNICAST:1;
|
||||
UINT32 MULTICAST:1;
|
||||
UINT32 BROADCAST:1;
|
||||
|
||||
UINT32 FRAME0:1;
|
||||
UINT32 FRAME1:1;
|
||||
UINT32 FRAME2:1;
|
||||
UINT32 FRAME3:1;
|
||||
UINT32 FRAME4:1;
|
||||
UINT32 FRAME5:1;
|
||||
UINT32 FRAME6:1;
|
||||
UINT32 FRAME7:1;
|
||||
|
||||
UINT32 MAXPKTLENGTH;
|
||||
PHY_MAC_ADDRESS macaddress;
|
||||
PHY_MULTICAST_REG multicast;
|
||||
|
||||
PHY_WAKEUP_FRAME wakeframe0;
|
||||
|
||||
} PHY_WOL_EVENT;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
bool Enable;
|
||||
UINT16 Temperature;
|
||||
UINT16 Temperature_threshold;
|
||||
}PHY_THERMAL_RESULT;
|
||||
|
||||
|
||||
BOOLEAN
|
||||
MmdPhyRead(
|
||||
IN HANDLE hDevice,
|
||||
IN UINT16 dev,
|
||||
IN UINT16 addr,
|
||||
OUT UINT16 *data);
|
||||
|
||||
BOOLEAN
|
||||
MmdPhyWrite(
|
||||
IN HANDLE hDevice,
|
||||
IN UINT16 dev,
|
||||
IN UINT16 addr,
|
||||
IN UINT16 data);
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* __NIC_RTL8226_TYPEDEF_H__ */
|
||||
|
||||
|
||||
@ -0,0 +1,42 @@
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_mdio.h>
|
||||
#include <linux/of_net.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/if_vlan.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/tcp.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mdio.h>
|
||||
#include <linux/of_mdio.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/of_net.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
||||
#include "../mtk_eth_soc.h"
|
||||
#include "rtl_adapter.h"
|
||||
#include "rtl8226_typedef.h"
|
||||
|
||||
bool MmdPhyWrite(HANDLE unit, uint16_t devad, uint16_t addr, uint16_t value)
|
||||
{
|
||||
struct mtk_eth *eth = unit.eth;
|
||||
if (eth != NULL)
|
||||
{
|
||||
mtk_mmd_write(eth, unit.addr, devad, addr, value);
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
bool MmdPhyRead(HANDLE unit, uint16_t devad, uint16_t addr, uint16_t *value)
|
||||
{
|
||||
struct mtk_eth *eth = unit.eth;
|
||||
if (eth != NULL)
|
||||
{
|
||||
int val = mtk_mmd_read(eth, unit.addr, devad, addr);
|
||||
*value = (uint16_t)val;
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
@ -0,0 +1,40 @@
|
||||
#ifndef __RTL_ADAPTER_LOAD__
|
||||
#define __RTL_ADAPTER_LOAD__
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#include <linux/errno.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/perf_event.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/ioport.h>
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
|
||||
|
||||
#define uint32 uint32_t
|
||||
#define uint16 uint16_t
|
||||
#define uint8 uint8_t
|
||||
#ifdef __KERNEL__
|
||||
#define osal_time_udelay(aa) msleep((aa)/1000)
|
||||
#define phy_osal_printf printk
|
||||
#define osal_printf printk
|
||||
#else
|
||||
#define osal_time_udelay(aa) usleep(aa)
|
||||
#define phy_osal_printf printf
|
||||
#define osal_printf printf
|
||||
#endif
|
||||
#endif
|
||||
Loading…
x
Reference in New Issue
Block a user