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r8125: bump to 9.004.01 to fix packet loss issue

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coolsnowwolf 2020-10-20 13:07:35 +08:00 committed by CN_SZTL
parent 739c450fdd
commit a14094b0c1
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GPG Key ID: 6850B6345C862176
13 changed files with 5366 additions and 1641 deletions
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3
package/lean/r8125/Makefile
View File

@ -65,7 +65,7 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=r8125
PKG_VERSION:=9.002.02
PKG_VERSION:=9.004.01
PKG_RELEASE:=1
#PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
@ -79,7 +79,6 @@ define KernelPackage/r8125
TITLE:=Driver for Realtek r8125 chipsets
SUBMENU:=Network Devices
VERSION:=$(LINUX_VERSION)+$(PKG_VERSION)-$(BOARD)-$(PKG_RELEASE)
DEPENDS:=@!LINUX_5_4
FILES:= $(PKG_BUILD_DIR)/r8125.ko
AUTOLOAD:=$(call AutoProbe,r8125)
endef

32
package/lean/r8125/src/Makefile
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@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
################################################################################
#
# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
@ -37,8 +38,13 @@ CONFIG_DOWN_SPEED_100 = n
CONFIG_ASPM = y
ENABLE_S5WOL = y
ENABLE_S5_KEEP_CURR_MAC = n
ENABLE_EEE = n
ENABLE_EEE = y
ENABLE_S0_MAGIC_PACKET = n
ENABLE_TX_NO_CLOSE = y
ENABLE_MULTIPLE_TX_QUEUE = n
ENABLE_PTP_SUPPORT = n
ENABLE_RSS_SUPPORT = n
ENABLE_LIB_SUPPORT = n
ifneq ($(KERNELRELEASE),)
obj-m := r8125.o
@ -47,15 +53,15 @@ ifneq ($(KERNELRELEASE),)
EXTRA_CFLAGS += -DCONFIG_SOC_LAN
endif
ifeq ($(ENABLE_REALWOW_SUPPORT), y)
r8125-objs += r8125_realwow.o
r8125-objs += r8125_realwow.o
EXTRA_CFLAGS += -DENABLE_REALWOW_SUPPORT
endif
ifeq ($(ENABLE_DASH_SUPPORT), y)
r8125-objs += r8125_dash.o
r8125-objs += r8125_dash.o
EXTRA_CFLAGS += -DENABLE_DASH_SUPPORT
endif
ifeq ($(ENABLE_DASH_PRINTER_SUPPORT), y)
r8125-objs += r8125_dash.o
r8125-objs += r8125_dash.o
EXTRA_CFLAGS += -DENABLE_DASH_SUPPORT -DENABLE_DASH_PRINTER_SUPPORT
endif
EXTRA_CFLAGS += -DCONFIG_R8125_NAPI
@ -78,6 +84,24 @@ ifneq ($(KERNELRELEASE),)
ifeq ($(ENABLE_S0_MAGIC_PACKET), y)
EXTRA_CFLAGS += -DENABLE_S0_MAGIC_PACKET
endif
ifeq ($(ENABLE_TX_NO_CLOSE), y)
EXTRA_CFLAGS += -DENABLE_TX_NO_CLOSE
endif
ifeq ($(ENABLE_MULTIPLE_TX_QUEUE), y)
EXTRA_CFLAGS += -DENABLE_MULTIPLE_TX_QUEUE
endif
ifeq ($(ENABLE_PTP_SUPPORT), y)
r8125-objs += r8125_ptp.o
EXTRA_CFLAGS += -DENABLE_PTP_SUPPORT
endif
ifeq ($(ENABLE_RSS_SUPPORT), y)
r8125-objs += r8125_rss.o
EXTRA_CFLAGS += -DENABLE_RSS_SUPPORT
endif
ifeq ($(ENABLE_LIB_SUPPORT), y)
r8125-objs += r8125_lib.o
EXTRA_CFLAGS += -DENABLE_LIB_SUPPORT
endif
else
BASEDIR := /lib/modules/$(shell uname -r)
KERNELDIR ?= $(BASEDIR)/build

1
package/lean/r8125/src/Makefile_linux24x
View File

@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
################################################################################
#
# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet

539
package/lean/r8125/src/r8125.h
View File

@ -1,10 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
################################################################################
#
# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
# controllers with PCI-Express interface.
#
# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved.
# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
@ -31,9 +32,20 @@
* US6,570,884, US6,115,776, and US6,327,625.
***********************************************************************************/
#ifndef __R8125_H
#define __R8125_H
//#include <linux/pci.h>
#include <linux/ethtool.h>
#include <linux/interrupt.h>
#include <linux/version.h>
#include "r8125_dash.h"
#include "r8125_realwow.h"
#include "r8125_ptp.h"
#include "r8125_rss.h"
#ifdef ENABLE_LIB_SUPPORT
#include "r8125_lib.h"
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)
#define skb_transport_offset(skb) (skb->h.raw - skb->data)
@ -124,11 +136,11 @@ do { \
#endif
#endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0)
#define RTL_ALLOC_SKB_INTR(tp, length) dev_alloc_skb(length)
#define RTL_ALLOC_SKB_INTR(napi, length) dev_alloc_skb(length)
#ifdef CONFIG_R8125_NAPI
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,19,0)
#undef RTL_ALLOC_SKB_INTR
#define RTL_ALLOC_SKB_INTR(tp, length) napi_alloc_skb(&tp->napi, length)
#define RTL_ALLOC_SKB_INTR(napi, length) napi_alloc_skb(napi, length)
#endif
#endif
@ -249,6 +261,14 @@ do { \
#define SUPPORTED_Asym_Pause (1 << 14)
#endif
#ifndef MDIO_EEE_100TX
#define MDIO_EEE_100TX 0x0002
#endif
#ifndef MDIO_EEE_1000T
#define MDIO_EEE_1000T 0x0004
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
#ifdef CONFIG_NET_POLL_CONTROLLER
#define RTL_NET_POLL_CONTROLLER dev->poll_controller=rtl8125_netpoll
@ -315,12 +335,30 @@ do { \
#define DASH_SUFFIX ""
#endif
#define RTL8125_VERSION "9.002.02" NAPI_SUFFIX DASH_SUFFIX
#if defined(ENABLE_REALWOW_SUPPORT)
#define REALWOW_SUFFIX "-REALWOW"
#else
#define REALWOW_SUFFIX ""
#endif
#if defined(ENABLE_PTP_SUPPORT)
#define PTP_SUFFIX "-PTP"
#else
#define PTP_SUFFIX ""
#endif
#if defined(ENABLE_RSS_SUPPORT)
#define RSS_SUFFIX "-RSS"
#else
#define RSS_SUFFIX ""
#endif
#define RTL8125_VERSION "9.004.01" NAPI_SUFFIX DASH_SUFFIX REALWOW_SUFFIX PTP_SUFFIX RSS_SUFFIX
#define MODULENAME "r8125"
#define PFX MODULENAME ": "
#define GPL_CLAIM "\
r8125 Copyright (C) 2019 Realtek NIC software team <nicfae@realtek.com> \n \
r8125 Copyright (C) 2020 Realtek NIC software team <nicfae@realtek.com> \n \
This program comes with ABSOLUTELY NO WARRANTY; for details, please see <http://www.gnu.org/licenses/>. \n \
This is free software, and you are welcome to redistribute it under certain conditions; see <http://www.gnu.org/licenses/>. \n"
@ -339,9 +377,6 @@ This is free software, and you are welcome to redistribute it under certain cond
#define R8125_MSG_DEFAULT \
(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
#define TX_BUFFS_AVAIL(tp) \
(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
#ifdef CONFIG_R8125_NAPI
#define rtl8125_rx_hwaccel_skb vlan_hwaccel_receive_skb
#define rtl8125_rx_quota(count, quota) min(count, quota)
@ -402,6 +437,11 @@ This is free software, and you are welcome to redistribute it under certain cond
#define R8125_PCI_REGS_SIZE (0x100)
#define R8125_NAPI_WEIGHT 64
#define R8125_MAX_MSIX_VEC_8125B 32
#define R8125_MIN_MSIX_VEC_8125B 17
#define R8125_MAX_MSIX_VEC 32
#define R8125_MAX_RX_QUEUES_VEC_V3 (16)
#define RTL8125_TX_TIMEOUT (6 * HZ)
#define RTL8125_LINK_TIMEOUT (1 * HZ)
#define RTL8125_ESD_TIMEOUT (2 * HZ)
@ -412,18 +452,29 @@ This is free software, and you are welcome to redistribute it under certain cond
#define RX_BUF_SIZE 0x05F3 /* 0x05F3 = 1522bye + 1 */
#define R8125_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
#define R8125_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
#define R8125_MAX_TX_QUEUES (2)
#define R8125_MAX_RX_QUEUES (4)
#define R8125_MAX_QUEUES R8125_MAX_RX_QUEUES
#ifdef ENABLE_LIB_SUPPORT
#define R8125_MULTI_RX_Q(tp) 1
#else
#define R8125_MULTI_RX_Q(tp) (tp->num_rx_rings > 1)
#endif
#define NODE_ADDRESS_SIZE 6
#define SHORT_PACKET_PADDING_BUF_SIZE 256
#define RTK_MAGIC_DEBUG_VALUE 0x0badbeef
/* write/read MMIO register */
#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
#define RTL_R8(reg) readb (ioaddr + (reg))
#define RTL_R16(reg) readw (ioaddr + (reg))
#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
#define RTL_R32(tp, reg) ((unsigned long) readl(tp->mmio_addr + (reg)))
#ifndef DMA_64BIT_MASK
#define DMA_64BIT_MASK 0xffffffffffffffffULL
@ -479,6 +530,14 @@ This is free software, and you are welcome to redistribute it under certain cond
#define RTK_ADVERTISE_2500FULL 0x80
/* Tx NO CLOSE */
#define MAX_TX_NO_CLOSE_DESC_PTR_V2 0x10000
#define TX_NO_CLOSE_SW_PTR_MASK_V2 0x1FFFF
#ifndef ETH_MIN_MTU
#define ETH_MIN_MTU 68
#endif
/*****************************************************************************/
//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3)
@ -1009,14 +1068,6 @@ struct _kc_ethtool_pauseparam {
/*****************************************************************************/
enum RTL8125_DSM_STATE {
DSM_MAC_INIT = 1,
DSM_NIC_GOTO_D3 = 2,
DSM_IF_DOWN = 3,
DSM_NIC_RESUME_D3 = 4,
DSM_IF_UP = 5,
};
enum RTL8125_registers {
MAC0 = 0x00, /* Ethernet hardware address. */
MAC4 = 0x04,
@ -1029,6 +1080,7 @@ enum RTL8125_registers {
TxHDescStartAddrLow = 0x28,
TxHDescStartAddrHigh = 0x2c,
FLASH = 0x30,
INT_CFG0_8125 = 0x34,
ERSR = 0x36,
ChipCmd = 0x37,
TxPoll = 0x38,
@ -1056,6 +1108,7 @@ enum RTL8125_registers {
PMCH = 0x6F,
ERIDR = 0x70,
ERIAR = 0x74,
INT_CFG1_8125 = 0x7A,
EPHY_RXER_NUM = 0x7C,
EPHYAR = 0x80,
TimeInt2 = 0x8C,
@ -1089,6 +1142,12 @@ enum RTL8125_registers {
IMR0_8125 = 0x38,
ISR0_8125 = 0x3C,
TPPOLL_8125 = 0x90,
IMR1_8125 = 0x800,
ISR1_8125 = 0x802,
IMR2_8125 = 0x804,
ISR2_8125 = 0x806,
IMR3_8125 = 0x808,
ISR3_8125 = 0x80A,
BACKUP_ADDR0_8125 = 0x19E0,
BACKUP_ADDR1_8125 = 0X19E4,
TCTR0_8125 = 0x0048,
@ -1099,6 +1158,32 @@ enum RTL8125_registers {
TIMER_INT1_8125 = 0x005C,
TIMER_INT2_8125 = 0x008C,
TIMER_INT3_8125 = 0x00F4,
INT_MITI_V2_0_RX = 0x0A00,
INT_MITI_V2_0_TX = 0x0A02,
INT_MITI_V2_1_TX = 0x0A0A,
IMR_V2_CLEAR_REG_8125 = 0x0D00,
ISR_V2_8125 = 0x0D04,
IMR_V2_SET_REG_8125 = 0x0D0C,
TNPDS_Q1_LOW_8125 = 0x2100,
SW_TAIL_PTR0_8125 = 0x2800,
HW_CLO_PTR0_8125 = 0x2802,
RDSAR_Q1_LOW_8125 = 0x4000,
RSS_CTRL_8125 = 0x4500,
Q_NUM_CTRL_8125 = 0x4800,
EEE_TXIDLE_TIMER_8125 = 0x6048,
PTP_CTRL_8125 = 0x6800,
PTP_STATUS_8125 = 0x6802,
PTP_ISR_8125 = 0x6804,
PTP_IMR_8125 = 0x6805,
PTP_TIME_CORRECT_CMD_8125 = 0x6806,
PTP_SOFT_CONFIG_Time_NS_8125 = 0x6808,
PTP_SOFT_CONFIG_Time_S_8125 = 0x680C,
PTP_LOCAL_Time_SUB_NS_8125 = 0x6814,
PTP_LOCAL_Time_NS_8125 = 0x6818,
PTP_LOCAL_Time_S_8125 = 0x681C,
PTP_Time_SHIFTER_S_8125 = 0x6856,
PPS_RISE_TIME_NS_8125 = 0x68A0,
PPS_RISE_TIME_S_8125 = 0x68A4,
};
enum RTL8125_register_content {
@ -1114,6 +1199,8 @@ enum RTL8125_register_content {
TxOK = 0x0004,
RxErr = 0x0002,
RxOK = 0x0001,
RxDU1 = 0x0002,
RxOK1 = 0x0001,
/* RxStatusDesc */
RxRWT = (1 << 22),
@ -1121,6 +1208,11 @@ enum RTL8125_register_content {
RxRUNT = (1 << 20),
RxCRC = (1 << 19),
RxRWT_V3 = (1 << 18),
RxRES_V3 = (1 << 20),
RxRUNT_V3 = (1 << 19),
RxCRC_V3 = (1 << 17),
/* ChipCmdBits */
StopReq = 0x80,
CmdReset = 0x10,
@ -1154,6 +1246,9 @@ enum RTL8125_register_content {
/* RxConfigBits */
Reserved2_shift = 13,
RxCfgDMAShift = 8,
EnableRxDescV3 = (1 << 24),
EnableOuterVlan = (1 << 23),
EnableInnerVlan = (1 << 22),
RxCfg_128_int_en = (1 << 15),
RxCfg_fet_multi_en = (1 << 14),
RxCfg_half_refetch = (1 << 13),
@ -1311,6 +1406,23 @@ enum RTL8125_register_content {
/* GPIO */
GPIO_en = (1 << 0),
/* PTP */
PTP_ISR_TOK = (1 << 1),
PTP_ISR_TER = (1 << 2),
PTP_EXEC_CMD = (1 << 7),
PTP_ADJUST_TIME_NS_NEGATIVE = (1 << 30),
PTP_ADJUST_TIME_S_NEGATIVE = (1ULL << 48),
/* New Interrupt Bits */
INT_CFG0_ENABLE_8125 = (1 << 0),
INT_CFG0_TIMEOUT0_BYPASS_8125 = (1 << 1),
INT_CFG0_MITIGATION_BYPASS_8125 = (1 << 2),
ISRIMR_V2_ROK_Q0 = (1 << 0),
ISRIMR_TOK_Q0 = (1 << 16),
ISRIMR_TOK_Q1 = (1 << 18),
/* Magic Number */
RTL8125_MAGIC_NUMBER = 0x0badbadbadbadbadull,
};
enum _DescStatusBit {
@ -1319,6 +1431,11 @@ enum _DescStatusBit {
FirstFrag = (1 << 29), /* First segment of a packet */
LastFrag = (1 << 28), /* Final segment of a packet */
DescOwn_V3 = (DescOwn), /* Descriptor is owned by NIC */
RingEnd_V3 = (RingEnd), /* End of descriptor ring */
FirstFrag_V3 = (1 << 25), /* First segment of a packet */
LastFrag_V3 = (1 << 24), /* Final segment of a packet */
/* Tx private */
/*------ offset 0 of tx descriptor ------*/
LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
@ -1332,12 +1449,12 @@ enum _DescStatusBit {
TxTCPCS = (1 << 16), /* Calculate TCP/IP checksum */
TxVlanTag = (1 << 17), /* Add VLAN tag */
/*@@@@@@ offset 4 of tx descriptor => bits for RTL8125C/CP only begin @@@@@@*/
/*@@@@@@ offset 4 of tx descriptor => bits for RTL8125 only begin @@@@@@*/
TxUDPCS_C = (1 << 31), /* Calculate UDP/IP checksum */
TxTCPCS_C = (1 << 30), /* Calculate TCP/IP checksum */
TxIPCS_C = (1 << 29), /* Calculate IP checksum */
TxIPV6F_C = (1 << 28), /* Indicate it is an IPv6 packet */
/*@@@@@@ offset 4 of tx descriptor => bits for RTL8125C/CP only end @@@@@@*/
/*@@@@@@ offset 4 of tx descriptor => bits for RTL8125 only end @@@@@@*/
/* Rx private */
@ -1355,20 +1472,47 @@ enum _DescStatusBit {
RxTCPF = (1 << 14), /* TCP/IP checksum failed */
RxVlanTag = (1 << 16), /* VLAN tag available */
/*@@@@@@ offset 0 of rx descriptor => bits for RTL8125C/CP only begin @@@@@@*/
/*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only begin @@@@@@*/
RxUDPT = (1 << 18),
RxTCPT = (1 << 17),
/*@@@@@@ offset 0 of rx descriptor => bits for RTL8125C/CP only end @@@@@@*/
/*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only end @@@@@@*/
/*@@@@@@ offset 4 of rx descriptor => bits for RTL8125C/CP only begin @@@@@@*/
/*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only begin @@@@@@*/
RxV6F = (1 << 31),
RxV4F = (1 << 30),
/*@@@@@@ offset 4 of rx descriptor => bits for RTL8125C/CP only end @@@@@@*/
/*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only end @@@@@@*/
PID1_v3 = (1 << 29), /* Protocol ID bit 1/2 */
PID0_v3 = (1 << 28), /* Protocol ID bit 2/2 */
#define RxProtoUDP_v3 (PID1_v3)
#define RxProtoTCP_v3 (PID0_v3)
#define RxProtoIP_v3 (PID1_v3 | PID0_v3)
#define RxProtoMask_v3 RxProtoIP_v3
RxIPF_v3 = (1 << 26), /* IP checksum failed */
RxUDPF_v3 = (1 << 25), /* UDP/IP checksum failed */
RxTCPF_v3 = (1 << 24), /* TCP/IP checksum failed */
RxSCTPF_v3 = (1 << 23), /* TCP/IP checksum failed */
RxVlanTag_v3 = (RxVlanTag), /* VLAN tag available */
/*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only begin @@@@@@*/
RxUDPT_v3 = (1 << 29),
RxTCPT_v3 = (1 << 28),
RxSCTP_v3 = (1 << 27),
/*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only end @@@@@@*/
/*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only begin @@@@@@*/
RxV6F_v3 = (RxV6F),
RxV4F_v3 = (RxV4F),
/*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only end @@@@@@*/
};
enum features {
// RTL_FEATURE_WOL = (1 << 0),
RTL_FEATURE_MSI = (1 << 1),
RTL_FEATURE_MSIX = (1 << 2),
};
enum wol_capability {
@ -1419,6 +1563,7 @@ enum effuse {
EFUSE_SUPPORT_V4,
};
#define RsvdMask 0x3fffc000
#define RsvdMaskV3 0x3fff8000
struct TxDesc {
u32 opts1;
@ -1436,6 +1581,76 @@ struct RxDesc {
u64 addr;
};
struct RxDescV3 {
union {
struct {
u32 rsv1;
u32 rsv2;
} RxDescDDWord1;
};
union {
struct {
u32 RSSResult;
u16 HeaderBufferLen;
u16 HeaderInfo;
} RxDescNormalDDWord2;
struct {
u32 rsv5;
u32 rsv6;
} RxDescDDWord2;
};
union {
u64 addr;
struct {
u32 TimeStampLow;
u32 TimeStampHigh;
} RxDescTimeStamp;
struct {
u32 rsv8;
u32 rsv9;
} RxDescDDWord3;
};
union {
struct {
u32 opts2;
u32 opts1;
} RxDescNormalDDWord4;
struct {
u16 TimeStampHHigh;
u16 rsv11;
u32 opts1;
} RxDescPTPDDWord4;
};
};
enum rxdesc_type {
RXDESC_TYPE_NORMAL=0,
RXDESC_TYPE_NEXT,
RXDESC_TYPE_PTP,
RXDESC_TYPE_MAX
};
//Rx Desc Type
enum rx_desc_ring_type {
RX_DESC_RING_TYPE_UNKNOWN=0,
RX_DESC_RING_TYPE_1,
RX_DESC_RING_TYPE_2,
RX_DESC_RING_TYPE_3,
RX_DESC_RING_TYPE_MAX
};
enum rx_desc_len {
RX_DESC_LEN_TYPE_1 = (sizeof(struct RxDesc)),
RX_DESC_LEN_TYPE_3 = (sizeof(struct RxDescV3))
};
struct ring_info {
struct sk_buff *skb;
u32 len;
@ -1462,15 +1677,65 @@ struct pci_resource {
u32 pci_sn_h;
};
struct rtl8125_private {
void __iomem *mmio_addr; /* memory map physical address */
struct pci_dev *pci_dev; /* Index of PCI device */
struct net_device *dev;
struct rtl8125_tx_ring {
void* priv;
u32 index;
u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
u32 dirty_tx;
struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
dma_addr_t TxPhyAddr;
struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
u32 NextHwDesCloPtr;
u32 BeginHwDesCloPtr;
u16 hw_clo_ptr_reg;
u16 sw_tail_ptr_reg;
u16 tdsar_reg; /* Transmit Descriptor Start Address */
};
struct rtl8125_rx_ring {
void* priv;
u32 index;
u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
u32 dirty_rx;
struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
u64 RxDescPhyAddr[NUM_RX_DESC]; /* Rx desc physical address*/
dma_addr_t RxPhyAddr;
struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
u16 rdsar_reg; /* Receive Descriptor Start Address */
};
struct r8125_napi {
#ifdef CONFIG_R8125_NAPI
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
struct napi_struct napi;
#endif
#endif
void* priv;
int index;
};
struct r8125_irq {
irq_handler_t handler;
unsigned int vector;
u8 requested;
char name[IFNAMSIZ + 10];
};
struct rtl8125_private {
void __iomem *mmio_addr; /* memory map physical address */
struct pci_dev *pci_dev; /* Index of PCI device */
struct net_device *dev;
struct r8125_napi r8125napi[R8125_MAX_MSIX_VEC];
struct r8125_irq irq_tbl[R8125_MAX_MSIX_VEC];
unsigned int irq_nvecs;
unsigned int max_irq_nvecs;
unsigned int min_irq_nvecs;
//struct msix_entry msix_entries[R8125_MAX_MSIX_VEC];
struct net_device_stats stats; /* statistics of net device */
spinlock_t lock; /* spin lock flag */
u32 msg_enable;
@ -1481,17 +1746,28 @@ struct rtl8125_private {
int max_jumbo_frame_size;
int chipset;
u32 mcfg;
u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
u32 dirty_rx;
u32 dirty_tx;
struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
dma_addr_t TxPhyAddr;
dma_addr_t RxPhyAddr;
struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
//u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
//u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
//u32 dirty_rx;
//u32 dirty_tx;
//struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
//struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
//dma_addr_t TxPhyAddr;
//dma_addr_t RxPhyAddr;
//struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
//struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
unsigned rx_buf_sz;
u16 HwSuppNumTxQueues;
u16 HwSuppNumRxQueues;
unsigned int num_tx_rings;
unsigned int num_rx_rings;
struct rtl8125_tx_ring tx_ring[R8125_MAX_TX_QUEUES];
struct rtl8125_rx_ring rx_ring[R8125_MAX_RX_QUEUES];
#ifdef ENABLE_LIB_SUPPORT
struct atomic_notifier_head lib_nh;
struct rtl8125_ring lib_tx_ring[R8125_MAX_TX_QUEUES];
struct rtl8125_ring lib_rx_ring[R8125_MAX_RX_QUEUES];
#endif
struct timer_list esd_timer;
struct timer_list link_timer;
struct pci_resource pci_cfg_space;
@ -1501,6 +1777,8 @@ struct rtl8125_private {
u16 cp_cmd;
u32 intr_mask;
u32 timer_intr_mask;
u16 isr_reg[R8125_MAX_QUEUES];
u16 imr_reg[R8125_MAX_QUEUES];
int phy_auto_nego_reg;
int phy_1000_ctrl_reg;
int phy_2500_ctrl_reg;
@ -1562,6 +1840,7 @@ struct rtl8125_private {
u8 ShortPacketSwChecksum;
u8 UseSwPaddingShortPkt;
u16 SwPaddingShortPktLen;
void *ShortPacketEmptyBuffer;
dma_addr_t ShortPacketEmptyBufferPhy;
@ -1576,6 +1855,10 @@ struct rtl8125_private {
u8 RequiredSecLanDonglePatch;
u8 RequirePhyMdiSwapPatch;
u8 RequireLSOPatch;
u32 HwFiberModeVer;
u32 HwFiberStat;
u8 HwSwitchMdiToFiber;
@ -1594,6 +1877,14 @@ struct rtl8125_private {
u32 HwPcieSNOffset;
u8 HwSuppTxNoCloseVer;
u8 EnableTxNoClose;
u8 HwSuppIsrVer;
u8 HwCurrIsrVer;
u8 HwSuppIntMitiVer;
//Dash+++++++++++++++++
u8 HwSuppDashVer;
u8 DASH;
@ -1683,12 +1974,96 @@ struct rtl8125_private {
//Realwow--------------
#endif //ENABLE_REALWOW_SUPPORT
u32 eee_adv_t;
u8 eee_enabled;
#ifdef ENABLE_R8125_PROCFS
//Procfs support
struct proc_dir_entry *proc_dir;
#endif
u8 InitRxDescType;
u16 RxDescLength; //V1 16 Byte V2 32 Bytes
u32 RxDescRingLength;
u8 HwSuppPtpVer;
u8 EnablePtp;
s64 ptp_adjust;
#ifdef ENABLE_PTP_SUPPORT
u32 tx_hwtstamp_timeouts;
u32 tx_hwtstamp_skipped;
struct work_struct ptp_tx_work;
struct sk_buff *ptp_tx_skb;
struct hwtstamp_config hwtstamp_config;
unsigned long ptp_tx_start;
struct ptp_clock_info ptp_clock_info;
struct ptp_clock *ptp_clock;
#endif
u8 HwSuppRssVer;
u8 EnableRss;
u16 HwSuppIndirTblEntries;
#ifdef ENABLE_RSS_SUPPORT
u32 rss_flags;
/* Receive Side Scaling settings */
#define RTL8125_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
u8 rss_key[RTL8125_RSS_KEY_SIZE];
#define RTL8125_MAX_INDIRECTION_TABLE_ENTRIES 128
u8 rss_indir_tbl[RTL8125_MAX_INDIRECTION_TABLE_ENTRIES];
u32 rss_options;
#endif
};
#ifdef ENABLE_LIB_SUPPORT
static inline unsigned int
rtl8125_num_lib_tx_rings(struct rtl8125_private *tp)
{
int count, i;
for (count = 0, i = tp->num_tx_rings; i < tp->HwSuppNumTxQueues; i++)
if(tp->lib_tx_ring[i].enabled)
count++;
return count;
}
static inline unsigned int
rtl8125_num_lib_rx_rings(struct rtl8125_private *tp)
{
int count, i;
for (count = 0, i = tp->num_rx_rings; i < tp->HwSuppNumRxQueues; i++)
if(tp->lib_rx_ring[i].enabled)
count++;
return count;
}
#else
static inline unsigned int
rtl8125_num_lib_tx_rings(struct rtl8125_private *tp)
{
return 0;
}
static inline unsigned int
rtl8125_num_lib_rx_rings(struct rtl8125_private *tp)
{
return 0;
}
#endif
static inline unsigned int
rtl8125_tot_tx_rings(struct rtl8125_private *tp)
{
return tp->num_tx_rings + rtl8125_num_lib_tx_rings(tp);
}
static inline unsigned int
rtl8125_tot_rx_rings(struct rtl8125_private *tp)
{
return tp->num_rx_rings + rtl8125_num_lib_rx_rings(tp);
}
enum eetype {
EEPROM_TYPE_NONE=0,
EEPROM_TYPE_93C46,
@ -1697,8 +2072,10 @@ enum eetype {
};
enum mcfg {
CFG_METHOD_2=0,
CFG_METHOD_2=2,
CFG_METHOD_3,
CFG_METHOD_4,
CFG_METHOD_5,
CFG_METHOD_MAX,
CFG_METHOD_DEFAULT = 0xFF
};
@ -1731,18 +2108,22 @@ enum mcfg {
//Ram Code Version
#define NIC_RAMCODE_VERSION_CFG_METHOD_2 (0x0b11)
#define NIC_RAMCODE_VERSION_CFG_METHOD_3 (0x0b33)
#define NIC_RAMCODE_VERSION_CFG_METHOD_4 (0x0b17)
#define NIC_RAMCODE_VERSION_CFG_METHOD_5 (0x0b36)
//hwoptimize
#define HW_PATCH_SOC_LAN (BIT_0)
#define HW_PATCH_SAMSUNG_LAN_DONGLE (BIT_2)
static const u16 other_q_intr_mask = (RxOK1 | RxDU1);
void rtl8125_mdio_write(struct rtl8125_private *tp, u32 RegAddr, u32 value);
void rtl8125_mdio_prot_write(struct rtl8125_private *tp, u32 RegAddr, u32 value);
void rtl8125_mdio_prot_write_phy_ocp(struct rtl8125_private *tp, u32 RegAddr, u32 value);
void rtl8125_mdio_prot_direct_write_phy_ocp(struct rtl8125_private *tp, u32 RegAddr, u32 value);
u32 rtl8125_mdio_read(struct rtl8125_private *tp, u32 RegAddr);
u32 rtl8125_mdio_prot_read(struct rtl8125_private *tp, u32 RegAddr);
u32 rtl8125_mdio_prot_read_phy_ocp(struct rtl8125_private *tp, u32 RegAddr);
void rtl8125_ephy_write(void __iomem *ioaddr, int RegAddr, int value);
u32 rtl8125_mdio_prot_direct_read_phy_ocp(struct rtl8125_private *tp, u32 RegAddr);
void rtl8125_ephy_write(struct rtl8125_private *tp, int RegAddr, int value);
void rtl8125_mac_ocp_write(struct rtl8125_private *tp, u16 reg_addr, u16 value);
u16 rtl8125_mac_ocp_read(struct rtl8125_private *tp, u16 reg_addr);
void rtl8125_clear_eth_phy_bit(struct rtl8125_private *tp, u8 addr, u16 mask);
@ -1750,16 +2131,17 @@ void rtl8125_set_eth_phy_bit(struct rtl8125_private *tp, u8 addr, u16 mask);
void rtl8125_ocp_write(struct rtl8125_private *tp, u16 addr, u8 len, u32 data);
void rtl8125_oob_notify(struct rtl8125_private *tp, u8 cmd);
void rtl8125_init_ring_indexes(struct rtl8125_private *tp);
int rtl8125_eri_write(void __iomem *ioaddr, int addr, int len, u32 value, int type);
int rtl8125_eri_write(struct rtl8125_private *tp, int addr, int len, u32 value, int type);
void rtl8125_oob_mutex_lock(struct rtl8125_private *tp);
u32 rtl8125_mdio_read(struct rtl8125_private *tp, u32 RegAddr);
u32 rtl8125_ocp_read(struct rtl8125_private *tp, u16 addr, u8 len);
u32 rtl8125_ocp_read_with_oob_base_address(struct rtl8125_private *tp, u16 addr, u8 len, u32 base_address);
u32 rtl8125_ocp_write_with_oob_base_address(struct rtl8125_private *tp, u16 addr, u8 len, u32 value, u32 base_address);
u32 rtl8125_eri_read(void __iomem *ioaddr, int addr, int len, int type);
u32 rtl8125_eri_read_with_oob_base_address(void __iomem *ioaddr, int addr, int len, int type, u32 base_address);
int rtl8125_eri_write_with_oob_base_address(void __iomem *ioaddr, int addr, int len, u32 value, int type, u32 base_address);
u16 rtl8125_ephy_read(void __iomem *ioaddr, int RegAddr);
u32 rtl8125_eri_read(struct rtl8125_private *tp, int addr, int len, int type);
u32 rtl8125_eri_read_with_oob_base_address(struct rtl8125_private *tp, int addr, int len, int type, u32 base_address);
int rtl8125_eri_write(struct rtl8125_private *tp, int addr, int len, u32 value, int type);
int rtl8125_eri_write_with_oob_base_address(struct rtl8125_private *tp, int addr, int len, u32 value, int type, u32 base_address);
u16 rtl8125_ephy_read(struct rtl8125_private *tp, int RegAddr);
void rtl8125_wait_txrx_fifo_empty(struct net_device *dev);
void rtl8125_enable_now_is_oob(struct rtl8125_private *tp);
void rtl8125_disable_now_is_oob(struct rtl8125_private *tp);
@ -1769,8 +2151,61 @@ void rtl8125_dash2_enable_tx(struct rtl8125_private *tp);
void rtl8125_dash2_disable_rx(struct rtl8125_private *tp);
void rtl8125_dash2_enable_rx(struct rtl8125_private *tp);
void rtl8125_hw_disable_mac_mcu_bps(struct net_device *dev);
void rtl8125_mark_to_asic(struct rtl8125_private *tp, struct RxDesc *desc, u32 rx_buf_sz);
static inline void
rtl8125_make_unusable_by_asic(struct rtl8125_private *tp,
struct RxDesc *desc)
{
if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) {
((struct RxDescV3 *)desc)->addr = RTL8125_MAGIC_NUMBER;
((struct RxDescV3 *)desc)->RxDescNormalDDWord4.opts1 &= ~cpu_to_le32(DescOwn | RsvdMaskV3);
} else {
desc->addr = RTL8125_MAGIC_NUMBER;
desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
}
}
static inline struct RxDesc*
rtl8125_get_rxdesc(struct rtl8125_private *tp, struct RxDesc *RxDescBase, u32 const cur_rx)
{
return (struct RxDesc*)((u8*)RxDescBase + (cur_rx * tp->RxDescLength));
}
static inline void
rtl8125_disable_hw_interrupt_v2(struct rtl8125_private *tp,
u32 message_id)
{
RTL_W32(tp, IMR_V2_CLEAR_REG_8125, BIT(message_id));
}
static inline void
rtl8125_enable_hw_interrupt_v2(struct rtl8125_private *tp, u32 message_id)
{
RTL_W32(tp, IMR_V2_SET_REG_8125, BIT(message_id));
}
void rtl8125_hw_set_timer_int_8125(struct rtl8125_private *tp, u32 message_id, u8 timer_intmiti_val);
void rtl8125_set_rx_q_num(struct rtl8125_private *tp, unsigned int num_rx_queues);
void rtl8125_set_tx_q_num(struct rtl8125_private *tp, unsigned int num_tx_queues);
int rtl8125_set_real_num_queue(struct rtl8125_private *tp);
void rtl8125_hw_start(struct net_device *dev);
void rtl8125_hw_reset(struct net_device *dev);
void rtl8125_tx_clear(struct rtl8125_private *tp);
void rtl8125_rx_clear(struct rtl8125_private *tp);
int rtl8125_init_ring(struct net_device *dev);
void rtl8125_hw_set_rx_packet_filter(struct net_device *dev);
#ifdef ENABLE_LIB_SUPPORT
void rtl8125_lib_reset_prepare(struct rtl8125_private *tp);
void rtl8125_lib_reset_complete(struct rtl8125_private *tp);
#else
static inline void rtl8125_lib_reset_prepare(struct rtl8125_private *tp) { }
static inline void rtl8125_lib_reset_complete(struct rtl8125_private *tp) { }
#endif
#define HW_SUPPORT_CHECK_PHY_DISABLE_MODE(_M) ((_M)->HwSuppCheckPhyDisableModeVer > 0 )
#define HW_HAS_WRITE_PHY_MCU_RAM_CODE(_M) (((_M)->HwHasWrRamCodeToMicroP == TRUE) ? 1 : 0)
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)
#define netdev_mc_count(dev) ((dev)->mc_count)
@ -1778,3 +2213,5 @@ void rtl8125_hw_disable_mac_mcu_bps(struct net_device *dev);
#define netdev_for_each_mc_addr(mclist, dev) \
for (mclist = dev->mc_list; mclist; mclist = mclist->next)
#endif
#endif /* __R8125_H */

17
package/lean/r8125/src/r8125_dash.h
View File

@ -1,10 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
################################################################################
#
# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
# controllers with PCI-Express interface.
#
# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved.
# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
@ -34,6 +35,8 @@
#ifndef _LINUX_R8125_DASH_H
#define _LINUX_R8125_DASH_H
#include <linux/if.h>
#define SIOCDEVPRIVATE_RTLDASH SIOCDEVPRIVATE+2
enum rtl_dash_cmd {
@ -241,12 +244,12 @@ RX_DASH_BUFFER_TYPE_2, *PRX_DASH_BUFFER_TYPE_2;
#define CMAC_TXDESC_OFFSET 0x98 //TX: 0x98 - 0x9F
/* cmac write/read MMIO register */
#define RTL_CMAC_W8(reg, val8) writeb ((val8), tp->cmac_ioaddr + (reg))
#define RTL_CMAC_W16(reg, val16) writew ((val16), tp->cmac_ioaddr + (reg))
#define RTL_CMAC_W32(reg, val32) writel ((val32), tp->cmac_ioaddr + (reg))
#define RTL_CMAC_R8(reg) readb (tp->cmac_ioaddr + (reg))
#define RTL_CMAC_R16(reg) readw (tp->cmac_ioaddr + (reg))
#define RTL_CMAC_R32(reg) ((unsigned long) readl (tp->cmac_ioaddr + (reg)))
#define RTL_CMAC_W8(tp, reg, val8) writeb ((val8), tp->cmac_ioaddr + (reg))
#define RTL_CMAC_W16(tp, reg, val16) writew ((val16), tp->cmac_ioaddr + (reg))
#define RTL_CMAC_W32(tp, reg, val32) writel ((val32), tp->cmac_ioaddr + (reg))
#define RTL_CMAC_R8(tp, reg) readb (tp->cmac_ioaddr + (reg))
#define RTL_CMAC_R16(tp, reg) readw (tp->cmac_ioaddr + (reg))
#define RTL_CMAC_R32(tp, reg) ((unsigned long) readl (tp->cmac_ioaddr + (reg)))
int rtl8125_dash_ioctl(struct net_device *dev, struct ifreq *ifr);
void HandleDashInterrupt(struct net_device *dev);

6109
package/lean/r8125/src/r8125_n.c
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File diff suppressed because it is too large Load Diff

81
package/lean/r8125/src/r8125_ptp.h Normal file
View File

@ -0,0 +1,81 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
################################################################################
#
# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
# controllers with PCI-Express interface.
#
# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License along with
# this program; if not, see <http://www.gnu.org/licenses/>.
#
# Author:
# Realtek NIC software team <nicfae@realtek.com>
# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
#
################################################################################
*/
/************************************************************************************
* This product is covered by one or more of the following patents:
* US6,570,884, US6,115,776, and US6,327,625.
***********************************************************************************/
#ifndef _LINUX_rtl8125_PTP_H
#define _LINUX_rtl8125_PTP_H
#include <linux/ktime.h>
#include <linux/timecounter.h>
#include <linux/net_tstamp.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/ptp_classify.h>
struct rtl8125_ptp_info {
s64 time_sec;
u32 time_ns;
u16 ts_info;
};
#ifndef _STRUCT_TIMESPEC
#define _STRUCT_TIMESPEC
struct timespec {
__kernel_old_time_t tv_sec; /* seconds */
long tv_nsec; /* nanoseconds */
};
#endif
enum PTP_CMD_TYPE {
PTP_CMD_SET_LOCAL_TIME = 0,
PTP_CMD_DRIFT_LOCAL_TIME,
PTP_CMD_LATCHED_LOCAL_TIME,
};
struct rtl8125_private;
struct RxDescV3;
int rtl8125_get_ts_info(struct net_device *netdev,
struct ethtool_ts_info *info);
void rtl8125_ptp_reset(struct rtl8125_private *tp);
void rtl8125_ptp_init(struct rtl8125_private *tp);
void rtl8125_ptp_suspend(struct rtl8125_private *tp);
void rtl8125_ptp_stop(struct rtl8125_private *tp);
int rtl8125_ptp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
void rtl8125_rx_ptp_pktstamp(struct rtl8125_private *tp, struct sk_buff *skb,
struct RxDescV3 *descv3);
#endif /* _LINUX_rtl8125_PTP_H */

3
package/lean/r8125/src/r8125_realwow.h
View File

@ -1,10 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
################################################################################
#
# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
# controllers with PCI-Express interface.
#
# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved.
# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free

66
package/lean/r8125/src/r8125_rss.h Normal file
View File

@ -0,0 +1,66 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
################################################################################
#
# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
# controllers with PCI-Express interface.
#
# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License along with
# this program; if not, see <http://www.gnu.org/licenses/>.
#
# Author:
# Realtek NIC software team <nicfae@realtek.com>
# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
#
################################################################################
*/
/************************************************************************************
* This product is covered by one or more of the following patents:
* US6,570,884, US6,115,776, and US6,327,625.
***********************************************************************************/
#ifndef _LINUX_rtl8125_RSS_H
#define _LINUX_rtl8125_RSS_H
#include <linux/netdevice.h>
#include <linux/types.h>
enum rtl8125_rss_flag {
RTL_8125_RSS_FLAG_HASH_UDP_IPV4 = (1 << 0),
RTL_8125_RSS_FLAG_HASH_UDP_IPV6 = (1 << 1),
};
struct rtl8125_private;
int rtl8125_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
u32 *rule_locs);
int rtl8125_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
u32 rtl8125_get_rxfh_key_size(struct net_device *netdev);
u32 rtl8125_rss_indir_size(struct net_device *netdev);
int rtl8125_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
u8 *hfunc);
int rtl8125_set_rxfh(struct net_device *netdev, const u32 *indir,
const u8 *key, const u8 hfunc);
void rtl8125_rx_hash(struct rtl8125_private *tp,
struct RxDescV3 *descv3,
struct sk_buff *skb);
void _rtl8125_config_rss(struct rtl8125_private *tp);
void rtl8125_config_rss(struct rtl8125_private *tp);
void rtl8125_init_rss(struct rtl8125_private *tp);
u32 rtl8125_rss_indir_tbl_entries(struct rtl8125_private *tp);
void rtl8125_disable_rss(struct rtl8125_private *tp);
#endif /* _LINUX_rtl8125_RSS_H */

118
package/lean/r8125/src/rtl_eeprom.c
View File

@ -1,10 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
################################################################################
#
# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
# controllers with PCI-Express interface.
#
# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved.
# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
@ -52,18 +53,17 @@
//-------------------------------------------------------------------
void rtl8125_eeprom_type(struct rtl8125_private *tp)
{
void __iomem *ioaddr=tp->mmio_addr;
u16 magic = 0;
if (tp->mcfg == CFG_METHOD_DEFAULT)
goto out_no_eeprom;
if(RTL_R8(0xD2)&0x04) {
if(RTL_R8(tp, 0xD2)&0x04) {
//not support
//tp->eeprom_type = EEPROM_TWSI;
//tp->eeprom_len = 256;
goto out_no_eeprom;
} else if(RTL_R32(RxConfig) & RxCfg_9356SEL) {
} else if(RTL_R32(tp, RxConfig) & RxCfg_9356SEL) {
tp->eeprom_type = EEPROM_TYPE_93C56;
tp->eeprom_len = 256;
} else {
@ -80,28 +80,28 @@ out_no_eeprom:
}
}
void rtl8125_eeprom_cleanup(void __iomem *ioaddr)
void rtl8125_eeprom_cleanup(struct rtl8125_private *tp)
{
u8 x;
x = RTL_R8(Cfg9346);
x = RTL_R8(tp, Cfg9346);
x &= ~(Cfg9346_EEDI | Cfg9346_EECS);
RTL_W8(Cfg9346, x);
RTL_W8(tp, Cfg9346, x);
rtl8125_raise_clock(&x, ioaddr);
rtl8125_lower_clock(&x, ioaddr);
rtl8125_raise_clock(tp, &x);
rtl8125_lower_clock(tp, &x);
}
int rtl8125_eeprom_cmd_done(void __iomem *ioaddr)
int rtl8125_eeprom_cmd_done(struct rtl8125_private *tp)
{
u8 x;
int i;
rtl8125_stand_by(ioaddr);
rtl8125_stand_by(tp);
for (i = 0; i < 50000; i++) {
x = RTL_R8(Cfg9346);
x = RTL_R8(tp, Cfg9346);
if (x & Cfg9346_EEDO) {
udelay(RTL_CLOCK_RATE * 2 * 3);
@ -119,7 +119,6 @@ int rtl8125_eeprom_cmd_done(void __iomem *ioaddr)
//-------------------------------------------------------------------
u16 rtl8125_eeprom_read_sc(struct rtl8125_private *tp, u16 reg)
{
void __iomem *ioaddr=tp->mmio_addr;
int addr_sz = 6;
u8 x;
u16 data;
@ -134,16 +133,16 @@ u16 rtl8125_eeprom_read_sc(struct rtl8125_private *tp, u16 reg)
addr_sz = 8;
x = Cfg9346_EEM1 | Cfg9346_EECS;
RTL_W8(Cfg9346, x);
RTL_W8(tp, Cfg9346, x);
rtl8125_shift_out_bits(RTL_EEPROM_READ_OPCODE, 3, ioaddr);
rtl8125_shift_out_bits(reg, addr_sz, ioaddr);
rtl8125_shift_out_bits(tp, RTL_EEPROM_READ_OPCODE, 3);
rtl8125_shift_out_bits(tp, reg, addr_sz);
data = rtl8125_shift_in_bits(ioaddr);
data = rtl8125_shift_in_bits(tp);
rtl8125_eeprom_cleanup(ioaddr);
rtl8125_eeprom_cleanup(tp);
RTL_W8(Cfg9346, 0);
RTL_W8(tp, Cfg9346, 0);
return data;
}
@ -154,7 +153,6 @@ u16 rtl8125_eeprom_read_sc(struct rtl8125_private *tp, u16 reg)
//-------------------------------------------------------------------
void rtl8125_eeprom_write_sc(struct rtl8125_private *tp, u16 reg, u16 data)
{
void __iomem *ioaddr=tp->mmio_addr;
u8 x;
int addr_sz = 6;
int w_dummy_addr = 4;
@ -172,56 +170,56 @@ void rtl8125_eeprom_write_sc(struct rtl8125_private *tp, u16 reg, u16 data)
}
x = Cfg9346_EEM1 | Cfg9346_EECS;
RTL_W8(Cfg9346, x);
RTL_W8(tp, Cfg9346, x);
rtl8125_shift_out_bits(RTL_EEPROM_EWEN_OPCODE, 5, ioaddr);
rtl8125_shift_out_bits(reg, w_dummy_addr, ioaddr);
rtl8125_stand_by(ioaddr);
rtl8125_shift_out_bits(tp, RTL_EEPROM_EWEN_OPCODE, 5);
rtl8125_shift_out_bits(tp, reg, w_dummy_addr);
rtl8125_stand_by(tp);
rtl8125_shift_out_bits(RTL_EEPROM_ERASE_OPCODE, 3, ioaddr);
rtl8125_shift_out_bits(reg, addr_sz, ioaddr);
if (rtl8125_eeprom_cmd_done(ioaddr) < 0) {
rtl8125_shift_out_bits(tp, RTL_EEPROM_ERASE_OPCODE, 3);
rtl8125_shift_out_bits(tp, reg, addr_sz);
if (rtl8125_eeprom_cmd_done(tp) < 0) {
return;
}
rtl8125_stand_by(ioaddr);
rtl8125_stand_by(tp);
rtl8125_shift_out_bits(RTL_EEPROM_WRITE_OPCODE, 3, ioaddr);
rtl8125_shift_out_bits(reg, addr_sz, ioaddr);
rtl8125_shift_out_bits(data, 16, ioaddr);
if (rtl8125_eeprom_cmd_done(ioaddr) < 0) {
rtl8125_shift_out_bits(tp, RTL_EEPROM_WRITE_OPCODE, 3);
rtl8125_shift_out_bits(tp, reg, addr_sz);
rtl8125_shift_out_bits(tp, data, 16);
if (rtl8125_eeprom_cmd_done(tp) < 0) {
return;
}
rtl8125_stand_by(ioaddr);
rtl8125_stand_by(tp);
rtl8125_shift_out_bits(RTL_EEPROM_EWDS_OPCODE, 5, ioaddr);
rtl8125_shift_out_bits(reg, w_dummy_addr, ioaddr);
rtl8125_shift_out_bits(tp, RTL_EEPROM_EWDS_OPCODE, 5);
rtl8125_shift_out_bits(tp, reg, w_dummy_addr);
rtl8125_eeprom_cleanup(ioaddr);
RTL_W8(Cfg9346, 0);
rtl8125_eeprom_cleanup(tp);
RTL_W8(tp, Cfg9346, 0);
}
void rtl8125_raise_clock(u8 *x, void __iomem *ioaddr)
void rtl8125_raise_clock(struct rtl8125_private *tp, u8 *x)
{
*x = *x | Cfg9346_EESK;
RTL_W8(Cfg9346, *x);
RTL_W8(tp, Cfg9346, *x);
udelay(RTL_CLOCK_RATE);
}
void rtl8125_lower_clock(u8 *x, void __iomem *ioaddr)
void rtl8125_lower_clock(struct rtl8125_private *tp, u8 *x)
{
*x = *x & ~Cfg9346_EESK;
RTL_W8(Cfg9346, *x);
RTL_W8(tp, Cfg9346, *x);
udelay(RTL_CLOCK_RATE);
}
void rtl8125_shift_out_bits(int data, int count, void __iomem *ioaddr)
void rtl8125_shift_out_bits(struct rtl8125_private *tp, int data, int count)
{
u8 x;
int mask;
mask = 0x01 << (count - 1);
x = RTL_R8(Cfg9346);
x = RTL_R8(tp, Cfg9346);
x &= ~(Cfg9346_EEDI | Cfg9346_EEDO);
do {
@ -230,62 +228,62 @@ void rtl8125_shift_out_bits(int data, int count, void __iomem *ioaddr)
else
x &= ~Cfg9346_EEDI;
RTL_W8(Cfg9346, x);
RTL_W8(tp, Cfg9346, x);
udelay(RTL_CLOCK_RATE);
rtl8125_raise_clock(&x, ioaddr);
rtl8125_lower_clock(&x, ioaddr);
rtl8125_raise_clock(tp, &x);
rtl8125_lower_clock(tp, &x);
mask = mask >> 1;
} while(mask);
x &= ~Cfg9346_EEDI;
RTL_W8(Cfg9346, x);
RTL_W8(tp, Cfg9346, x);
}
u16 rtl8125_shift_in_bits(void __iomem *ioaddr)
u16 rtl8125_shift_in_bits(struct rtl8125_private *tp)
{
u8 x;
u16 d, i;
x = RTL_R8(Cfg9346);
x = RTL_R8(tp, Cfg9346);
x &= ~(Cfg9346_EEDI | Cfg9346_EEDO);
d = 0;
for (i = 0; i < 16; i++) {
d = d << 1;
rtl8125_raise_clock(&x, ioaddr);
rtl8125_raise_clock(tp, &x);
x = RTL_R8(Cfg9346);
x = RTL_R8(tp, Cfg9346);
x &= ~Cfg9346_EEDI;
if (x & Cfg9346_EEDO)
d |= 1;
rtl8125_lower_clock(&x, ioaddr);
rtl8125_lower_clock(tp, &x);
}
return d;
}
void rtl8125_stand_by(void __iomem *ioaddr)
void rtl8125_stand_by(struct rtl8125_private *tp)
{
u8 x;
x = RTL_R8(Cfg9346);
x = RTL_R8(tp, Cfg9346);
x &= ~(Cfg9346_EECS | Cfg9346_EESK);
RTL_W8(Cfg9346, x);
RTL_W8(tp, Cfg9346, x);
udelay(RTL_CLOCK_RATE);
x |= Cfg9346_EECS;
RTL_W8(Cfg9346, x);
RTL_W8(tp, Cfg9346, x);
}
void rtl8125_set_eeprom_sel_low(void __iomem *ioaddr)
void rtl8125_set_eeprom_sel_low(struct rtl8125_private *tp)
{
RTL_W8(Cfg9346, Cfg9346_EEM1);
RTL_W8(Cfg9346, Cfg9346_EEM1 | Cfg9346_EESK);
RTL_W8(tp, Cfg9346, Cfg9346_EEM1);
RTL_W8(tp, Cfg9346, Cfg9346_EEM1 | Cfg9346_EESK);
udelay(20);
RTL_W8(Cfg9346, Cfg9346_EEM1);
RTL_W8(tp, Cfg9346, Cfg9346_EEM1);
}

20
package/lean/r8125/src/rtl_eeprom.h
View File

@ -1,10 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
################################################################################
#
# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
# controllers with PCI-Express interface.
#
# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved.
# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
@ -41,15 +42,12 @@
#define RTL_CLOCK_RATE 3
void rtl8125_eeprom_type(struct rtl8125_private *tp);
void rtl8125_eeprom_cleanup(void __iomem *ioaddr);
void rtl8125_eeprom_cleanup(struct rtl8125_private *tp);
u16 rtl8125_eeprom_read_sc(struct rtl8125_private *tp, u16 reg);
void rtl8125_eeprom_write_sc(struct rtl8125_private *tp, u16 reg, u16 data);
void rtl8125_shift_out_bits(int data, int count, void __iomem *ioaddr);
u16 rtl8125_shift_in_bits(void __iomem *ioaddr);
void rtl8125_raise_clock(u8 *x, void __iomem *ioaddr);
void rtl8125_lower_clock(u8 *x, void __iomem *ioaddr);
void rtl8125_stand_by(void __iomem *ioaddr);
void rtl8125_set_eeprom_sel_low(void __iomem *ioaddr);
void rtl8125_shift_out_bits(struct rtl8125_private *tp, int data, int count);
u16 rtl8125_shift_in_bits(struct rtl8125_private *tp);
void rtl8125_raise_clock(struct rtl8125_private *tp, u8 *x);
void rtl8125_lower_clock(struct rtl8125_private *tp, u8 *x);
void rtl8125_stand_by(struct rtl8125_private *tp);
void rtl8125_set_eeprom_sel_low(struct rtl8125_private *tp);

15
package/lean/r8125/src/rtltool.c
View File

@ -1,10 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
################################################################################
#
# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
# controllers with PCI-Express interface.
#
# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved.
# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
@ -121,7 +122,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr)
return -EPERM;
spin_lock_irqsave(&tp->lock, flags);
my_cmd.data = rtl8125_ephy_read(tp->mmio_addr, my_cmd.offset);
my_cmd.data = rtl8125_ephy_read(tp, my_cmd.offset);
spin_unlock_irqrestore(&tp->lock, flags);
if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) {
@ -136,7 +137,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr)
return -EPERM;
spin_lock_irqsave(&tp->lock, flags);
rtl8125_ephy_write(tp->mmio_addr, my_cmd.offset, my_cmd.data);
rtl8125_ephy_write(tp, my_cmd.offset, my_cmd.data);
spin_unlock_irqrestore(&tp->lock, flags);
break;
@ -144,7 +145,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr)
my_cmd.data = 0;
if (my_cmd.len==1 || my_cmd.len==2 || my_cmd.len==4) {
spin_lock_irqsave(&tp->lock, flags);
my_cmd.data = rtl8125_eri_read(tp->mmio_addr, my_cmd.offset, my_cmd.len, ERIAR_ExGMAC);
my_cmd.data = rtl8125_eri_read(tp, my_cmd.offset, my_cmd.len, ERIAR_ExGMAC);
spin_unlock_irqrestore(&tp->lock, flags);
} else {
ret = -EOPNOTSUPP;
@ -167,7 +168,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr)
if (my_cmd.len==1 || my_cmd.len==2 || my_cmd.len==4) {
spin_lock_irqsave(&tp->lock, flags);
rtl8125_eri_write(tp->mmio_addr, my_cmd.offset, my_cmd.len, my_cmd.data, ERIAR_ExGMAC);
rtl8125_eri_write(tp, my_cmd.offset, my_cmd.len, my_cmd.data, ERIAR_ExGMAC);
spin_unlock_irqrestore(&tp->lock, flags);
} else {
ret = -EOPNOTSUPP;
@ -330,7 +331,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr)
return -EPERM;
spin_lock_irqsave(&tp->lock, flags);
my_cmd.data = rtl8125_mdio_prot_read_phy_ocp(tp, my_cmd.offset);
my_cmd.data = rtl8125_mdio_prot_direct_read_phy_ocp(tp, my_cmd.offset);
spin_unlock_irqrestore(&tp->lock, flags);
if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) {
@ -345,7 +346,7 @@ int rtl8125_tool_ioctl(struct rtl8125_private *tp, struct ifreq *ifr)
return -EPERM;
spin_lock_irqsave(&tp->lock, flags);
rtl8125_mdio_prot_write_phy_ocp(tp, my_cmd.offset, my_cmd.data);
rtl8125_mdio_prot_direct_write_phy_ocp(tp, my_cmd.offset, my_cmd.data);
spin_unlock_irqrestore(&tp->lock, flags);
break;

3
package/lean/r8125/src/rtltool.h
View File

@ -1,10 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
################################################################################
#
# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
# controllers with PCI-Express interface.
#
# Copyright(c) 2019 Realtek Semiconductor Corp. All rights reserved.
# Copyright(c) 2020 Realtek Semiconductor Corp. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free