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ath79: restore pin state on probe for ar934x-spi
If bootloader doesn't terminate its last spi operation properly before starting kernel, our first transfer in kernel becomes a continuous transfer to that request instead of a new one. Fix this flaw by restoring IOC register, which restored all pin state to default. Fixes: ebf0d8dade ("ath79: add new ar934x spi driver") Reported-by: Russell Senior <russell@personaltelco.net> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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@ -1,7 +1,7 @@
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From b518f18f89dbd49fe9403a8c92230f1af59219bc Mon Sep 17 00:00:00 2001
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From 7e161c423a232ef7ddf6c11b09ebe471dd5a23cf Mon Sep 17 00:00:00 2001
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From: Chuanhong Guo <gch981213@gmail.com>
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Date: Wed, 5 Feb 2020 18:25:37 +0800
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Subject: [PATCH 1/2] spi: add driver for ar934x spi controller
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Subject: [PATCH v4 1/2] spi: add driver for ar934x spi controller
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This patch adds driver for SPI controller found in Qualcomm Atheros
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AR934x/QCA95xx SoCs.
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@ -13,8 +13,8 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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---
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drivers/spi/Kconfig | 7 ++
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drivers/spi/Makefile | 1 +
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drivers/spi/spi-ar934x.c | 229 +++++++++++++++++++++++++++++++++++++++
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3 files changed, 237 insertions(+)
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drivers/spi/spi-ar934x.c | 235 +++++++++++++++++++++++++++++++++++++++
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3 files changed, 243 insertions(+)
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create mode 100644 drivers/spi/spi-ar934x.c
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--- a/drivers/spi/Kconfig
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@ -45,7 +45,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
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--- /dev/null
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+++ b/drivers/spi/spi-ar934x.c
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@@ -0,0 +1,229 @@
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@@ -0,0 +1,235 @@
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+// SPDX-License-Identifier: GPL-2.0
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+//
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+// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
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@ -70,6 +70,9 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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+#define AR934X_SPI_REG_FS 0x00
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+#define AR934X_SPI_ENABLE BIT(0)
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+
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+#define AR934X_SPI_REG_IOC 0x08
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+#define AR934X_SPI_IOC_INITVAL 0x70000
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+
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+#define AR934X_SPI_REG_CTRL 0x04
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+#define AR934X_SPI_CLK_MASK GENMASK(5, 0)
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+
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@ -227,7 +230,10 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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+ return -ENOMEM;
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+ }
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+
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+ /* disable flash mapping and expose spi controller registers */
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+ iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
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+ /* restore pins to default state: CSn=1 DO=CLK=0 */
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+ iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
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+
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+ ctlr->mode_bits = SPI_LSB_FIRST;
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+ ctlr->setup = ar934x_spi_setup;
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