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mt7981: add clt-r30b1 support (#107)

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参考原厂固件修改
This commit is contained in:
benboguan 2023-08-26 00:30:07 +08:00 committed by GitHub
parent bf8be02de8
commit 912deb4379
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GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 441 additions and 1 deletions
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4
defconfig/mt7981-ax3000.config
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@ -3,6 +3,10 @@ CONFIG_TARGET_mediatek_mt7981=y
CONFIG_TARGET_MULTI_PROFILE=y
CONFIG_TARGET_DEVICE_mediatek_mt7981_DEVICE_cetron_ct3003=y
CONFIG_TARGET_DEVICE_PACKAGES_mediatek_mt7981_DEVICE_cetron_ct3003=""
CONFIG_TARGET_DEVICE_mediatek_mt7981_DEVICE_mt7981-clt-r30b1=y
CONFIG_TARGET_DEVICE_PACKAGES_mediatek_mt7981_DEVICE_mt7981-clt-r30b1=""
CONFIG_TARGET_DEVICE_mediatek_mt7981_DEVICE_mt7981-clt-r30b1-112M=y
CONFIG_TARGET_DEVICE_PACKAGES_mediatek_mt7981_DEVICE_mt7981-clt-r30b1-112M=""
CONFIG_TARGET_DEVICE_mediatek_mt7981_DEVICE_cmcc_rax3000m=y
CONFIG_TARGET_DEVICE_PACKAGES_mediatek_mt7981_DEVICE_cmcc_rax3000m=""
CONFIG_TARGET_DEVICE_mediatek_mt7981_DEVICE_h3c_nx30pro=y

1
package/boot/uboot-envtools/files/mediatek
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@ -18,6 +18,7 @@ livinet,zr-3020*)
ubootenv_add_uci_config "/dev/mtd2" "0x0" "0x20000" "0x20000" "1"
;;
h3c,nx30pro |\
*clt,r30b1* |\
cmcc,rax3000m)
ubootenv_add_uci_config "/dev/mtd2" "0x0" "0x80000" "0x20000" "4"
;;

45
target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clt-r30b1-112M.dts Normal file
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@ -0,0 +1,45 @@
/dts-v1/;
#include "mt7981-clt-r30b1-base.dtsi"
/ {
nmbm_spim_nand {
compatible = "generic,nmbm";
#address-cells = <1>;
#size-cells = <1>;
lower-mtd-device = <&spi_nand>;
forced-create;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x100000>;
};
partition@100000 {
label = "u-boot-env";
reg = <0x100000 0x80000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x200000>;
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x200000>;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x7000000>;
};
};
};
};

297
target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clt-r30b1-base.dtsi Normal file
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@ -0,0 +1,297 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "mt7981.dtsi"
/ {
model = "CLT R30B1";
compatible = "clt,r30b1", "mediatek,mt7981";
aliases {
led-boot = &red_led;
led-failsafe = &red_led;
led-running = &green_led;
led-upgrade = &blue_led;
};
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
earlycon=uart8250,mmio32,0x11002000";
};
memory {
reg = <0 0x40000000 0 0x10000000>;
};
leds {
compatible = "gpio-leds";
red_led: red {
label = "r30b1:red";
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
green_led: green {
label = "r30b1:green";
gpios = <&pio 12 GPIO_ACTIVE_LOW>;
};
blue_led: blue {
label = "r30b1:blue";
gpios = <&pio 11 GPIO_ACTIVE_LOW>;
};
};
gpio-keys {
compatible = "gpio-keys";
reset-button {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
mesh-button {
label = "mesh";
linux,code = <BTN_9>;
linux,input-type = <EV_SW>;
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
};
};
sound_wm8960 {
compatible = "mediatek,mt79xx-wm8960-machine";
mediatek,platform = <&afe>;
audio-routing = "Headphone", "HP_L",
"Headphone", "HP_R",
"LINPUT1", "AMIC",
"RINPUT1", "AMIC";
mediatek,audio-codec = <&wm8960>;
status = "disabled";
};
sound_si3218x {
compatible = "mediatek,mt79xx-si3218x-machine";
mediatek,platform = <&afe>;
mediatek,ext-codec = <&proslic_spi>;
status = "disabled";
};
gsw: gsw@0 {
compatible = "mediatek,mt753x";
mediatek,ethsys = <&ethsys>;
#address-cells = <1>;
#size-cells = <0>;
};
};
&afe {
pinctrl-names = "default";
pinctrl-0 = <&pcm_pins>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins>;
status = "disabled";
wm8960: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
};
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "gmii";
phy-handle = <&phy0>;
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9461";
reg = <0>;
phy-mode = "gmii";
nvmem-cells = <&phy_calibration>;
nvmem-cell-names = "phy-cal-data";
};
};
};
&gsw {
mediatek,mdio = <&mdio>;
mediatek,mdio_master_pinmux = <0>;
reset-gpios = <&pio 39 0>;
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
port6: port@6 {
compatible = "mediatek,mt753x-port";
mediatek,ssc-on;
reg = <6>;
phy-mode = "sgmii";
fixed-link {
speed = <2500>;
full-duplex;
};
};
};
&hnat {
mtketh-wan = "eth1";
mtketh-lan = "eth0";
mtketh-max-gmac = <2>;
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "okay";
spi_nand: spi_nand@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
spi-cal-enable;
spi-cal-mode = "read-data";
spi-cal-datalen = <7>;
spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; /* 'SPINAND' */
spi-cal-addrlen = <5>;
spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins>;
status = "okay";
proslic_spi: proslic_spi@0 {
compatible = "silabs,proslic_spi";
reg = <0>;
spi-max-frequency = <10000000>;
spi-cpha = <1>;
spi-cpol = <1>;
channel_count = <1>;
debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
reset_gpio = <&pio 15 0>;
ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
};
};
&pio {
i2c_pins: i2c-pins-g0 {
mux {
function = "i2c";
groups = "i2c0_0";
};
};
pcm_pins: pcm-pins-g0 {
mux {
function = "pcm";
groups = "pcm";
};
};
pwm0_pin: pwm0-pin-g0 {
mux {
function = "pwm";
groups = "pwm0_0";
};
};
pwm1_pin: pwm1-pin-g0 {
mux {
function = "pwm";
groups = "pwm1_0";
};
};
pwm2_pin: pwm2-pin {
mux {
function = "pwm";
groups = "pwm2";
};
};
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
spic_pins: spi1-pins {
mux {
function = "spi";
groups = "spi1_1";
};
};
uart1_pins: uart1-pins-g1 {
mux {
function = "uart";
groups = "uart1_1";
};
};
uart2_pins: uart2-pins-g1 {
mux {
function = "uart";
groups = "uart2_1";
};
};
};

50
target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7981-clt-r30b1.dts Normal file
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@ -0,0 +1,50 @@
/dts-v1/;
#include "mt7981-clt-r30b1-base.dtsi"
/ {
nmbm_spim_nand {
compatible = "generic,nmbm";
#address-cells = <1>;
#size-cells = <1>;
lower-mtd-device = <&spi_nand>;
forced-create;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x100000>;
};
partition@100000 {
label = "u-boot-env";
reg = <0x100000 0x80000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x200000>;
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x200000>;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x4000000>;
};
partition@4580000 {
label = "data";
reg = <0x4580000 0x2000000>;
};
};
};
};

34
target/linux/mediatek/image/mt7981.mk
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@ -223,6 +223,40 @@ define Device/cetron_ct3003
endef
TARGET_DEVICES += cetron_ct3003
define Device/mt7981-clt-r30b1
DEVICE_VENDOR := MediaTek
DEVICE_MODEL := CLT R30B1
DEVICE_DTS := mt7981-clt-r30b1
DEVICE_DTS_DIR := $(DTS_DIR)/mediatek
SUPPORTED_DEVICES := clt,30rb1
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 65536k
KERNEL_IN_UBI := 1
IMAGES += factory.bin
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
TARGET_DEVICES += mt7981-clt-r30b1
define Device/mt7981-clt-r30b1-112M
DEVICE_VENDOR := MediaTek
DEVICE_MODEL := CLT R30B1 (with 112M ubi)
DEVICE_DTS := mt7981-clt-r30b1-112M
DEVICE_DTS_DIR := $(DTS_DIR)/mediatek
SUPPORTED_DEVICES := clt,r30b1
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 114688k
KERNEL_IN_UBI := 1
IMAGES += factory.bin
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
TARGET_DEVICES += mt7981-clt-r30b1-112M
define Device/xiaomi_mi-router-wr30u-stock
DEVICE_VENDOR := Xiaomi
DEVICE_MODEL := Mi Router WR30U (stock layout)

5
target/linux/mediatek/mt7981/base-files/etc/board.d/01_leds
View File

@ -11,6 +11,11 @@ board=$(board_name)
board_config_update
case "$board" in
clt,r30b1)
ucidef_set_led_default "green" "GREEN" "r30b1:green" "1"
ucidef_set_led_default "red" "RED" "r30b1:red" "0"
ucidef_set_led_netdev "blue" "BLUE" "r30b1:blue" "eth1"
;;
imou,lc-hx3001)
ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" "link"
ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" "link"

4
target/linux/mediatek/mt7981/base-files/etc/board.d/02_network
View File

@ -37,9 +37,10 @@ mediatek_setup_interfaces()
ucidef_add_switch "switch0" \
"0:lan" "1:lan" "2:lan" "3:wan" "6t@eth0"
;;
*clt,r30b1* |\
*imou,lc-hx3001*)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
ucidef_add_switch "switch0" \
ucidef_add_switch "switch0" \
"0:lan" "1:lan" "2:lan" "6u@eth0"
;;
*jcg,q30*)
@ -185,6 +186,7 @@ mediatek_setup_macs()
mtk_facrory_write_mac "Factory" 4 $wifi_mac
fi
;;
*clt,r30b1* |\
*konka,komi-a31*)
lan_mac=$(mtd_get_mac_binary $part_name 0x2A)
wan_mac=$(mtd_get_mac_binary $part_name 0x24)

2
target/linux/mediatek/mt7981/base-files/lib/upgrade/platform.sh
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@ -194,6 +194,7 @@ platform_do_upgrade() {
*zr-3020* |\
*360,t7* |\
*cetron,ct3003* |\
*clt,r30b1* |\
*imou,lc-hx3001* |\
*jcg,q30* |\
cmcc,rax3000m |\
@ -232,6 +233,7 @@ platform_check_image() {
xiaomi,mi-router-wr30u-stock|\
xiaomi,mi-router-wr30u-112m|\
*cetron,ct3003* |\
*clt,r30b1* |\
*imou,lc-hx3001* |\
*jcg,q30* |\
cmcc,rax3000m |\