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CN_SZTL 2020-10-10 23:30:13 +08:00
commit 7f2a48dcfa
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GPG Key ID: 6850B6345C862176
35 changed files with 2472 additions and 2577 deletions
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4
include/kernel-version.mk
View File

@ -7,10 +7,10 @@ ifdef CONFIG_TESTING_KERNEL
endif
LINUX_VERSION-4.19 = .138
LINUX_VERSION-5.4 = .69
LINUX_VERSION-5.4 = .70
LINUX_KERNEL_HASH-4.19.138 = d15c27d05f6c527269b75b30cc72972748e55720e7e00ad8abbaa4fe3b1d5e02
LINUX_KERNEL_HASH-5.4.69 = a8b31d716b397303a183e42ad525ff2871024a43e3ea530d0fdf73b7f9d27da7
LINUX_KERNEL_HASH-5.4.70 = c0b3d8085c5ba235df38b00b740e053659709e8a5ca21957a239f6bc22c45007
remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))

1
package/utils/secilc/Makefile
View File

@ -33,6 +33,7 @@ define Package/secilc
CATEGORY:=Utilities
TITLE:=SELinux Common Intermediate Language (CIL) Compiler
URL:=http://selinuxproject.org/page/Main_Page
DEPENDS:=+libsepol
endef
define Package/secilc/description

2
target/linux/armvirt/config-4.19
View File

@ -58,8 +58,6 @@ CONFIG_EXT4_FS=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FAILOVER=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y

1
target/linux/armvirt/config-5.4
View File

@ -71,7 +71,6 @@ CONFIG_EXT4_FS=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_STAT_FS=y
CONFIG_FAILOVER=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y

4
target/linux/ath79/dts/ar7161_aruba_ap-105.dts
View File

@ -85,10 +85,6 @@
sda-gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
scl-gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
/* can be removed on 4.19 */
gpios = <&gpio 5 GPIO_ACTIVE_LOW>,
<&gpio 4 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;

4
target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts
View File

@ -30,10 +30,6 @@
sda-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
scl-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
/* can be removed on 4.19 */
gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
<&gpio 15 GPIO_ACTIVE_LOW>;
pcf8563: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;

2
target/linux/generic/config-4.19
View File

@ -1407,7 +1407,9 @@ CONFIG_EXTRA_TARGETS=""
# CONFIG_F2FS_FS is not set
# CONFIG_F2FS_FS_ENCRYPTION is not set
# CONFIG_F2FS_FS_POSIX_ACL is not set
CONFIG_F2FS_FS_XATTR=y
# CONFIG_F2FS_IO_TRACE is not set
CONFIG_F2FS_STAT_FS=y
# CONFIG_FAILOVER is not set
# CONFIG_FAIR_GROUP_SCHED is not set
# CONFIG_FANOTIFY is not set

2
target/linux/generic/config-5.4
View File

@ -1524,7 +1524,9 @@ CONFIG_EXTRA_TARGETS=""
# CONFIG_F2FS_FS_ENCRYPTION is not set
# CONFIG_F2FS_FS_POSIX_ACL is not set
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_FS_XATTR=y
# CONFIG_F2FS_IO_TRACE is not set
CONFIG_F2FS_STAT_FS=y
# CONFIG_FAILOVER is not set
# CONFIG_FAIR_GROUP_SCHED is not set
# CONFIG_FANOTIFY is not set

2
target/linux/imx6/config-4.19
View File

@ -191,8 +191,6 @@ CONFIG_EXTRA_FIRMWARE_DIR="firmware"
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FEC=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y

1
target/linux/imx6/config-5.4
View File

@ -195,7 +195,6 @@ CONFIG_EXTCON=y
CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin"
CONFIG_EXTRA_FIRMWARE_DIR="firmware"
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FEC=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y

2118
target/linux/ipq40xx/files-5.4/drivers/net/phy/ar40xx.c Normal file
View File

File diff suppressed because it is too large Load Diff

342
target/linux/ipq40xx/files-5.4/drivers/net/phy/ar40xx.h Normal file
View File

@ -0,0 +1,342 @@
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR40XX_H
#define __AR40XX_H
#define AR40XX_MAX_VLANS 128
#define AR40XX_NUM_PORTS 6
#define AR40XX_NUM_PHYS 5
#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
struct ar40xx_priv {
struct switch_dev dev;
u8 __iomem *hw_addr;
u8 __iomem *psgmii_hw_addr;
u32 mac_mode;
struct reset_control *ess_rst;
u32 cpu_bmp;
u32 lan_bmp;
u32 wan_bmp;
struct mii_bus *mii_bus;
struct phy_device *phy;
/* mutex for qm task */
struct mutex qm_lock;
struct delayed_work qm_dwork;
u32 port_link_up[AR40XX_NUM_PORTS];
u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
u32 phy_t_status;
/* mutex for switch reg access */
struct mutex reg_mutex;
/* mutex for mib task */
struct mutex mib_lock;
struct delayed_work mib_work;
int mib_next_port;
u64 *mib_stats;
char buf[2048];
/* all fields below will be cleared on reset */
bool vlan;
u16 vlan_id[AR40XX_MAX_VLANS];
u8 vlan_table[AR40XX_MAX_VLANS];
u8 vlan_tagged;
u16 pvid[AR40XX_NUM_PORTS];
/* mirror */
bool mirror_rx;
bool mirror_tx;
int source_port;
int monitor_port;
};
#define AR40XX_PORT_LINK_UP 1
#define AR40XX_PORT_LINK_DOWN 0
#define AR40XX_QM_NOT_EMPTY 1
#define AR40XX_QM_EMPTY 0
#define AR40XX_LAN_VLAN 1
#define AR40XX_WAN_VLAN 2
enum ar40xx_port_wrapper_cfg {
PORT_WRAPPER_PSGMII = 0,
};
struct ar40xx_mib_desc {
u32 size;
u32 offset;
const char *name;
};
#define AR40XX_PORT_CPU 0
#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
#define AR40XX_MII_ATH_MMD_ADDR 0x0d
#define AR40XX_MII_ATH_MMD_DATA 0x0e
#define AR40XX_MII_ATH_DBG_ADDR 0x1d
#define AR40XX_MII_ATH_DBG_DATA 0x1e
#define AR40XX_STATS_RXBROAD 0x00
#define AR40XX_STATS_RXPAUSE 0x04
#define AR40XX_STATS_RXMULTI 0x08
#define AR40XX_STATS_RXFCSERR 0x0c
#define AR40XX_STATS_RXALIGNERR 0x10
#define AR40XX_STATS_RXRUNT 0x14
#define AR40XX_STATS_RXFRAGMENT 0x18
#define AR40XX_STATS_RX64BYTE 0x1c
#define AR40XX_STATS_RX128BYTE 0x20
#define AR40XX_STATS_RX256BYTE 0x24
#define AR40XX_STATS_RX512BYTE 0x28
#define AR40XX_STATS_RX1024BYTE 0x2c
#define AR40XX_STATS_RX1518BYTE 0x30
#define AR40XX_STATS_RXMAXBYTE 0x34
#define AR40XX_STATS_RXTOOLONG 0x38
#define AR40XX_STATS_RXGOODBYTE 0x3c
#define AR40XX_STATS_RXBADBYTE 0x44
#define AR40XX_STATS_RXOVERFLOW 0x4c
#define AR40XX_STATS_FILTERED 0x50
#define AR40XX_STATS_TXBROAD 0x54
#define AR40XX_STATS_TXPAUSE 0x58
#define AR40XX_STATS_TXMULTI 0x5c
#define AR40XX_STATS_TXUNDERRUN 0x60
#define AR40XX_STATS_TX64BYTE 0x64
#define AR40XX_STATS_TX128BYTE 0x68
#define AR40XX_STATS_TX256BYTE 0x6c
#define AR40XX_STATS_TX512BYTE 0x70
#define AR40XX_STATS_TX1024BYTE 0x74
#define AR40XX_STATS_TX1518BYTE 0x78
#define AR40XX_STATS_TXMAXBYTE 0x7c
#define AR40XX_STATS_TXOVERSIZE 0x80
#define AR40XX_STATS_TXBYTE 0x84
#define AR40XX_STATS_TXCOLLISION 0x8c
#define AR40XX_STATS_TXABORTCOL 0x90
#define AR40XX_STATS_TXMULTICOL 0x94
#define AR40XX_STATS_TXSINGLECOL 0x98
#define AR40XX_STATS_TXEXCDEFER 0x9c
#define AR40XX_STATS_TXDEFER 0xa0
#define AR40XX_STATS_TXLATECOL 0xa4
#define AR40XX_REG_MODULE_EN 0x030
#define AR40XX_MODULE_EN_MIB BIT(0)
#define AR40XX_REG_MIB_FUNC 0x034
#define AR40XX_MIB_BUSY BIT(17)
#define AR40XX_MIB_CPU_KEEP BIT(20)
#define AR40XX_MIB_FUNC BITS(24, 3)
#define AR40XX_MIB_FUNC_S 24
#define AR40XX_MIB_FUNC_NO_OP 0x0
#define AR40XX_MIB_FUNC_FLUSH 0x1
#define AR40XX_ESS_SERVICE_TAG 0x48
#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
#define AR40XX_PORT_SPEED BITS(0, 2)
#define AR40XX_PORT_STATUS_SPEED_S 0
#define AR40XX_PORT_TX_EN BIT(2)
#define AR40XX_PORT_RX_EN BIT(3)
#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
#define AR40XX_PORT_DUPLEX BIT(6)
#define AR40XX_PORT_TXHALF_FLOW BIT(7)
#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
#define AR40XX_REG_MAX_FRAME_SIZE 0x078
#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
#define AR40XX_REG_EEE_CTRL 0x100
#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9)
#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7)
#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
#define AR40XX_REG_VTU_FUNC0 0x0610
#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
#define AR40XX_VTU_FUNC0_IVL BIT(19)
#define AR40XX_VTU_FUNC0_VALID BIT(20)
#define AR40XX_REG_VTU_FUNC1 0x0614
#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
#define AR40XX_VTU_FUNC1_OP_NOOP 0
#define AR40XX_VTU_FUNC1_OP_FLUSH 1
#define AR40XX_VTU_FUNC1_OP_LOAD 2
#define AR40XX_VTU_FUNC1_OP_PURGE 3
#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
#define AR40XX_VTU_FUNC1_FULL BIT(4)
#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
#define AR40XX_VTU_FUNC1_PORT_S 8
#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
#define AR40XX_VTU_FUNC1_VID_S 16
#define AR40XX_VTU_FUNC1_BUSY BIT(31)
#define AR40XX_REG_FWD_CTRL0 0x620
#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
#define AR40XX_REG_FWD_CTRL1 0x624
#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
#define AR40XX_FWD_CTRL1_IGMP_S 24
#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
#define AR40XX_PORT_LOOKUP_STATE_S 16
#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
#define AR40XX_REG_ATU_FUNC 0x60c
#define AR40XX_ATU_FUNC_OP BITS(0, 4)
#define AR40XX_ATU_FUNC_OP_NOOP 0x0
#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
#define AR40XX_ATU_FUNC_OP_LOAD 0x2
#define AR40XX_ATU_FUNC_OP_PURGE 0x3
#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
#define AR40XX_ATU_FUNC_BUSY BIT(31)
#define AR40XX_REG_QM_DEBUG_ADDR 0x820
#define AR40XX_REG_QM_DEBUG_VALUE 0x824
#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
#define AR40XX_PHY_DEBUG_0 0
#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
#define AR40XX_PHY_DEBUG_2 2
#define AR40XX_PHY_SPEC_STATUS 0x11
#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
/* port forwarding state */
enum {
AR40XX_PORT_STATE_DISABLED = 0,
AR40XX_PORT_STATE_BLOCK = 1,
AR40XX_PORT_STATE_LISTEN = 2,
AR40XX_PORT_STATE_LEARN = 3,
AR40XX_PORT_STATE_FORWARD = 4
};
/* ingress 802.1q mode */
enum {
AR40XX_IN_PORT_ONLY = 0,
AR40XX_IN_PORT_FALLBACK = 1,
AR40XX_IN_VLAN_ONLY = 2,
AR40XX_IN_SECURE = 3
};
/* egress 802.1q mode */
enum {
AR40XX_OUT_KEEP = 0,
AR40XX_OUT_STRIP_VLAN = 1,
AR40XX_OUT_ADD_VLAN = 2
};
/* port speed */
enum {
AR40XX_PORT_SPEED_10M = 0,
AR40XX_PORT_SPEED_100M = 1,
AR40XX_PORT_SPEED_1000M = 2,
AR40XX_PORT_SPEED_ERR = 3,
};
#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
#define AR40XX_QM_WORK_DELAY 100
#define AR40XX_MIB_FUNC_CAPTURE 0x3
#define AR40XX_REG_PORT_STATS_START 0x1000
#define AR40XX_REG_PORT_STATS_LEN 0x100
#define AR40XX_PORTS_ALL 0x3f
#define AR40XX_PSGMII_ID 5
#define AR40XX_PSGMII_CALB_NUM 100
#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
#define AR40XX_MALIBU_PHY_LAST_ADDR 4
static inline struct ar40xx_priv *
swdev_to_ar40xx(struct switch_dev *swdev)
{
return container_of(swdev, struct ar40xx_priv, dev);
}
#endif

2499
target/linux/ipq40xx/patches-5.4/705-net-add-qualcomm-ar40xx-phy.patch
View File

File diff suppressed because it is too large Load Diff

2
target/linux/malta/config-4.19
View File

@ -96,8 +96,6 @@ CONFIG_EXT4_FS=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FS_POSIX_ACL=y

1
target/linux/malta/config-5.4
View File

@ -97,7 +97,6 @@ CONFIG_EFI_EARLYCON=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_EXT4_FS=y
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FONT_8x16=y
CONFIG_FONT_AUTOSELECT=y
CONFIG_FONT_SUPPORT=y

2
target/linux/mvebu/config-4.19
View File

@ -179,8 +179,6 @@ CONFIG_EXTCON=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FS_IOMAP=y

1
target/linux/mvebu/config-5.4
View File

@ -180,7 +180,6 @@ CONFIG_EDAC_SUPPORT=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FS_IOMAP=y

2
target/linux/octeon/config-4.19
View File

@ -76,8 +76,6 @@ CONFIG_EXT4_FS=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FAT_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FRAME_WARN=2048

1
target/linux/octeon/config-5.4
View File

@ -74,7 +74,6 @@ CONFIG_EFI_EARLYCON=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_EXT4_FS=y
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FAT_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FONT_8x16=y

1
target/linux/octeontx/config-5.4
View File

@ -234,7 +234,6 @@ CONFIG_EFI_EARLYCON=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FANOTIFY=y
CONFIG_FAT_FS=y
CONFIG_FIXED_PHY=y

2
target/linux/omap/config-4.19
View File

@ -241,8 +241,6 @@ CONFIG_EXTCON_USB_GPIO=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FANOTIFY=y
CONFIG_FAT_FS=y
CONFIG_FB_CMDLINE=y

1
target/linux/omap/config-5.4
View File

@ -243,7 +243,6 @@ CONFIG_EXTCON=y
CONFIG_EXTCON_PALMAS=y
CONFIG_EXTCON_USB_GPIO=y
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FANOTIFY=y
CONFIG_FAT_FS=y
CONFIG_FB_CMDLINE=y

4
target/linux/oxnas/files/drivers/ata/sata_oxnas.c
View File

@ -1802,7 +1802,7 @@ static inline void sata_oxnas_reset_ucode(struct ata_host *ah, int force,
* Prepare as much as possible for a command without involving anything that is
* shared between ports.
*/
static void sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
static enum ata_completion_errors sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
{
struct sata_oxnas_port_priv *pd;
int port_no = qc->ap->port_no;
@ -1848,6 +1848,8 @@ static void sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
/* tell it to wait */
iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
}
return AC_ERR_OK;
}
static int sata_oxnas_port_start(struct ata_port *ap)

11
target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c
View File

@ -88,13 +88,8 @@ int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node, int
return -ENODEV;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)
phydev->supported &= PHY_GBIT_FEATURES;
phydev->advertising = phydev->supported;
#else
phy_set_max_speed(phydev, SPEED_1000);
linkmode_copy(phydev->advertising, phydev->supported);
#endif
phydev->no_auto_carrier_off = 1;
dev_info(priv->dev,
@ -116,17 +111,11 @@ static void phy_init(struct fe_priv *priv, struct phy_device *phy)
phy->speed = 0;
phy->duplex = 0;
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)
phy->supported &= IS_ENABLED(CONFIG_NET_RALINK_MDIO_MT7620) ?
PHY_GBIT_FEATURES : PHY_BASIC_FEATURES;
phy->advertising = phy->supported | ADVERTISED_Autoneg;
#else
phy_set_max_speed(phy, IS_ENABLED(CONFIG_NET_RALINK_MDIO_MT7620) ?
SPEED_1000 :
SPEED_100);
linkmode_copy(phy->advertising, phy->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phy->advertising);
#endif
phy_start_aneg(phy);
}

20
target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
View File

@ -715,19 +715,11 @@ next_frag:
/* TX SG offload */
nr_frags = skb_shinfo(skb)->nr_frags;
for (i = 0; i < nr_frags; i++) {
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)
struct skb_frag_struct *frag;
#else
skb_frag_t *frag;
#endif
frag = &skb_shinfo(skb)->frags[i];
if (fe_tx_dma_map_page(ring, &st, skb_frag_page(frag),
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)
frag->page_offset, skb_frag_size(frag)))
#else
skb_frag_off(frag), skb_frag_size(frag)))
#endif
goto err_dma;
}
@ -762,11 +754,7 @@ next_frag:
netif_wake_queue(dev);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)
if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !head->xmit_more)
#else
if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !netdev_xmit_more())
#endif
fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
return 0;
@ -825,22 +813,14 @@ static inline int fe_cal_txd_req(struct sk_buff *skb)
{
struct sk_buff *head = skb;
int i, nfrags = 0;
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)
struct skb_frag_struct *frag;
#else
skb_frag_t *frag;
#endif
next_frag:
nfrags++;
if (skb_is_gso(skb)) {
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
frag = &skb_shinfo(skb)->frags[i];
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)
nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
#else
nfrags += DIV_ROUND_UP(skb_frag_size(frag), TX_DMA_BUF_LEN);
#endif
}
} else {
nfrags += skb_shinfo(skb)->nr_frags;

6
target/linux/ramips/modules.mk
View File

@ -84,8 +84,7 @@ define KernelPackage/dma-ralink
CONFIG_DMA_RALINK
FILES:= \
$(LINUX_DIR)/drivers/dma/virt-dma.ko \
$(LINUX_DIR)/drivers/dma/ralink-gdma.ko@lt5.4 \
$(LINUX_DIR)/drivers/staging/ralink-gdma/ralink-gdma.ko@ge5.4
$(LINUX_DIR)/drivers/staging/ralink-gdma/ralink-gdma.ko
AUTOLOAD:=$(call AutoLoad,52,ralink-gdma)
endef
@ -105,8 +104,7 @@ define KernelPackage/hsdma-mtk
CONFIG_MTK_HSDMA
FILES:= \
$(LINUX_DIR)/drivers/dma/virt-dma.ko \
$(LINUX_DIR)/drivers/dma/mtk-hsdma.ko@lt5.4 \
$(LINUX_DIR)/drivers/staging/mt7621-dma/mtk-hsdma.ko@ge5.4
$(LINUX_DIR)/drivers/staging/mt7621-dma/mtk-hsdma.ko
AUTOLOAD:=$(call AutoLoad,53,mtk-hsdma)
endef

1
target/linux/rockchip/config-default
View File

@ -122,7 +122,6 @@ CONFIG_DTC=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EFI_EARLYCON=y
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FONT_8x16=y
CONFIG_FONT_AUTOSELECT=y

2
target/linux/sunxi/config-4.19
View File

@ -173,8 +173,6 @@ CONFIG_EXTCON=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FAT_FS=y
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y

1
target/linux/sunxi/config-5.4
View File

@ -172,7 +172,6 @@ CONFIG_ENABLE_MUST_CHECK=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FAT_FS=y
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y

2
target/linux/tegra/config-4.19
View File

@ -198,8 +198,6 @@ CONFIG_EXTCON=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y

1
target/linux/tegra/config-5.4
View File

@ -213,7 +213,6 @@ CONFIG_EXTCON=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_STAT_FS=y
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y

2
target/linux/x86/config-4.19
View File

@ -131,8 +131,6 @@ CONFIG_EXT4_FS=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_STAT_FS=y
# CONFIG_F71808E_WDT is not set
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_FIX_EARLYCON_MEM=y

1
target/linux/x86/config-5.4
View File

@ -148,7 +148,6 @@ CONFIG_EXT4_FS=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_STAT_FS=y
# CONFIG_F71808E_WDT is not set
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_FIX_EARLYCON_MEM=y

2
target/linux/zynq/config-4.19
View File

@ -195,8 +195,6 @@ CONFIG_EXTCON=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_STAT_FS=y
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y

1
target/linux/zynq/config-5.4
View File

@ -206,7 +206,6 @@ CONFIG_EXTCON=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS=y
# CONFIG_F2FS_FS_SECURITY is not set
CONFIG_F2FS_STAT_FS=y
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y