mirror of
https://github.com/hanwckf/immortalwrt-mt798x.git
synced 2025-01-09 02:43:53 +08:00
uboot-rockchip: update to v2021.07
Tested on NanoPi R2S Signed-off-by: David Bauer <mail@david-bauer.net> (cherry picked from commit e68e80ead9a0f700701ca494282756454719d7de)
This commit is contained in:
David Bauer
Tianling Shen
parent
bd3354c27b
commit
775f71487a
@ -5,10 +5,10 @@
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_VERSION:=2021.01
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PKG_VERSION:=2021.07
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PKG_RELEASE:=1
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PKG_HASH:=b407e1510a74e863b8b5cb42a24625344f0e0c2fc7582d8c866bd899367d0454
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PKG_HASH:=312b7eeae44581d1362c3a3f02c28d806647756c82ba8c72241c7cdbe68ba77e
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PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
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@ -114,8 +114,9 @@ ifneq ($(OF_PLATDATA),)
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mkdir -p $(PKG_BUILD_DIR)/tpl/dts
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mkdir -p $(PKG_BUILD_DIR)/include/generated
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$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-platdata.c $(PKG_BUILD_DIR)/tpl/dts/dt-platdata.c
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$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-plat.c $(PKG_BUILD_DIR)/tpl/dts/dt-plat.c
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$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h
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$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-decl.h $(PKG_BUILD_DIR)/include/generated/dt-decl.h
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endif
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$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
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@ -17,16 +17,12 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
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--- a/scripts/Makefile.spl
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+++ b/scripts/Makefile.spl
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@@ -321,12 +321,6 @@ PHONY += dts_dir
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dts_dir:
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$(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts)
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@@ -354,8 +354,6 @@ $(platdata-hdr) $(u-boot-spl-platdata_c)
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@# of OF_PLATDATA_INST and this might change between builds. Leaving old
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@# ones around is confusing and it is possible that switching the
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@# setting again will use the old one instead of regenerating it.
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- @rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata)
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- $(call if_changed,dtoc)
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-include/generated/dt-structs-gen.h: $(obj)/$(SPL_BIN).dtb dts_dir FORCE
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- $(call if_changed,dtoch)
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-
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-$(obj)/dts/dt-platdata.c: $(obj)/$(SPL_BIN).dtb dts_dir FORCE
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- $(call if_changed,dtocc)
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-
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ifdef CONFIG_SAMSUNG
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ifdef CONFIG_VAR_SIZE_SPL
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VAR_SIZE_PARAM = --vs
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@ -1,571 +0,0 @@
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From 4189a8db90ca7edc16cf9509576ca2e74f028c1c Mon Sep 17 00:00:00 2001
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From: David Bauer <mail@david-bauer.net>
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Date: Thu, 7 Jan 2021 00:05:46 +0100
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Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S
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This adds support for the NanoPi R2S from FriendlyArm.
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Rockchip RK3328 SoC
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1GB DDR4 RAM
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Gigabit Ethernet (WAN)
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Gigabit Ethernet (USB3) (LAN)
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USB 2.0 Host Port
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MicroSD slot
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Reset button
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WAN - LAN - SYS LED
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Signed-off-by: David Bauer <mail@david-bauer.net>
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---
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arch/arm/dts/Makefile | 1 +
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arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 40 +++
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arch/arm/dts/rk3328-nanopi-r2s.dts | 370 +++++++++++++++++++++
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board/rockchip/evb_rk3328/MAINTAINERS | 7 +
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configs/nanopi-r2s-rk3328_defconfig | 98 ++++++
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5 files changed, 516 insertions(+)
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create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
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create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts
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create mode 100644 configs/nanopi-r2s-rk3328_defconfig
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
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dtb-$(CONFIG_ROCKCHIP_RK3328) += \
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rk3328-evb.dtb \
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+ rk3328-nanopi-r2s.dtb \
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rk3328-roc-cc.dtb \
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rk3328-rock64.dtb \
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rk3328-rock-pi-e.dtb
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
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@@ -0,0 +1,40 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
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+ * (C) Copyright 2020 David Bauer
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+ */
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+
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+#include "rk3328-u-boot.dtsi"
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+#include "rk3328-sdram-ddr4-666.dtsi"
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+/ {
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+ chosen {
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+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
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+ };
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+};
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+
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+&gpio0 {
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+ u-boot,dm-spl;
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+};
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+
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+&pinctrl {
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+ u-boot,dm-spl;
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+};
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+
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+&sdmmc0m1_gpio {
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+ u-boot,dm-spl;
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+};
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+
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+&pcfg_pull_up_4ma {
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+ u-boot,dm-spl;
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+};
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+
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+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
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+&vcc_sd {
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+ u-boot,dm-spl;
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+};
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+
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+&gmac2io {
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+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ snps,reset-active-low;
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+ snps,reset-delays-us = <0 10000 50000>;
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+};
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-nanopi-r2s.dts
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@@ -0,0 +1,370 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
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+ */
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/gpio/gpio.h>
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+#include "rk3328.dtsi"
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+
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+/ {
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+ model = "FriendlyElec NanoPi R2S";
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+ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
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+
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+ chosen {
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+ stdout-path = "serial2:1500000n8";
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+ };
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+
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+ gmac_clk: gmac-clock {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "gmac_clkin";
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+ #clock-cells = <0>;
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+ };
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+
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+ keys {
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+ compatible = "gpio-keys";
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+ pinctrl-0 = <&reset_button_pin>;
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+ pinctrl-names = "default";
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+
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+ reset {
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+ label = "reset";
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+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
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+ linux,code = <KEY_RESTART>;
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+ debounce-interval = <50>;
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+ };
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
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+ pinctrl-names = "default";
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+
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+ lan_led: led-0 {
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+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
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+ label = "nanopi-r2s:green:lan";
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+ };
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+
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+ sys_led: led-1 {
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+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
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+ label = "nanopi-r2s:red:sys";
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+ };
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+
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+ wan_led: led-2 {
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+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
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+ label = "nanopi-r2s:green:wan";
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+ };
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+ };
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+
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+ vcc_io_sdio: sdmmcio-regulator {
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+ compatible = "regulator-gpio";
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+ enable-active-high;
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+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
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+ pinctrl-0 = <&sdio_vcc_pin>;
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+ pinctrl-names = "default";
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+ regulator-name = "vcc_io_sdio";
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+ regulator-always-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-settling-time-us = <5000>;
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+ regulator-type = "voltage";
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+ startup-delay-us = <2000>;
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+ states = <1800000 0x1
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+ 3300000 0x0>;
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+ vin-supply = <&vcc_io_33>;
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+ };
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+
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+ vcc_sd: sdmmc-regulator {
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+ compatible = "regulator-fixed";
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+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
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+ pinctrl-0 = <&sdmmc0m1_gpio>;
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+ pinctrl-names = "default";
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+ regulator-name = "vcc_sd";
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <&vcc_io_33>;
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+ };
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+
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+ vdd_5v: vdd-5v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vdd_5v";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+};
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+
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+&cpu0 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu1 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu2 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu3 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&gmac2io {
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+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
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+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
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+ clock_in_out = "input";
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+ phy-handle = <&rtl8211e>;
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+ phy-mode = "rgmii";
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+ phy-supply = <&vcc_io_33>;
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+ pinctrl-0 = <&rgmiim1_pins>;
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+ pinctrl-names = "default";
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+ rx_delay = <0x18>;
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+ snps,aal;
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+ tx_delay = <0x24>;
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+ status = "okay";
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+
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+ mdio {
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+ compatible = "snps,dwmac-mdio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ rtl8211e: ethernet-phy@1 {
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+ compatible = "ethernet-phy-id001c.c915",
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+ "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ pinctrl-0 = <ð_phy_reset_pin>;
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+ pinctrl-names = "default";
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+ reset-assert-us = <10000>;
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+ reset-deassert-us = <50000>;
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+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+};
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+
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+&i2c1 {
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+ status = "okay";
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+
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+ rk805: pmic@18 {
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+ compatible = "rockchip,rk805";
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+ reg = <0x18>;
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
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+ #clock-cells = <1>;
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+ clock-output-names = "xin32k", "rk805-clkout2";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ pinctrl-0 = <&pmic_int_l>;
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+ pinctrl-names = "default";
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+ rockchip,system-power-controller;
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+ wakeup-source;
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+
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+ vcc1-supply = <&vdd_5v>;
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+ vcc2-supply = <&vdd_5v>;
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+ vcc3-supply = <&vdd_5v>;
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+ vcc4-supply = <&vdd_5v>;
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+ vcc5-supply = <&vcc_io_33>;
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+ vcc6-supply = <&vdd_5v>;
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+
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+ regulators {
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+ vdd_log: DCDC_REG1 {
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+ regulator-name = "vdd_log";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <712500>;
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+ regulator-max-microvolt = <1450000>;
|
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+ regulator-ramp-delay = <12500>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
|
||||
+ };
|
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+
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+ vdd_arm: DCDC_REG2 {
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+ regulator-name = "vdd_arm";
|
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+ regulator-always-on;
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+ regulator-boot-on;
|
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+ regulator-min-microvolt = <712500>;
|
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+ regulator-max-microvolt = <1450000>;
|
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+ regulator-ramp-delay = <12500>;
|
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+
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+ regulator-state-mem {
|
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+ regulator-on-in-suspend;
|
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+ regulator-suspend-microvolt = <950000>;
|
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+ };
|
||||
+ };
|
||||
+
|
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+ vcc_ddr: DCDC_REG3 {
|
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+ regulator-name = "vcc_ddr";
|
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+ regulator-always-on;
|
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+ regulator-boot-on;
|
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+
|
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+ regulator-state-mem {
|
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+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_io_33: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_io_33";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_18: LDO_REG1 {
|
||||
+ regulator-name = "vcc_18";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc18_emmc: LDO_REG2 {
|
||||
+ regulator-name = "vcc18_emmc";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_10: LDO_REG3 {
|
||||
+ regulator-name = "vdd_10";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1000000>;
|
||||
+ regulator-max-microvolt = <1000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ pmuio-supply = <&vcc_io_33>;
|
||||
+ vccio1-supply = <&vcc_io_33>;
|
||||
+ vccio2-supply = <&vcc18_emmc>;
|
||||
+ vccio3-supply = <&vcc_io_sdio>;
|
||||
+ vccio4-supply = <&vcc_18>;
|
||||
+ vccio5-supply = <&vcc_io_33>;
|
||||
+ vccio6-supply = <&vcc_io_33>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ button {
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethernet-phy {
|
||||
+ eth_phy_reset_pin: eth-phy-reset-pin {
|
||||
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ lan_led_pin: lan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ sys_led_pin: sys-led-pin {
|
||||
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sd {
|
||||
+ sdio_vcc_pin: sdio-vcc-pin {
|
||||
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
|
||||
+ pinctrl-names = "default";
|
||||
+ sd-uhs-sdr12;
|
||||
+ sd-uhs-sdr25;
|
||||
+ sd-uhs-sdr50;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc_sd>;
|
||||
+ vqmmc-supply = <&vcc_io_sdio>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <0>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb20_otg {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- a/board/rockchip/evb_rk3328/MAINTAINERS
|
||||
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
|
||||
@@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328
|
||||
F: include/configs/evb_rk3328.h
|
||||
F: configs/evb-rk3328_defconfig
|
||||
|
||||
+NANOPI-R2S-RK3328
|
||||
+M: David Bauer <mail@david-bauer.net>
|
||||
+S: Maintained
|
||||
+F: configs/nanopi-r2s-rk3328_defconfig
|
||||
+F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
|
||||
+F: arch/arm/dts/rk3328-nanopi-r2s.dts
|
||||
+
|
||||
ROC-RK3328-CC
|
||||
M: Loic Devulder <ldevulder@suse.com>
|
||||
M: Chen-Yu Tsai <wens@csie.org>
|
||||
--- /dev/null
|
||||
+++ b/configs/nanopi-r2s-rk3328_defconfig
|
||||
@@ -0,0 +1,98 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_SPL_GPIO_SUPPORT=y
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_ROCKCHIP_RK3328=y
|
||||
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYSINFO=y
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
|
||||
+CONFIG_MISC_INIT_R=y
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_I2C_SUPPORT=y
|
||||
+CONFIG_SPL_POWER_SUPPORT=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_TPL_OF_CONTROL=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_TPL_OF_PLATDATA=y
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_TPL_DM=y
|
||||
+CONFIG_REGMAP=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_TPL_REGMAP=y
|
||||
+CONFIG_SYSCON=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_TPL_SYSCON=y
|
||||
+CONFIG_CLK=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
|
||||
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PINCTRL=y
|
||||
+CONFIG_SPL_PINCTRL=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_DM_REGULATOR=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_RAM=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_TPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYSRESET=y
|
||||
+# CONFIG_TPL_SYSRESET is not set
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC2=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+# CONFIG_USB_DWC3_GADGET is not set
|
||||
+CONFIG_USB_GADGET=y
|
||||
+CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_TPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
@ -1,257 +0,0 @@
|
||||
From 2dd6b01ec665c376e6be7d37b513fb4d05df60db Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Fri, 8 Jan 2021 05:55:50 +0000
|
||||
Subject: [PATCH] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S
|
||||
|
||||
This adds support for the NanoPi R4S from FriendlyArm.
|
||||
|
||||
Rockchip RK3399 SoC
|
||||
1GB DDR3 or 4GB LPDDR4 RAM
|
||||
Gigabit Ethernet (WAN)
|
||||
Gigabit Ethernet (PCIe) (LAN)
|
||||
USB 3.0 Host Port x 2
|
||||
MicroSD slot
|
||||
Reset button
|
||||
WAN - LAN - SYS LED
|
||||
|
||||
Co-developed-by: Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
[minor adjustments]
|
||||
Co-developed-by: Marty Jones <mj8263788@gmail.com>
|
||||
Signed-off-by: Marty Jones <mj8263788@gmail.com>
|
||||
[further adjustments, fixed format issues]
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
---
|
||||
arch/arm/dts/Makefile | 1 +
|
||||
arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 9 ++
|
||||
arch/arm/dts/rk3399-nanopi-r4s.dts | 133 +++++++++++++++++++++
|
||||
configs/nanopi-r4s-rk3399_defconfig | 63 ++++++++++
|
||||
4 files changed, 206 insertions(+)
|
||||
create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
|
||||
create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts
|
||||
create mode 100644 configs/nanopi-r4s-rk3399_defconfig
|
||||
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -134,6 +134,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
rk3399-nanopi-m4.dtb \
|
||||
rk3399-nanopi-m4-2gb.dtb \
|
||||
rk3399-nanopi-neo4.dtb \
|
||||
+ rk3399-nanopi-r4s.dtb \
|
||||
rk3399-orangepi.dtb \
|
||||
rk3399-pinebook-pro.dtb \
|
||||
rk3399-puma-haikou.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
|
||||
@@ -0,0 +1,9 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * (C) Copyright 2020 Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
+ */
|
||||
+
|
||||
+#include "rk3399-nanopi4-u-boot.dtsi"
|
||||
+#include "rk3399-sdram-lpddr4-100.dtsi"
|
||||
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
|
||||
+#include "rk3399-sdram-ddr3-1866.dtsi"
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-nanopi-r4s.dts
|
||||
@@ -0,0 +1,133 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * FriendlyElec NanoPC-T4 board device tree source
|
||||
+ *
|
||||
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2018 Collabora Ltd.
|
||||
+ *
|
||||
+ * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
+ * Copyright (c) 2020 Marty Jones <mj8263788@gmail.com>
|
||||
+ * Copyright (c) 2021 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3399-nanopi4.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R4S";
|
||||
+ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
|
||||
+
|
||||
+ /delete-node/ display-subsystem;
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
|
||||
+
|
||||
+ /delete-node/ status;
|
||||
+
|
||||
+ lan_led: led-lan {
|
||||
+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:lan";
|
||||
+ };
|
||||
+
|
||||
+ sys_led: led-sys {
|
||||
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "red:sys";
|
||||
+ default-state = "on";
|
||||
+ };
|
||||
+
|
||||
+ wan_led: led-wan {
|
||||
+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:wan";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+
|
||||
+ /delete-node/ power;
|
||||
+
|
||||
+ reset {
|
||||
+ debounce-interval = <50>;
|
||||
+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
|
||||
+ label = "reset";
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_5v: vdd-5v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vdd_5v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&emmc_phy {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&i2c4 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&pcie0 {
|
||||
+ max-link-speed = <1>;
|
||||
+ num-lanes = <1>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gpio-leds {
|
||||
+ /delete-node/ leds-gpio;
|
||||
+
|
||||
+ lan_led_pin: lan-led-pin {
|
||||
+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ sys_led_pin: sys-led-pin {
|
||||
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rockchip-key {
|
||||
+ /delete-node/ power-key;
|
||||
+
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&sdio0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_host {
|
||||
+ phy-supply = <&vdd_5v>;
|
||||
+};
|
||||
+
|
||||
+&u2phy1_host {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_0 {
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&vcc3v3_sys {
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/nanopi-r4s-rk3399_defconfig
|
||||
@@ -0,0 +1,63 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_ROCKCHIP_RK3399=y
|
||||
+CONFIG_TARGET_EVB_RK3399=y
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s"
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
|
||||
+CONFIG_MISC_INIT_R=y
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
+CONFIG_TPL=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_SYS_MMC_ENV_DEV=1
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_RAM_RK3399_LPDDR4=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_KEYBOARD=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_USB_ETHER_ASIX88179=y
|
||||
+CONFIG_USB_ETHER_MCS7830=y
|
||||
+CONFIG_USB_ETHER_RTL8152=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_DM_VIDEO=y
|
||||
+CONFIG_DISPLAY=y
|
||||
+CONFIG_VIDEO_ROCKCHIP=y
|
||||
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
@ -1,6 +1,6 @@
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
|
||||
@@ -109,6 +109,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
|
||||
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
|
||||
rk3328-evb.dtb \
|
||||
rk3328-nanopi-r2s.dtb \
|
||||
|
||||
@ -0,0 +1,23 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Declares externs for all device/uclass instances.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
|
||||
/* driver declarations - these allow DM_DRIVER_GET() to be used */
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
|
||||
extern U_BOOT_DRIVER(ns16550_serial);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
|
||||
|
||||
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
|
||||
extern UCLASS_DRIVER(clk);
|
||||
extern UCLASS_DRIVER(mmc);
|
||||
extern UCLASS_DRIVER(ram);
|
||||
extern UCLASS_DRIVER(serial);
|
||||
extern UCLASS_DRIVER(syscon);
|
||||
@ -12,19 +12,38 @@
|
||||
#include <dm.h>
|
||||
#include <dt-structs.h>
|
||||
|
||||
/* Node /clock-controller@ff440000 index 0 */
|
||||
/*
|
||||
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
|
||||
*
|
||||
* idx driver_info driver
|
||||
* --- -------------------- --------------------
|
||||
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
|
||||
* 1: dmc rockchip_rk3328_dmc
|
||||
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
|
||||
* 3: serial_at_ff130000 ns16550_serial
|
||||
* 4: syscon_at_ff100000 rockchip_rk3328_grf
|
||||
* --- -------------------- --------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Node /clock-controller@ff440000 index 0
|
||||
* driver rockchip_rk3328_cru parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
|
||||
.reg = {0xff440000, 0x1000},
|
||||
.rockchip_grf = 0x3a,
|
||||
};
|
||||
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
|
||||
.name = "rockchip_rk3328_cru",
|
||||
.plat = &dtv_clock_controller_at_ff440000,
|
||||
.plat = &dtv_clock_controller_at_ff440000,
|
||||
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /dmc index 1 */
|
||||
/*
|
||||
* Node /dmc index 1
|
||||
* driver rockchip_rk3328_dmc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
||||
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
|
||||
0xff720000, 0x1000, 0xff798000, 0x1000},
|
||||
@ -56,12 +75,15 @@ static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
||||
};
|
||||
U_BOOT_DRVINFO(dmc) = {
|
||||
.name = "rockchip_rk3328_dmc",
|
||||
.plat = &dtv_dmc,
|
||||
.plat = &dtv_dmc,
|
||||
.plat_size = sizeof(dtv_dmc),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /mmc@ff500000 index 2 */
|
||||
/*
|
||||
* Node /mmc@ff500000 index 2
|
||||
* driver rockchip_rk3288_dw_mshc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
||||
.bus_width = 0x4,
|
||||
.cap_sd_highspeed = true,
|
||||
@ -87,12 +109,15 @@ static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
||||
};
|
||||
U_BOOT_DRVINFO(mmc_at_ff500000) = {
|
||||
.name = "rockchip_rk3288_dw_mshc",
|
||||
.plat = &dtv_mmc_at_ff500000,
|
||||
.plat = &dtv_mmc_at_ff500000,
|
||||
.plat_size = sizeof(dtv_mmc_at_ff500000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /serial@ff130000 index 3 */
|
||||
/*
|
||||
* Node /serial@ff130000 index 3
|
||||
* driver ns16550_serial parent None
|
||||
*/
|
||||
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
||||
.clock_frequency = 0x16e3600,
|
||||
.clocks = {
|
||||
@ -109,18 +134,21 @@ static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
||||
};
|
||||
U_BOOT_DRVINFO(serial_at_ff130000) = {
|
||||
.name = "ns16550_serial",
|
||||
.plat = &dtv_serial_at_ff130000,
|
||||
.plat = &dtv_serial_at_ff130000,
|
||||
.plat_size = sizeof(dtv_serial_at_ff130000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /syscon@ff100000 index 4 */
|
||||
/*
|
||||
* Node /syscon@ff100000 index 4
|
||||
* driver rockchip_rk3328_grf parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
|
||||
.reg = {0xff100000, 0x1000},
|
||||
};
|
||||
U_BOOT_DRVINFO(syscon_at_ff100000) = {
|
||||
.name = "rockchip_rk3328_grf",
|
||||
.plat = &dtv_syscon_at_ff100000,
|
||||
.plat = &dtv_syscon_at_ff100000,
|
||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
@ -0,0 +1,23 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Declares externs for all device/uclass instances.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
|
||||
/* driver declarations - these allow DM_DRIVER_GET() to be used */
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
|
||||
extern U_BOOT_DRIVER(ns16550_serial);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
|
||||
|
||||
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
|
||||
extern UCLASS_DRIVER(clk);
|
||||
extern UCLASS_DRIVER(mmc);
|
||||
extern UCLASS_DRIVER(ram);
|
||||
extern UCLASS_DRIVER(serial);
|
||||
extern UCLASS_DRIVER(syscon);
|
||||
@ -1,29 +1,49 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* This file was generated by dtoc from a .dtb (device tree binary) file.
|
||||
* Declares the U_BOOT_DRIVER() records and platform data.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
/* Allow use of U_BOOT_DEVICE() in this file */
|
||||
#define DT_PLATDATA_C
|
||||
/* Allow use of U_BOOT_DRVINFO() in this file */
|
||||
#define DT_PLAT_C
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dt-structs.h>
|
||||
|
||||
/* Node /clock-controller@ff440000 index 0 */
|
||||
/*
|
||||
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
|
||||
*
|
||||
* idx driver_info driver
|
||||
* --- -------------------- --------------------
|
||||
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
|
||||
* 1: dmc rockchip_rk3328_dmc
|
||||
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
|
||||
* 3: serial_at_ff130000 ns16550_serial
|
||||
* 4: syscon_at_ff100000 rockchip_rk3328_grf
|
||||
* --- -------------------- --------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Node /clock-controller@ff440000 index 0
|
||||
* driver rockchip_rk3328_cru parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
|
||||
.reg = {0xff440000, 0x1000},
|
||||
.rockchip_grf = 0x3a,
|
||||
};
|
||||
U_BOOT_DEVICE(clock_controller_at_ff440000) = {
|
||||
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
|
||||
.name = "rockchip_rk3328_cru",
|
||||
.platdata = &dtv_clock_controller_at_ff440000,
|
||||
.platdata_size = sizeof(dtv_clock_controller_at_ff440000),
|
||||
.plat = &dtv_clock_controller_at_ff440000,
|
||||
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /dmc index 1 */
|
||||
/*
|
||||
* Node /dmc index 1
|
||||
* driver rockchip_rk3328_dmc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
||||
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
|
||||
0xff720000, 0x1000, 0xff798000, 0x1000},
|
||||
@ -53,30 +73,17 @@ static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
||||
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
|
||||
0x77, 0x77, 0x79, 0x9},
|
||||
};
|
||||
U_BOOT_DEVICE(dmc) = {
|
||||
U_BOOT_DRVINFO(dmc) = {
|
||||
.name = "rockchip_rk3328_dmc",
|
||||
.platdata = &dtv_dmc,
|
||||
.platdata_size = sizeof(dtv_dmc),
|
||||
.plat = &dtv_dmc,
|
||||
.plat_size = sizeof(dtv_dmc),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /pinctrl/gpio0@ff210000 index 2 */
|
||||
static struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = {
|
||||
.clocks = {
|
||||
{0, {200}},},
|
||||
.gpio_controller = true,
|
||||
.interrupt_controller = true,
|
||||
.interrupts = {0x0, 0x33, 0x4},
|
||||
.reg = {0xff210000, 0x100},
|
||||
};
|
||||
U_BOOT_DEVICE(gpio0_at_ff210000) = {
|
||||
.name = "rockchip_gpio_bank",
|
||||
.platdata = &dtv_gpio0_at_ff210000,
|
||||
.platdata_size = sizeof(dtv_gpio0_at_ff210000),
|
||||
.parent_idx = 4,
|
||||
};
|
||||
|
||||
/* Node /mmc@ff500000 index 3 */
|
||||
/*
|
||||
* Node /mmc@ff500000 index 2
|
||||
* driver rockchip_rk3288_dw_mshc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
||||
.bus_width = 0x4,
|
||||
.cap_sd_highspeed = true,
|
||||
@ -100,44 +107,17 @@ static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
||||
.vmmc_supply = 0x4b,
|
||||
.vqmmc_supply = 0x1e,
|
||||
};
|
||||
U_BOOT_DEVICE(mmc_at_ff500000) = {
|
||||
U_BOOT_DRVINFO(mmc_at_ff500000) = {
|
||||
.name = "rockchip_rk3288_dw_mshc",
|
||||
.platdata = &dtv_mmc_at_ff500000,
|
||||
.platdata_size = sizeof(dtv_mmc_at_ff500000),
|
||||
.plat = &dtv_mmc_at_ff500000,
|
||||
.plat_size = sizeof(dtv_mmc_at_ff500000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /pinctrl index 4 */
|
||||
static struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = {
|
||||
.ranges = true,
|
||||
.rockchip_grf = 0x3a,
|
||||
};
|
||||
U_BOOT_DEVICE(pinctrl) = {
|
||||
.name = "rockchip_rk3328_pinctrl",
|
||||
.platdata = &dtv_pinctrl,
|
||||
.platdata_size = sizeof(dtv_pinctrl),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /sdmmc-regulator index 5 */
|
||||
static struct dtd_regulator_fixed dtv_sdmmc_regulator = {
|
||||
.gpio = {0x61, 0x1e, 0x1},
|
||||
.pinctrl_0 = 0x67,
|
||||
.pinctrl_names = "default",
|
||||
.regulator_boot_on = true,
|
||||
.regulator_max_microvolt = 0x325aa0,
|
||||
.regulator_min_microvolt = 0x325aa0,
|
||||
.regulator_name = "vcc_sd",
|
||||
.vin_supply = 0x1c,
|
||||
};
|
||||
U_BOOT_DEVICE(sdmmc_regulator) = {
|
||||
.name = "regulator_fixed",
|
||||
.platdata = &dtv_sdmmc_regulator,
|
||||
.platdata_size = sizeof(dtv_sdmmc_regulator),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /serial@ff130000 index 6 */
|
||||
/*
|
||||
* Node /serial@ff130000 index 3
|
||||
* driver ns16550_serial parent None
|
||||
*/
|
||||
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
||||
.clock_frequency = 0x16e3600,
|
||||
.clocks = {
|
||||
@ -152,23 +132,24 @@ static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
||||
.reg_io_width = 0x4,
|
||||
.reg_shift = 0x2,
|
||||
};
|
||||
U_BOOT_DEVICE(serial_at_ff130000) = {
|
||||
U_BOOT_DRVINFO(serial_at_ff130000) = {
|
||||
.name = "ns16550_serial",
|
||||
.platdata = &dtv_serial_at_ff130000,
|
||||
.platdata_size = sizeof(dtv_serial_at_ff130000),
|
||||
.plat = &dtv_serial_at_ff130000,
|
||||
.plat_size = sizeof(dtv_serial_at_ff130000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /syscon@ff100000 index 7 */
|
||||
/*
|
||||
* Node /syscon@ff100000 index 4
|
||||
* driver rockchip_rk3328_grf parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
|
||||
.reg = {0xff100000, 0x1000},
|
||||
};
|
||||
U_BOOT_DEVICE(syscon_at_ff100000) = {
|
||||
U_BOOT_DRVINFO(syscon_at_ff100000) = {
|
||||
.name = "rockchip_rk3328_grf",
|
||||
.platdata = &dtv_syscon_at_ff100000,
|
||||
.platdata_size = sizeof(dtv_syscon_at_ff100000),
|
||||
.plat = &dtv_syscon_at_ff100000,
|
||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
void dm_populate_phandle_data(void) {
|
||||
}
|
||||
@ -1,7 +1,8 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* This file was generated by dtoc from a .dtb (device tree binary) file.
|
||||
* Defines the structs used to hold devicetree data.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
@ -18,23 +19,6 @@ struct dtd_ns16550_serial {
|
||||
fdt32_t reg_io_width;
|
||||
fdt32_t reg_shift;
|
||||
};
|
||||
struct dtd_regulator_fixed {
|
||||
fdt32_t gpio[3];
|
||||
fdt32_t pinctrl_0;
|
||||
const char * pinctrl_names;
|
||||
bool regulator_boot_on;
|
||||
fdt32_t regulator_max_microvolt;
|
||||
fdt32_t regulator_min_microvolt;
|
||||
const char * regulator_name;
|
||||
fdt32_t vin_supply;
|
||||
};
|
||||
struct dtd_rockchip_gpio_bank {
|
||||
struct phandle_1_arg clocks[1];
|
||||
bool gpio_controller;
|
||||
bool interrupt_controller;
|
||||
fdt32_t interrupts[3];
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
struct dtd_rockchip_rk3288_dw_mshc {
|
||||
fdt32_t bus_width;
|
||||
bool cap_sd_highspeed;
|
||||
@ -65,7 +49,3 @@ struct dtd_rockchip_rk3328_dmc {
|
||||
struct dtd_rockchip_rk3328_grf {
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
struct dtd_rockchip_rk3328_pinctrl {
|
||||
bool ranges;
|
||||
fdt32_t rockchip_grf;
|
||||
};
|
||||
|
||||
@ -0,0 +1,23 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Declares externs for all device/uclass instances.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
|
||||
/* driver declarations - these allow DM_DRIVER_GET() to be used */
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
|
||||
extern U_BOOT_DRIVER(ns16550_serial);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
|
||||
|
||||
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
|
||||
extern UCLASS_DRIVER(clk);
|
||||
extern UCLASS_DRIVER(mmc);
|
||||
extern UCLASS_DRIVER(ram);
|
||||
extern UCLASS_DRIVER(serial);
|
||||
extern UCLASS_DRIVER(syscon);
|
||||
@ -1,29 +1,49 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* This file was generated by dtoc from a .dtb (device tree binary) file.
|
||||
* Declares the U_BOOT_DRIVER() records and platform data.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
/* Allow use of U_BOOT_DEVICE() in this file */
|
||||
#define DT_PLATDATA_C
|
||||
/* Allow use of U_BOOT_DRVINFO() in this file */
|
||||
#define DT_PLAT_C
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dt-structs.h>
|
||||
|
||||
/* Node /clock-controller@ff440000 index 0 */
|
||||
/*
|
||||
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
|
||||
*
|
||||
* idx driver_info driver
|
||||
* --- -------------------- --------------------
|
||||
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
|
||||
* 1: dmc rockchip_rk3328_dmc
|
||||
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
|
||||
* 3: serial_at_ff130000 ns16550_serial
|
||||
* 4: syscon_at_ff100000 rockchip_rk3328_grf
|
||||
* --- -------------------- --------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Node /clock-controller@ff440000 index 0
|
||||
* driver rockchip_rk3328_cru parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
|
||||
.reg = {0xff440000, 0x1000},
|
||||
.rockchip_grf = 0x3a,
|
||||
};
|
||||
U_BOOT_DEVICE(clock_controller_at_ff440000) = {
|
||||
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
|
||||
.name = "rockchip_rk3328_cru",
|
||||
.platdata = &dtv_clock_controller_at_ff440000,
|
||||
.platdata_size = sizeof(dtv_clock_controller_at_ff440000),
|
||||
.plat = &dtv_clock_controller_at_ff440000,
|
||||
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /dmc index 1 */
|
||||
/*
|
||||
* Node /dmc index 1
|
||||
* driver rockchip_rk3328_dmc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
||||
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
|
||||
0xff720000, 0x1000, 0xff798000, 0x1000},
|
||||
@ -53,30 +73,17 @@ static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
||||
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
|
||||
0x77, 0x77, 0x79, 0x9},
|
||||
};
|
||||
U_BOOT_DEVICE(dmc) = {
|
||||
U_BOOT_DRVINFO(dmc) = {
|
||||
.name = "rockchip_rk3328_dmc",
|
||||
.platdata = &dtv_dmc,
|
||||
.platdata_size = sizeof(dtv_dmc),
|
||||
.plat = &dtv_dmc,
|
||||
.plat_size = sizeof(dtv_dmc),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /pinctrl/gpio0@ff210000 index 2 */
|
||||
static struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = {
|
||||
.clocks = {
|
||||
{0, {200}},},
|
||||
.gpio_controller = true,
|
||||
.interrupt_controller = true,
|
||||
.interrupts = {0x0, 0x33, 0x4},
|
||||
.reg = {0xff210000, 0x100},
|
||||
};
|
||||
U_BOOT_DEVICE(gpio0_at_ff210000) = {
|
||||
.name = "rockchip_gpio_bank",
|
||||
.platdata = &dtv_gpio0_at_ff210000,
|
||||
.platdata_size = sizeof(dtv_gpio0_at_ff210000),
|
||||
.parent_idx = 4,
|
||||
};
|
||||
|
||||
/* Node /mmc@ff500000 index 3 */
|
||||
/*
|
||||
* Node /mmc@ff500000 index 2
|
||||
* driver rockchip_rk3288_dw_mshc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
||||
.bus_width = 0x4,
|
||||
.cap_sd_highspeed = true,
|
||||
@ -100,44 +107,17 @@ static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
||||
.vmmc_supply = 0x4b,
|
||||
.vqmmc_supply = 0x1e,
|
||||
};
|
||||
U_BOOT_DEVICE(mmc_at_ff500000) = {
|
||||
U_BOOT_DRVINFO(mmc_at_ff500000) = {
|
||||
.name = "rockchip_rk3288_dw_mshc",
|
||||
.platdata = &dtv_mmc_at_ff500000,
|
||||
.platdata_size = sizeof(dtv_mmc_at_ff500000),
|
||||
.plat = &dtv_mmc_at_ff500000,
|
||||
.plat_size = sizeof(dtv_mmc_at_ff500000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /pinctrl index 4 */
|
||||
static struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = {
|
||||
.ranges = true,
|
||||
.rockchip_grf = 0x3a,
|
||||
};
|
||||
U_BOOT_DEVICE(pinctrl) = {
|
||||
.name = "rockchip_rk3328_pinctrl",
|
||||
.platdata = &dtv_pinctrl,
|
||||
.platdata_size = sizeof(dtv_pinctrl),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /sdmmc-regulator index 5 */
|
||||
static struct dtd_regulator_fixed dtv_sdmmc_regulator = {
|
||||
.gpio = {0x61, 0x1e, 0x1},
|
||||
.pinctrl_0 = 0x67,
|
||||
.pinctrl_names = "default",
|
||||
.regulator_boot_on = true,
|
||||
.regulator_max_microvolt = 0x325aa0,
|
||||
.regulator_min_microvolt = 0x325aa0,
|
||||
.regulator_name = "vcc_sd",
|
||||
.vin_supply = 0x1c,
|
||||
};
|
||||
U_BOOT_DEVICE(sdmmc_regulator) = {
|
||||
.name = "regulator_fixed",
|
||||
.platdata = &dtv_sdmmc_regulator,
|
||||
.platdata_size = sizeof(dtv_sdmmc_regulator),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /serial@ff130000 index 6 */
|
||||
/*
|
||||
* Node /serial@ff130000 index 3
|
||||
* driver ns16550_serial parent None
|
||||
*/
|
||||
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
||||
.clock_frequency = 0x16e3600,
|
||||
.clocks = {
|
||||
@ -152,23 +132,24 @@ static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
||||
.reg_io_width = 0x4,
|
||||
.reg_shift = 0x2,
|
||||
};
|
||||
U_BOOT_DEVICE(serial_at_ff130000) = {
|
||||
U_BOOT_DRVINFO(serial_at_ff130000) = {
|
||||
.name = "ns16550_serial",
|
||||
.platdata = &dtv_serial_at_ff130000,
|
||||
.platdata_size = sizeof(dtv_serial_at_ff130000),
|
||||
.plat = &dtv_serial_at_ff130000,
|
||||
.plat_size = sizeof(dtv_serial_at_ff130000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /syscon@ff100000 index 7 */
|
||||
/*
|
||||
* Node /syscon@ff100000 index 4
|
||||
* driver rockchip_rk3328_grf parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
|
||||
.reg = {0xff100000, 0x1000},
|
||||
};
|
||||
U_BOOT_DEVICE(syscon_at_ff100000) = {
|
||||
U_BOOT_DRVINFO(syscon_at_ff100000) = {
|
||||
.name = "rockchip_rk3328_grf",
|
||||
.platdata = &dtv_syscon_at_ff100000,
|
||||
.platdata_size = sizeof(dtv_syscon_at_ff100000),
|
||||
.plat = &dtv_syscon_at_ff100000,
|
||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
void dm_populate_phandle_data(void) {
|
||||
}
|
||||
@ -1,7 +1,8 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* This file was generated by dtoc from a .dtb (device tree binary) file.
|
||||
* Defines the structs used to hold devicetree data.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
@ -18,23 +19,6 @@ struct dtd_ns16550_serial {
|
||||
fdt32_t reg_io_width;
|
||||
fdt32_t reg_shift;
|
||||
};
|
||||
struct dtd_regulator_fixed {
|
||||
fdt32_t gpio[3];
|
||||
fdt32_t pinctrl_0;
|
||||
const char * pinctrl_names;
|
||||
bool regulator_boot_on;
|
||||
fdt32_t regulator_max_microvolt;
|
||||
fdt32_t regulator_min_microvolt;
|
||||
const char * regulator_name;
|
||||
fdt32_t vin_supply;
|
||||
};
|
||||
struct dtd_rockchip_gpio_bank {
|
||||
struct phandle_1_arg clocks[1];
|
||||
bool gpio_controller;
|
||||
bool interrupt_controller;
|
||||
fdt32_t interrupts[3];
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
struct dtd_rockchip_rk3288_dw_mshc {
|
||||
fdt32_t bus_width;
|
||||
bool cap_sd_highspeed;
|
||||
@ -65,7 +49,3 @@ struct dtd_rockchip_rk3328_dmc {
|
||||
struct dtd_rockchip_rk3328_grf {
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
struct dtd_rockchip_rk3328_pinctrl {
|
||||
bool ranges;
|
||||
fdt32_t rockchip_grf;
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user