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mediatek: update gpy211 driver
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hanwckf
parent
701919f949
commit
572c2ee8a2
@ -1,31 +1,107 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/delay.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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struct t_phydev {
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// struct timer_list timer;
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struct phy_device *phydev;
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struct delayed_work dw;
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};
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#define PHY_MIISTAT 0x18
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#define PHY_MIISTAT_SPD_MASK GENMASK(2, 0)
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#define PHY_MIISTAT_DPX BIT(3)
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#define PHY_MIISTAT_LS BIT(10)
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#define PHY_MIISTAT_SPD_10 0
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#define PHY_MIISTAT_SPD_100 1
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#define PHY_MIISTAT_SPD_1000 2
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#define PHY_MIISTAT_SPD_2500 4
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void gpy211_status_timer(struct work_struct *t);
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// Starder Magament Registers
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#define MDIO_MMD_STD 0x0
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#define VSPEC1_NBT_DS_CTRL 0xA
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#define DOWNSHIFT_THR_MASK GENMASK(6, 2)
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#define DOWNSHIFT_EN BIT(1)
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#define DEFAULT_INTEL_GPY211_PHYID1_VALUE 0x67c9
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#define MAXLINEAR_MAX_LED_INDEX 4
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static int gpy211_phy_config_init(struct phy_device *phydev)
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{
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int sgmii_reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, 8);
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if (sgmii_reg != 0x24e2){
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phy_write_mmd(phydev, MDIO_MMD_VEND1, 8, 0x24e2);
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}
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phy_write_mmd(phydev, MDIO_MMD_VEND1, 1, 0x03f0);
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return 0;
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}
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#define MAX_RETRY_TIMES 80
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#define RETRY_INTERVAL 10 // unit is ms
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int gpy211_phy_probe(struct phy_device *phydev)
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{
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int sgmii_reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, 8);
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struct device_node *of_node = phydev->mdio.dev.of_node;
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u32 reg_value[MAXLINEAR_MAX_LED_INDEX] = {0};
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int ret;
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int i=0;
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u32 phyid1;
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int buf = 0;
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/*
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* After reset signal to GPY211B1VC(SSTEP SLN8A), the chip may take 600 ms to bootup complete.
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* driver can successfully read/write the register after bootup complete.
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* If phy is ready, the STD_PHYID1(Register 0.2) should be 0x67c9.
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*/
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i = MAX_RETRY_TIMES;
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while (i) {
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phyid1 = phy_read_mmd(phydev, MDIO_MMD_STD, MDIO_DEVID1);
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if ( phyid1 == DEFAULT_INTEL_GPY211_PHYID1_VALUE )
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break;
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msleep(RETRY_INTERVAL);
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i--;
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}
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if (!i) {
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phydev_err(phydev, "phy is not ready over %d ms!\n", (MAX_RETRY_TIMES-i)*10);
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}else {
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phydev_info(phydev, "driver wait %d ms for phy ready!\n", (MAX_RETRY_TIMES-i)*10);
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}
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ret = of_property_read_u32_array(of_node, "maxlinear,led-reg", reg_value, MAXLINEAR_MAX_LED_INDEX);
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if (ret < 0) {
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phydev_info(phydev, "not config \"maxlinear,led-reg\" parameter\n");
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} else {
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for(i=0;i<MAXLINEAR_MAX_LED_INDEX;i++) {
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phydev_dbg(phydev, "led-reg %d is %x.\n", i, reg_value[i]);
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phy_write_mmd(phydev, MDIO_MMD_VEND1, i+1, reg_value[i]);
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}
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}
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/* enable 2.5G SGMII rate adaption */
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phy_write_mmd(phydev, MDIO_MMD_VEND1, 8, 0x24e2);
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buf = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_NBT_DS_CTRL);
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//enable downshift and set training counter threshold to 3
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_NBT_DS_CTRL, buf | FIELD_PREP(DOWNSHIFT_THR_MASK, 0x3) | DOWNSHIFT_EN);
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return 0;
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}
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static int gpy211_get_features(struct phy_device *phydev)
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{
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struct t_phydev *t_phy;
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t_phy = kzalloc(sizeof(*t_phy), GFP_KERNEL);
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t_phy->phydev = phydev;
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int ret;
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ret = genphy_read_abilities(phydev);
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@ -33,6 +109,7 @@ static int gpy211_get_features(struct phy_device *phydev)
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return ret;
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/* GPY211 with rate adaption supports 100M/1G/2.5G speed. */
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linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
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phydev->supported);
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linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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@ -40,9 +117,76 @@ static int gpy211_get_features(struct phy_device *phydev)
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linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
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phydev->supported);
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//set timer to query status
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// timer_setup(&t_phy->timer, gpy211_status_timer, 0);
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// mod_timer(&t_phy->timer, jiffies + 20*HZ);
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INIT_DELAYED_WORK(&t_phy->dw, gpy211_status_timer);
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schedule_delayed_work(&t_phy->dw, msecs_to_jiffies(2000));
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return 0;
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}
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static int gpy_read_status(struct phy_device *phydev)
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{
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int old_link = phydev->link;
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const char *speed;
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const char *duplex;
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phydev_dbg(phydev, "### line[%d] addr[%d] link[%d] phyid[0x%x]\n", __LINE__, phydev->mdio.addr, phydev->link, phydev->phy_id);
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struct device_node *of_node = phydev->mdio.dev.of_node;
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// int ret = phydev->mdio.bus->read(phydev->mdio.bus, phydev->mdio.addr, PHY_MIISTAT);
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int ret = phy_read_mmd(phydev, MDIO_MMD_STD, PHY_MIISTAT);
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if(ret)
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{
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phydev_dbg(phydev, "### line[%d] addr[%d] val=[0x%x] link[%d] phyid[0x%x]\n", __LINE__, phydev->mdio.addr, ret, phydev->link, phydev->phy_id);
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phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0;
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phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF;
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duplex = (phydev->duplex == DUPLEX_FULL) ? "F" : "H";
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switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) {
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case PHY_MIISTAT_SPD_10:
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phydev->speed = SPEED_10;
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speed = "10";
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break;
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case PHY_MIISTAT_SPD_100:
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phydev->speed = SPEED_100;
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speed = "100";
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break;
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case PHY_MIISTAT_SPD_1000:
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phydev->speed = SPEED_1000;
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speed = "1000";
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break;
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case PHY_MIISTAT_SPD_2500:
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phydev->speed = SPEED_2500;
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speed = "2500";
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break;
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}
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phydev_dbg(phydev, "### line[%d] addr[%d] old[%d] newlink[%d] \n", __LINE__, phydev->mdio.addr, old_link, phydev->link);
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if(old_link != phydev->link)
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{
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if(phydev->link)
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phydev_info(phydev, "###phy_addr[%d] link up speed[%s]\n", phydev->mdio.addr, speed);
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else
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phydev_info(phydev, "###phy_addr[%d] link down \n", phydev->mdio.addr);
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}
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}
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return 0;
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}
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void gpy211_status_timer(struct work_struct *t)
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{
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struct t_phydev *t_phy = container_of(t, struct t_phydev, dw.work);
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gpy_read_status(t_phy->phydev);
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//trigger timer again
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// mod_timer(&t_phy->timer, jiffies + HZ);
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schedule_delayed_work(&t_phy->dw, msecs_to_jiffies(2000));
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}
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static struct phy_driver gpy211_phy_driver[] = {
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{
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PHY_ID_MATCH_MODEL(0x67c9de0a),
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@ -50,6 +194,7 @@ static struct phy_driver gpy211_phy_driver[] = {
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.config_init = gpy211_phy_config_init,
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.probe = gpy211_phy_probe,
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.get_features = gpy211_get_features,
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.read_status = gpy_read_status,
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}
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};
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