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conninfra: update to mt79xx_conninfra_20231229-f2fa25 (sdk 7.6.7.2)

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hanwckf 2024-10-14 00:16:48 +08:00
parent 89b7b28e8f
commit 3ea918e9cc
49 changed files with 2 additions and 13532 deletions
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dl/mt79xx_conninfra_20231229-f2fa25.tar.xz Normal file
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3
package/mtk/drivers/conninfra/Makefile
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@ -9,7 +9,8 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=conninfra
PKG_VERSION:=bbf588
PKG_VERSION:=f2fa25
PKG_SOURCE:=mt79xx_conninfra_20231229-f2fa25.tar.xz
PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)
PKG_MAINTAINER:=Kun-Ze Syue<kun-ze.syue@mediatek.com>

66
package/mtk/drivers/conninfra/src/Makefile
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@ -1,66 +0,0 @@
###############################################################################
# Necessary Check
#ifeq ($(AUTOCONF_H),)
# $(error AUTOCONF_H is not defined)
#endif
#ccflags-y += -imacros $(AUTOCONF_H)
# Force build fail on modpost warning
KBUILD_MODPOST_FAIL_ON_WARNINGS := y
###############################################################################
ccflags-y += -Werror
ccflags-y += -Wno-error=format
ccflags-y += -Wno-error=format-extra-args
ccflags-y += -Wframe-larger-than=1024
###############################################################################
MODULE_NAME := conninfra
obj-m += $(MODULE_NAME).o
###############################################################################
# common_main
###############################################################################
ccflags-y += \
-I$(SUBDIRS)/include \
-I$(SUBDIRS)/base/include \
-I$(SUBDIRS)/core/include \
-I$(SUBDIRS)/conf/include \
-I$(SUBDIRS)/platform/include
$(MODULE_NAME)-objs += base/ring.o
$(MODULE_NAME)-objs += base/osal.o
$(MODULE_NAME)-objs += base/msg_thread.o
$(MODULE_NAME)-objs += core/conninfra_core.o
$(MODULE_NAME)-objs += src/conninfra_dev.o
$(MODULE_NAME)-objs += src/conninfra.o
$(MODULE_NAME)-objs += platform/consys_hw.o
$(MODULE_NAME)-objs += platform/consys_hw_plat_data.o
$(MODULE_NAME)-objs += platform/pmic_mng.o
$(MODULE_NAME)-objs += platform/emi_mng.o
$(MODULE_NAME)-objs += platform/consys_reg_mng.o
# By Plaftfrom
# MT7986
ifeq ($(CONFIG_MTK_CONNINFRA_APSOC_MT7986),y)
ccflags-y += \
-I$(SUBDIRS)/platform/mt7986/include -DCONNINFRA_APSOC_MT7986
$(MODULE_NAME)-objs += platform/mt7986/mt7986.o
$(MODULE_NAME)-objs += platform/mt7986/mt7986_pmic.o
$(MODULE_NAME)-objs += platform/mt7986/mt7986_consys_reg.o
$(MODULE_NAME)-objs += platform/mt7986/mt7986_pos.o
$(MODULE_NAME)-objs += platform/mt7986/mt7986_emi.o
endif
# MT7981
ifeq ($(CONFIG_MTK_CONNINFRA_APSOC_MT7981),y)
ccflags-y += \
-I$(SUBDIRS)/platform/mt7981/include -DCONNINFRA_APSOC_MT7981
$(MODULE_NAME)-objs += platform/mt7981/mt7981.o
$(MODULE_NAME)-objs += platform/mt7981/mt7981_pmic.o
$(MODULE_NAME)-objs += platform/mt7981/mt7981_consys_reg.o
$(MODULE_NAME)-objs += platform/mt7981/mt7981_pos.o
$(MODULE_NAME)-objs += platform/mt7981/mt7981_emi.o
endif

202
package/mtk/drivers/conninfra/src/NOTICE
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@ -1,202 +0,0 @@
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END OF TERMS AND CONDITIONS

141
package/mtk/drivers/conninfra/src/base/include/msg_thread.h
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@ -1,141 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _BASE_MSG_THREAD_H_
#define _BASE_MSG_THREAD_H_
#include "osal.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
#define MSG_THREAD_OP_DATA_SIZE 8
#define MSG_THREAD_OP_BUF_SIZE 64
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
struct msg_op_data {
unsigned int op_id; /* Event ID */
unsigned int info_bit; /* Reserved */
size_t op_data[MSG_THREAD_OP_DATA_SIZE]; /* OP Data */
};
struct msg_op {
struct msg_op_data op;
OSAL_SIGNAL signal;
int result;
atomic_t ref_count;
};
struct msg_op_q {
OSAL_SLEEPABLE_LOCK lock;
unsigned int write;
unsigned int read;
unsigned int size;
struct msg_op *queue[MSG_THREAD_OP_BUF_SIZE];
};
typedef OSAL_OP_DAT msg_evt_op;
typedef int(*msg_opid_func) (struct msg_op_data *);
struct msg_thread_ctx {
OSAL_THREAD thread; /* core thread */
OSAL_EVENT evt;
struct msg_op_q free_op_q; /* free op queue */
struct msg_op_q active_op_q; /* active op queue */
struct msg_op op_q_inst[MSG_THREAD_OP_BUF_SIZE]; /* real op instances */
struct msg_op *cur_op; /* current op */
int op_func_size;
const msg_opid_func *op_func;
struct osal_op_history op_history;
};
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
#define MSG_OP_TIMEOUT 20000
int msg_thread_init(struct msg_thread_ctx *ctx, const char *name,
const msg_opid_func *func, int op_size);
int msg_thread_deinit(struct msg_thread_ctx *ctx);
/* timeout:
* 0: default value (by MSG_OP_TIMEOUT define)
* >0: cutom timeout (ms)
*/
int msg_thread_send(struct msg_thread_ctx *ctx, int opid);
int msg_thread_send_1(struct msg_thread_ctx *ctx, int opid,
size_t param1);
int msg_thread_send_2(struct msg_thread_ctx *ctx, int opid,
size_t param1, size_t param2);
int msg_thread_send_wait(struct msg_thread_ctx *ctx, int opid,
int timeout);
int msg_thread_send_wait_1(struct msg_thread_ctx *ctx, int opid,
int timeout, size_t param1);
int msg_thread_send_wait_2(struct msg_thread_ctx *ctx, int opid,
int timeout, size_t param1, size_t param2);
int msg_thread_send_wait_3(struct msg_thread_ctx *ctx, int opid, int timeout, size_t param1,
size_t param2,size_t param3);
int msg_thread_dump(struct msg_thread_ctx *ctx);
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#endif /* _BASE_MSG_THREAD_H_ */

399
package/mtk/drivers/conninfra/src/base/include/osal.h
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@ -1,399 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _OSAL_H_
#define _OSAL_H_
#include <linux/workqueue.h>
#include <linux/mutex.h>
#include <linux/completion.h>
#include <linux/wait.h>
#include "ring.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
#define OS_BIT_OPS_SUPPORT 1
#ifndef MTK_CONN_BOOL_TRUE
#define MTK_CONN_BOOL_FALSE ((MTK_CONN_BOOL) 0)
#define MTK_CONN_BOOL_TRUE ((MTK_CONN_BOOL) 1)
#endif
#define _osal_inline_ inline
#define MAX_THREAD_NAME_LEN 16
#define MAX_HISTORY_NAME_LEN 16
#define OSAL_OP_BUF_SIZE 64
#if (defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) && !defined(CONFIG_MTK_ENG_BUILD))
#define OSAL_OP_DATA_SIZE 8
#else
#define OSAL_OP_DATA_SIZE 32
#endif
#define DBG_LOG_STR_SIZE 256
#define osal_sizeof(x) sizeof(x)
#define osal_array_size(x) ARRAY_SIZE(x)
#ifndef NAME_MAX
#define NAME_MAX 256
#endif
#define WMT_OP_BIT(x) (0x1UL << x)
#define WMT_OP_HIF_BIT WMT_OP_BIT(0)
#define GET_BIT_MASK(value, mask) ((value) & (mask))
#define SET_BIT_MASK(pdest, value, mask) (*(pdest) = (GET_BIT_MASK(*(pdest), ~(mask)) | GET_BIT_MASK(value, mask)))
#define GET_BIT_RANGE(data, end, begin) ((data) & GENMASK(end, begin))
#define SET_BIT_RANGE(pdest, data, end, begin) (SET_BIT_MASK(pdest, data, GENMASK(end, begin)))
#define RB_LATEST(prb) ((prb)->write - 1)
#define RB_SIZE(prb) ((prb)->size)
#define RB_MASK(prb) (RB_SIZE(prb) - 1)
#define RB_COUNT(prb) ((prb)->write - (prb)->read)
#define RB_FULL(prb) (RB_COUNT(prb) >= RB_SIZE(prb))
#define RB_EMPTY(prb) ((prb)->write == (prb)->read)
#define RB_INIT(prb, qsize) \
do { \
(prb)->read = (prb)->write = 0; \
(prb)->size = (qsize); \
} while (0)
#define RB_PUT(prb, value) \
do { \
if (!RB_FULL(prb)) { \
(prb)->queue[(prb)->write & RB_MASK(prb)] = value; \
++((prb)->write); \
} \
else { \
pr_warn("RB is full!"); \
} \
} while (0)
#define RB_GET(prb, value) \
do { \
if (!RB_EMPTY(prb)) { \
value = (prb)->queue[(prb)->read & RB_MASK(prb)]; \
++((prb)->read); \
if (RB_EMPTY(prb)) { \
(prb)->read = (prb)->write = 0; \
} \
} \
else { \
value = NULL; \
pr_warn("RB is empty!"); \
} \
} while (0)
#define RB_GET_LATEST(prb, value) \
do { \
if (!RB_EMPTY(prb)) { \
value = (prb)->queue[RB_LATEST(prb) & RB_MASK(prb)]; \
if (RB_EMPTY(prb)) { \
(prb)->read = (prb)->write = 0; \
} \
} \
else { \
value = NULL; \
} \
} while (0)
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
typedef int MTK_CONN_BOOL;
typedef int(*P_COND) (void *);
typedef struct _OSAL_UNSLEEPABLE_LOCK_ {
spinlock_t lock;
unsigned long flag;
} OSAL_UNSLEEPABLE_LOCK, *P_OSAL_UNSLEEPABLE_LOCK;
typedef struct _OSAL_SLEEPABLE_LOCK_ {
struct mutex lock;
} OSAL_SLEEPABLE_LOCK, *P_OSAL_SLEEPABLE_LOCK;
typedef struct _OSAL_SIGNAL_ {
struct completion comp;
unsigned int timeoutValue;
unsigned int timeoutExtension; /* max number of timeout caused by thread not able to acquire CPU */
} OSAL_SIGNAL, *P_OSAL_SIGNAL;
typedef struct _OSAL_EVENT_ {
wait_queue_head_t waitQueue;
unsigned int timeoutValue;
int waitFlag;
} OSAL_EVENT, *P_OSAL_EVENT;
/* Data collected from sched_entity and sched_statistics */
typedef struct _OSAL_THREAD_SCHEDSTATS_ {
unsigned long long time; /* when marked: the profiling start time(ms), when unmarked: total duration(ms) */
unsigned long long exec; /* time spent in exec (sum_exec_runtime) */
unsigned long long runnable; /* time spent in run-queue while not being scheduled (wait_sum) */
unsigned long long iowait; /* time spent waiting for I/O (iowait_sum) */
} OSAL_THREAD_SCHEDSTATS, *P_OSAL_THREAD_SCHEDSTATS;
typedef struct _OSAL_THREAD_ {
struct task_struct *pThread;
void *pThreadFunc;
void *pThreadData;
char threadName[MAX_THREAD_NAME_LEN];
} OSAL_THREAD, *P_OSAL_THREAD;
typedef struct _OSAL_FIFO_ {
/*fifo definition */
void *pFifoBody;
spinlock_t fifoSpinlock;
/*fifo operations */
int (*FifoInit)(struct _OSAL_FIFO_ *pFifo, unsigned char *buf, unsigned int);
int (*FifoDeInit)(struct _OSAL_FIFO_ *pFifo);
int (*FifoReset)(struct _OSAL_FIFO_ *pFifo);
int (*FifoSz)(struct _OSAL_FIFO_ *pFifo);
int (*FifoAvailSz)(struct _OSAL_FIFO_ *pFifo);
int (*FifoLen)(struct _OSAL_FIFO_ *pFifo);
int (*FifoIsEmpty)(struct _OSAL_FIFO_ *pFifo);
int (*FifoIsFull)(struct _OSAL_FIFO_ *pFifo);
int (*FifoDataIn)(struct _OSAL_FIFO_ *pFifo, const void *buf, unsigned int len);
int (*FifoDataOut)(struct _OSAL_FIFO_ *pFifo, void *buf, unsigned int len);
} OSAL_FIFO, *P_OSAL_FIFO;
typedef struct firmware osal_firmware;
typedef struct _OSAL_OP_DAT {
unsigned int opId; /* Event ID */
unsigned int u4InfoBit; /* Reserved */
size_t au4OpData[OSAL_OP_DATA_SIZE]; /* OP Data */
} OSAL_OP_DAT, *P_OSAL_OP_DAT;
typedef struct _OSAL_LXOP_ {
OSAL_OP_DAT op;
OSAL_SIGNAL signal;
int result;
atomic_t ref_count;
} OSAL_OP, *P_OSAL_OP;
typedef struct _OSAL_LXOP_Q {
OSAL_SLEEPABLE_LOCK sLock;
unsigned int write;
unsigned int read;
unsigned int size;
P_OSAL_OP queue[OSAL_OP_BUF_SIZE];
} OSAL_OP_Q, *P_OSAL_OP_Q;
typedef struct _OSAL_BIT_OP_VAR_ {
unsigned long data;
OSAL_UNSLEEPABLE_LOCK opLock;
} OSAL_BIT_OP_VAR, *P_OSAL_BIT_OP_VAR;
typedef unsigned int (*P_OSAL_EVENT_CHECKER) (P_OSAL_THREAD pThread);
struct osal_op_history_entry {
void *opbuf_address;
unsigned int op_id;
unsigned int opbuf_ref_count;
unsigned int op_info_bit;
size_t param_0;
size_t param_1;
size_t param_2;
size_t param_3;
unsigned long long ts;
unsigned long usec;
};
struct osal_op_history {
struct ring ring_buffer;
struct osal_op_history_entry *queue;
spinlock_t lock;
struct ring dump_ring_buffer;
struct work_struct dump_work;
unsigned char name[MAX_HISTORY_NAME_LEN];
};
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
void FlashRead(char *name,unsigned char *value, unsigned long offset, unsigned long size);
void FlashWrite(char *name, unsigned char *p, unsigned long a, unsigned long b);
unsigned int osal_strlen(const char *str);
int osal_strcmp(const char *dst, const char *src);
int osal_strncmp(const char *dst, const char *src, unsigned int len);
char *osal_strcpy(char *dst, const char *src);
char *osal_strncpy(char *dst, const char *src, unsigned int len);
char *osal_strcat(char *dst, const char *src);
char *osal_strncat(char *dst, const char *src, unsigned int len);
char *osal_strchr(const char *str, unsigned char c);
char *osal_strsep(char **str, const char *c);
int osal_strtol(const char *str, unsigned int adecimal, long *res);
char *osal_strstr(char *str1, const char *str2);
char *osal_strnstr(char *str1, const char *str2, int n);
void osal_bug_on(unsigned int val);
int osal_snprintf(char *buf, unsigned int len, const char *fmt, ...);
int osal_sprintf(char *str, const char *format, ...);
void *osal_malloc(unsigned int size);
void osal_free(const void *dst);
void *osal_memset(void *buf, int i, unsigned int len);
void *osal_memcpy(void *dst, const void *src, unsigned int len);
void osal_memcpy_fromio(void *dst, const void *src, unsigned int len);
void osal_memcpy_toio(void *dst, const void *src, unsigned int len);
int osal_memcmp(const void *buf1, const void *buf2, unsigned int len);
int osal_sleep_ms(unsigned int ms);
int osal_udelay(unsigned int us);
int osal_usleep_range(unsigned long min, unsigned long max);
int osal_fifo_init(P_OSAL_FIFO pFifo, unsigned char *buffer, unsigned int size);
void osal_fifo_deinit(P_OSAL_FIFO pFifo);
int osal_fifo_reset(P_OSAL_FIFO pFifo);
unsigned int osal_fifo_in(P_OSAL_FIFO pFifo, unsigned char *buffer,
unsigned int size);
unsigned int osal_fifo_out(P_OSAL_FIFO pFifo, unsigned char *buffer,
unsigned int size);
unsigned int osal_fifo_len(P_OSAL_FIFO pFifo);
unsigned int osal_fifo_sz(P_OSAL_FIFO pFifo);
unsigned int osal_fifo_avail(P_OSAL_FIFO pFifo);
unsigned int osal_fifo_is_empty(P_OSAL_FIFO pFifo);
unsigned int osal_fifo_is_full(P_OSAL_FIFO pFifo);
#if defined(CONFIG_PROVE_LOCKING)
#define osal_unsleepable_lock_init(l) { spin_lock_init(&((l)->lock)); }
#else
int osal_unsleepable_lock_init(P_OSAL_UNSLEEPABLE_LOCK);
#endif
int osal_lock_unsleepable_lock(P_OSAL_UNSLEEPABLE_LOCK);
int osal_unlock_unsleepable_lock(P_OSAL_UNSLEEPABLE_LOCK);
int osal_unsleepable_lock_deinit(P_OSAL_UNSLEEPABLE_LOCK);
#if defined(CONFIG_PROVE_LOCKING)
#define osal_sleepable_lock_init(l) { mutex_init(&((l)->lock)); }
#else
int osal_sleepable_lock_init(P_OSAL_SLEEPABLE_LOCK);
#endif
int osal_lock_sleepable_lock(P_OSAL_SLEEPABLE_LOCK);
int osal_unlock_sleepable_lock(P_OSAL_SLEEPABLE_LOCK);
int osal_trylock_sleepable_lock(P_OSAL_SLEEPABLE_LOCK);
int osal_sleepable_lock_deinit(P_OSAL_SLEEPABLE_LOCK);
int osal_signal_init(P_OSAL_SIGNAL);
int osal_wait_for_signal(P_OSAL_SIGNAL);
int osal_wait_for_signal_timeout(P_OSAL_SIGNAL, P_OSAL_THREAD);
int osal_raise_signal(P_OSAL_SIGNAL);
int osal_signal_active_state(P_OSAL_SIGNAL pSignal);
int osal_signal_deinit(P_OSAL_SIGNAL);
int osal_event_init(P_OSAL_EVENT);
int osal_wait_for_event(P_OSAL_EVENT, P_COND, void*);
int osal_wait_for_event_timeout(P_OSAL_EVENT, P_COND, void*);
extern int osal_trigger_event(P_OSAL_EVENT);
int osal_event_deinit(P_OSAL_EVENT);
long osal_wait_for_event_bit_set(P_OSAL_EVENT pEvent, unsigned long *pState, unsigned int bitOffset);
long osal_wait_for_event_bit_clr(P_OSAL_EVENT pEvent, unsigned long *pState, unsigned int bitOffset);
int osal_thread_create(P_OSAL_THREAD);
int osal_thread_run(P_OSAL_THREAD);
int osal_thread_should_stop(P_OSAL_THREAD);
int osal_thread_stop(P_OSAL_THREAD);
/*int osal_thread_wait_for_event(P_OSAL_THREAD, P_OSAL_EVENT);*/
int osal_thread_wait_for_event(P_OSAL_THREAD, P_OSAL_EVENT, P_OSAL_EVENT_CHECKER);
/*check pOsalLxOp and OSAL_THREAD_SHOULD_STOP*/
int osal_thread_destroy(P_OSAL_THREAD);
int osal_thread_sched_mark(P_OSAL_THREAD, P_OSAL_THREAD_SCHEDSTATS schedstats);
int osal_thread_sched_unmark(P_OSAL_THREAD pThread, P_OSAL_THREAD_SCHEDSTATS schedstats);
int osal_clear_bit(unsigned int bitOffset, P_OSAL_BIT_OP_VAR pData);
int osal_set_bit(unsigned int bitOffset, P_OSAL_BIT_OP_VAR pData);
int osal_test_bit(unsigned int bitOffset, P_OSAL_BIT_OP_VAR pData);
int osal_test_and_clear_bit(unsigned int bitOffset, P_OSAL_BIT_OP_VAR pData);
int osal_test_and_set_bit(unsigned int bitOffset, P_OSAL_BIT_OP_VAR pData);
int osal_gettimeofday(int *sec, int *usec);
int osal_gettimeofday2(struct timeval *tv);
//int osal_printtimeofday(const unsigned char *prefix);
void osal_get_local_time(unsigned long long *sec, unsigned long *nsec);
unsigned long long osal_elapsed_us(unsigned long long ts, unsigned long usec);
void osal_buffer_dump(const unsigned char *buf, const unsigned char *title, unsigned int len, unsigned int limit);
void osal_buffer_dump_data(const unsigned int *buf, const unsigned char *title, const unsigned int len, const unsigned int limit,
const int flag);
unsigned int osal_op_get_id(P_OSAL_OP pOp);
MTK_CONN_BOOL osal_op_is_wait_for_signal(P_OSAL_OP pOp);
void osal_op_raise_signal(P_OSAL_OP pOp, int result);
void osal_set_op_result(P_OSAL_OP pOp, int result);
void osal_opq_dump(const char *qName, P_OSAL_OP_Q pOpQ);
void osal_opq_dump_locked(const char *qName, P_OSAL_OP_Q pOpQ);
MTK_CONN_BOOL osal_opq_has_op(P_OSAL_OP_Q pOpQ, P_OSAL_OP pOp);
int osal_ftrace_print(const char *str, ...);
int osal_ftrace_print_ctrl(int flag);
void osal_dump_thread_state(const unsigned char *name);
void osal_op_history_init(struct osal_op_history *log_history, int queue_size);
void osal_op_history_save(struct osal_op_history *log_history, P_OSAL_OP pOp);
void osal_op_history_print(struct osal_op_history *log_history, char *name);
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#endif /* _OSAL_H_ */

95
package/mtk/drivers/conninfra/src/base/include/ring.h
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@ -1,95 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
#ifndef _RING_H_
#define _RING_H_
struct ring {
/* addr where ring buffer starts */
void *base;
/* addr storing the next writable pos, guaranteed to be >= read except when write overflow, but it's ok. */
unsigned int write;
/* addr storing the next readable pos, except when read == write as buffer empty */
unsigned int read;
/* must be power of 2 */
unsigned int max_size;
};
struct ring_segment {
/* addr points into ring buffer for read/write */
void *ring_pt;
/* size to read/write */
unsigned int sz;
/* pos in external data buffer to read/write */
unsigned int data_pos;
/* the size to be read/write after this segment completed */
unsigned int remain;
};
void ring_init(void *base, unsigned int max_size, unsigned int read,
unsigned int write, struct ring *ring);
unsigned int ring_read_prepare(unsigned int sz, struct ring_segment *seg, struct ring *ring);
#define ring_read_all_prepare(seg, ring) ring_read_prepare((ring)->max_size, seg, ring)
unsigned int ring_write_prepare(unsigned int sz, struct ring_segment *seg, struct ring *ring);
unsigned int ring_overwrite_prepare(unsigned int sz,
struct ring_segment *seg, struct ring *ring);
/* making sure max_size is power of 2 */
#define RING_VALIDATE_SIZE(max_size) WARN_ON(!max_size || (max_size & (max_size - 1)))
#define RING_EMPTY(ring) ((ring)->read == (ring)->write)
/* equation works even when write overflow */
#define RING_SIZE(ring) ((ring)->write - (ring)->read)
#define RING_FULL(ring) (RING_SIZE(ring) == (ring)->max_size)
#define RING_WRITE_REMAIN_SIZE(ring) ((ring)->max_size - RING_SIZE(ring))
#define RING_READ_FOR_EACH(_sz, _seg, _ring) \
for (ring_read_prepare(_sz, &(_seg), _ring), \
_ring_segment_prepare((_ring)->read, &(_seg), (_ring)); \
(_seg).sz > 0; \
_ring_read_commit(&(_seg), (_ring)), _ring_segment_prepare((_ring)->read, \
&(_seg), (_ring)))
#define RING_READ_ALL_FOR_EACH(seg, ring) RING_READ_FOR_EACH((ring)->max_size, seg, ring)
#define RING_READ_FOR_EACH_ITEM(_sz, _seg, _ring) \
for (ring_read_prepare(_sz, &(_seg), _ring), \
_ring_segment_prepare_item((_ring)->read, &(_seg), (_ring)); \
(_seg).sz > 0; \
_ring_read_commit(&(_seg), (_ring)), _ring_segment_prepare_item((_ring)->read, \
&(_seg), (_ring)))
#define RING_WRITE_FOR_EACH(_sz, _seg, _ring) \
for (ring_write_prepare(_sz, &(_seg), _ring),\
_ring_segment_prepare((_ring)->write, &(_seg), (_ring)); \
(_seg).sz > 0; \
_ring_write_commit(&(_seg), (_ring)), _ring_segment_prepare((_ring)->write, \
&(_seg), (_ring)))
#define RING_OVERWRITE_FOR_EACH(_sz, _seg, _ring) \
for (ring_overwrite_prepare(_sz, &(_seg), _ring), \
_ring_segment_prepare((_ring)->write, &(_seg), (_ring)); \
(_seg).sz > 0; \
_ring_write_commit(&(_seg), (_ring)), _ring_segment_prepare((_ring)->write, \
&(_seg), (_ring)))
void ring_dump(const char *title, struct ring *ring);
void ring_dump_segment(const char *title, struct ring_segment *seg);
/* ring Buffer Internal API */
void _ring_segment_prepare(unsigned int from, struct ring_segment *seg, struct ring *ring);
void _ring_segment_prepare_item(unsigned int from, struct ring_segment *seg, struct ring *ring);
void _ring_read_commit(struct ring_segment *seg, struct ring *ring);
void _ring_write_commit(struct ring_segment *seg, struct ring *ring);
#endif

716
package/mtk/drivers/conninfra/src/base/msg_thread.c
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@ -1,716 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include <linux/delay.h>
#include "msg_thread.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
static void msg_opq_dump(const char *qName, struct msg_op_q *op_q);
static void _msg_opq_dump(const char *qName, struct msg_op_q *op_q);
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#define MSG_OP_SIZE(prb) ((prb)->size)
#define MSG_OP_MASK(prb) (MSG_OP_SIZE(prb) - 1)
#define MSG_OP_COUNT(prb) ((prb)->write - (prb)->read)
#define MSG_OP_FULL(prb) (MSG_OP_COUNT(prb) >= MSG_OP_SIZE(prb))
#define MSG_OP_EMPTY(prb) ((prb)->write == (prb)->read)
#define MSG_OP_INIT(prb, qsize) \
do { \
(prb)->read = (prb)->write = 0; \
(prb)->size = (qsize); \
} while (0)
#define MSG_OP_PUT(prb, value) \
do { \
if (!MSG_OP_FULL(prb)) { \
(prb)->queue[(prb)->write & MSG_OP_MASK(prb)] = value; \
++((prb)->write); \
} \
else { \
pr_warn("Message queue is full.\n"); \
} \
} while (0)
#define MSG_OP_GET(prb, value) \
do { \
if (!MSG_OP_EMPTY(prb)) { \
value = (prb)->queue[(prb)->read & MSG_OP_MASK(prb)]; \
++((prb)->read); \
if (MSG_OP_EMPTY(prb)) { \
(prb)->read = (prb)->write = 0; \
} \
} \
else { \
value = NULL; \
pr_warn("Message queue is empty.\n"); \
} \
} while (0)
#if defined(CONFIG_MTK_ENG_BUILD) || defined(CONFIG_MT_ENG_BUILD)
static bool msg_evt_opq_has_op(struct msg_op_q *op_q, struct msg_op *op)
{
unsigned int rd;
unsigned int wt;
struct msg_op *tmp_op;
rd = op_q->read;
wt = op_q->write;
while (rd != wt) {
tmp_op = op_q->queue[rd & MSG_OP_MASK(op_q)];
if (op == tmp_op)
return true;
rd++;
}
return false;
}
#endif
/*
* Utility functions
*/
static int msg_evt_put_op_to_q(struct msg_op_q *op_q, struct msg_op *op)
{
int ret;
if (!op_q || !op) {
pr_err("invalid input param: pOpQ(0x%p), pLxOp(0x%p)\n", op_q, op);
return -1;
}
ret = osal_lock_sleepable_lock(&op_q->lock);
if (ret) {
pr_warn("osal_lock_sleepable_lock iRet(%d)\n", ret);
return -2;
}
#if defined(CONFIG_MTK_ENG_BUILD) || defined(CONFIG_MT_ENG_BUILD)
if (msg_evt_opq_has_op(op_q, op)) {
pr_err("Op(%p) already exists in queue(%p)\n", op, op_q);
ret = -3;
}
#endif
/* acquire lock success */
if (!MSG_OP_FULL(op_q))
MSG_OP_PUT(op_q, op);
else {
pr_warn("MSG_OP_FULL(%p -> %p)\n", op, op_q);
ret = -4;
}
osal_unlock_sleepable_lock(&op_q->lock);
if (ret) {
//osal_opq_dump("FreeOpQ", &g_conninfra_ctx.rFreeOpQ);
//osal_opq_dump("ActiveOpQ", &g_conninfra_ctx.rActiveOpQ);
return ret;
}
return 0;
}
/*
* Utility functions
*/
static struct msg_op *msg_evt_get_op_from_q(struct msg_op_q *op_q)
{
struct msg_op *op;
int ret;
if (op_q == NULL) {
pr_err("pOpQ = NULL\n");
return NULL;
}
ret = osal_lock_sleepable_lock(&op_q->lock);
if (ret) {
pr_err("osal_lock_sleepable_lock iRet(%d)\n", ret);
return NULL;
}
/* acquire lock success */
MSG_OP_GET(op_q, op);
osal_unlock_sleepable_lock(&op_q->lock);
if (op == NULL) {
pr_warn("MSG_OP_GET(%p) return NULL\n", op_q);
//osal_opq_dump("FreeOpQ", &g_conninfra_ctx.rFreeOpQ);
//osal_opq_dump("ActiveOpQ", &g_conninfra_ctx.rActiveOpQ);
}
return op;
}
static void _msg_opq_dump(const char *qName, struct msg_op_q *op_q)
{
/* Line format:
* [LogicalIdx(PhysicalIdx)]Address:OpId(Ref)(Result)-Info-OpData0,OpData1,OpData2,OpData3,OpData5_
* [LogicalIdx] max 10+2=12 chars (decimal)
* (PhysicalIdx) max 10+2=12 chars (decimal)
* Address: max 16+1=17 chars (hex)
* OpId max 10 chars (decimal)
* (Ref) max 2+2=4 chars (should only be 1 digit, reserve 2 in case of negative number)
* (Result) max 11+2=13 chars (signed decimal)
* -Info- max 8+2=10 chars (hex)
* OpData, max 16+1=17 chars (hex)
*/
#define OPQ_DUMP_OP_PER_LINE 1
#define OPQ_DUMP_OPDATA_PER_OP 6
#define OPQ_DUMP_OP_BUF_SIZE (12 + 12 + 17 + 10 + 4 + 13 + 10 + (17 * (OPQ_DUMP_OPDATA_PER_OP)) + 1)
#define OPQ_DUMP_LINE_BUF_SIZE ((OPQ_DUMP_OP_BUF_SIZE * OPQ_DUMP_OP_PER_LINE) + 1)
unsigned int rd;
unsigned int wt;
unsigned int idx = 0;
unsigned int op_data_idx;
unsigned int buf_idx;
int printed;
struct msg_op *op;
char buf[OPQ_DUMP_LINE_BUF_SIZE];
rd = op_q->read;
wt = op_q->write;
pr_info("%s(%p), sz:%u/%u, rd:%u, wt:%u\n",
qName, op_q, RB_COUNT(op_q), RB_SIZE(op_q), rd, wt);
while (rd != wt && idx < RB_SIZE(op_q)) {
buf_idx = idx % OPQ_DUMP_OP_PER_LINE;
op = op_q->queue[rd & RB_MASK(op_q)];
if (buf_idx == 0) {
printed = 0;
buf[0] = 0;
}
if (op) {
printed += snprintf(buf + printed, OPQ_DUMP_LINE_BUF_SIZE - printed,
"[%u(%u)]%p:%u(%d)(%d)-%u-",
idx,
(rd & RB_MASK(op_q)),
op,
op->op.op_id,
atomic_read(&op->ref_count),
op->result,
op->op.info_bit);
for (op_data_idx = 0; op_data_idx < OPQ_DUMP_OPDATA_PER_OP; op_data_idx++)
printed += snprintf(buf + printed, OPQ_DUMP_LINE_BUF_SIZE - printed,
"%zx,", op->op.op_data[op_data_idx]);
buf[printed-1] = ' ';
} else {
printed += snprintf(buf + printed, OPQ_DUMP_LINE_BUF_SIZE - printed,
"[%u(%u)]%p ", idx, (rd & RB_MASK(op_q)), op);
}
buf[printed++] = ' ';
if (buf_idx == OPQ_DUMP_OP_PER_LINE - 1 || rd == wt - 1) {
buf[printed - 1] = 0;
pr_info("%s\n", buf);
}
rd++;
idx++;
}
}
void msg_opq_dump(const char *qName, struct msg_op_q *op_q)
{
int err;
err = osal_lock_sleepable_lock(&op_q->lock);
if (err) {
pr_info("Failed to lock queue (%d)\n", err);
return;
}
_msg_opq_dump(qName, op_q);
osal_unlock_sleepable_lock(&op_q->lock);
}
/*
* msg_evt_thread API
*/
int msg_evt_put_op_to_free_queue(struct msg_thread_ctx *ctx, struct msg_op *op)
{
if (msg_evt_put_op_to_q(&ctx->free_op_q, op))
return -1;
return 0;
}
struct msg_op *msg_evt_get_free_op(struct msg_thread_ctx *ctx)
{
struct msg_op *op = NULL;
if (ctx == NULL) {
pr_warn("ctx is null.\n");
return op;
}
op = msg_evt_get_op_from_q(&ctx->free_op_q);
if (op)
osal_memset(op, 0, osal_sizeof(struct msg_op));
return op;
}
int msg_evt_put_op_to_active(struct msg_thread_ctx *ctx, struct msg_op *op)
{
P_OSAL_SIGNAL signal = NULL;
int wait_ret = -1;
int ret = 0;
do {
if (!ctx || !op) {
pr_err("msg_thread_ctx(0x%p), op(0x%p)\n", ctx, op);
break;
}
signal = &op->signal;
if (signal->timeoutValue) {
op->result = -9;
osal_signal_init(signal);
atomic_set(&op->ref_count, 1);
} else
atomic_set(&op->ref_count, 0);
/* Increment ref_count by 1 as wmtd thread will hold a reference also,
* this must be done here instead of on target thread, because
* target thread might not be scheduled until a much later time,
* allowing current thread to decrement ref_count at the end of function,
* putting op back to free queue before target thread has a chance to process.
*/
atomic_inc(&op->ref_count);
/* put to active Q */
ret = msg_evt_put_op_to_q(&ctx->active_op_q, op);
if (ret) {
pr_warn("put to active queue fail\n");
atomic_dec(&op->ref_count);
break;
}
/* wake up conninfra_cored */
osal_trigger_event(&ctx->evt);
if (signal->timeoutValue == 0) {
//ret = -1;
/* Not set timeout, don't wait */
/* pr_info("[%s] timeout is zero", __func__);*/
break;
}
/* check result */
wait_ret = osal_wait_for_signal_timeout(signal, &ctx->thread);
/*pr_info("osal_wait_for_signal_timeout:%d result=[%d]\n",
wait_ret, op->result);*/
if (wait_ret == 0)
pr_warn("opId(%d) completion timeout\n", op->op.op_id);
else if (op->result)
pr_info("opId(%d) result:%d\n",
op->op.op_id, op->result);
/* op completes, check result */
ret = op->result;
} while (0);
if (op != NULL && signal != NULL && signal->timeoutValue &&
atomic_dec_and_test(&op->ref_count)) {
/* put Op back to freeQ */
msg_evt_put_op_to_free_queue(ctx, op);
}
return ret;
}
int msg_thread_send(struct msg_thread_ctx *ctx, int opid)
{
return msg_thread_send_2(ctx, opid, 0, 0);
}
int msg_thread_send_1(struct msg_thread_ctx *ctx, int opid,
size_t param1)
{
return msg_thread_send_2(ctx, opid, param1, 0);
}
int msg_thread_send_2(struct msg_thread_ctx *ctx, int opid,
size_t param1, size_t param2)
{
struct msg_op *op = NULL;
P_OSAL_SIGNAL signal;
int ret;
op = msg_evt_get_free_op(ctx);
if (!op) {
pr_err("[%s] can't get free op\n", __func__);
return -1;
}
op->op.op_id = opid;
op->op.op_data[0] = param1;
op->op.op_data[1] = param2;
signal = &op->signal;
//signal->timeoutValue = timeout > 0 ? timeout : MSG_OP_TIMEOUT;
signal->timeoutValue = 0;
ret = msg_evt_put_op_to_active(ctx, op);
return ret;
}
int msg_thread_send_wait(struct msg_thread_ctx *ctx, int opid,
int timeout)
{
return msg_thread_send_wait_3(ctx, opid, timeout, 0, 0, 0);
}
int msg_thread_send_wait_1(struct msg_thread_ctx *ctx,
int opid, int timeout,
size_t param1)
{
return msg_thread_send_wait_3(ctx, opid, timeout, param1, 0, 0);
}
int msg_thread_send_wait_2(struct msg_thread_ctx *ctx,
int opid, int timeout,
size_t param1,
size_t param2)
{
return msg_thread_send_wait_3(ctx, opid, timeout, param1, param2, 0);
}
int msg_thread_send_wait_3(struct msg_thread_ctx *ctx,
int opid, int timeout,
size_t param1,
size_t param2,
size_t param3)
{
struct msg_op *op = NULL;
P_OSAL_SIGNAL signal;
int ret;
op = msg_evt_get_free_op(ctx);
if (!op) {
pr_err("can't get free op for 0x%x\n", opid);
return -1;
}
op->op.op_id = opid;
op->op.op_data[0] = param1;
op->op.op_data[1] = param2;
op->op.op_data[2] = param3;
signal = &op->signal;
signal->timeoutValue = timeout > 0 ? timeout : MSG_OP_TIMEOUT;
ret = msg_evt_put_op_to_active(ctx, op);
return ret;
}
void msg_op_history_save(struct osal_op_history *log_history, struct msg_op *op)
{
struct osal_op_history_entry *entry = NULL;
struct ring_segment seg;
int index;
unsigned long long sec = 0;
unsigned long usec = 0;
unsigned long flags;
if (log_history->queue == NULL)
return;
osal_get_local_time(&sec, &usec);
spin_lock_irqsave(&(log_history->lock), flags);
RING_OVERWRITE_FOR_EACH(1, seg, &log_history->ring_buffer) {
index = seg.ring_pt - log_history->ring_buffer.base;
entry = &log_history->queue[index];
}
if (entry == NULL) {
pr_info("Entry is null, size %d\n",
RING_SIZE(&log_history->ring_buffer));
spin_unlock_irqrestore(&(log_history->lock), flags);
return;
}
entry->opbuf_address = op;
entry->op_id = op->op.op_id;
entry->opbuf_ref_count = atomic_read(&op->ref_count);
entry->op_info_bit = op->op.info_bit;
entry->param_0 = op->op.op_data[0];
entry->param_1 = op->op.op_data[1];
entry->param_2 = op->op.op_data[2];
entry->param_3 = op->op.op_data[3];
entry->ts = sec;
entry->usec = usec;
spin_unlock_irqrestore(&(log_history->lock), flags);
}
unsigned int msg_evt_wait_event_checker(P_OSAL_THREAD thread)
{
struct msg_thread_ctx *ctx = NULL;
if (thread) {
ctx = (struct msg_thread_ctx *) (thread->pThreadData);
return !MSG_OP_EMPTY(&ctx->active_op_q);
}
return 0;
}
int msg_evt_set_current_op(struct msg_thread_ctx *ctx, struct msg_op *op)
{
ctx->cur_op = op;
return 0;
}
int msg_evt_opid_handler(struct msg_thread_ctx *ctx, struct msg_op_data *op)
{
int opid, ret;
/*sanity check */
if (op == NULL) {
pr_warn("null op\n");
return -1;
}
if (ctx == NULL) {
pr_warn("null evt thread ctx\n");
return -2;
}
opid = op->op_id;
if (opid >= ctx->op_func_size) {
pr_err("msg_evt_thread invalid OPID(%d)\n", opid);
return -3;
}
if (ctx->op_func[opid] == NULL) {
pr_err("null handler (%d)\n", opid);
return -4;
}
ret = (*(ctx->op_func[opid])) (op);
return ret;
}
static int msg_evt_thread(void *pvData)
{
struct msg_thread_ctx *ctx = (struct msg_thread_ctx *)pvData;
P_OSAL_EVENT evt = NULL;
struct msg_op *op;
int ret;
if (ctx == NULL) {
pr_err("msg_evt_thread (NULL)\n");
return -1;
}
evt = &(ctx->evt);
for (;;) {
op = NULL;
evt->timeoutValue = 0;
osal_thread_wait_for_event(&ctx->thread, evt, msg_evt_wait_event_checker);
if (osal_thread_should_stop(&ctx->thread)) {
pr_info("msg_evt_thread thread should stop now...\n");
/* TODO: clean up active opQ */
break;
}
/* get Op from activeQ */
op = msg_evt_get_op_from_q(&ctx->active_op_q);
if (!op) {
pr_warn("get op from activeQ fail\n");
continue;
}
/* TODO: save op history */
msg_op_history_save(&ctx->op_history, op);
msg_evt_set_current_op(ctx, op);
ret = msg_evt_opid_handler(ctx, &op->op);
msg_evt_set_current_op(ctx, NULL);
if (ret)
pr_warn("opid (0x%x) failed, ret(%d)\n",
op->op.op_id, ret);
if (atomic_dec_and_test(&op->ref_count)) {
/* msg_evt_free_op(ctx) */
msg_evt_put_op_to_free_queue(ctx, op);
} else if (op->signal.timeoutValue) {
op->result = ret;
osal_raise_signal(&op->signal);
}
}
pr_debug("msg evt thread exists\n");
return 0;
}
int msg_thread_dump(struct msg_thread_ctx *ctx)
{
P_OSAL_THREAD p_thread;
struct msg_op *cur_op;
if (ctx == NULL) {
pr_err("get NULL input\n");
return 0;
}
p_thread = &ctx->thread;
pr_info("Dump msg_thread_ctx: %s\n", p_thread->threadName);
cur_op = ctx->cur_op;
if (cur_op) {
pr_info("cur_op: %x(%x)-%zx,%zx,%zx,%zx\n",
cur_op->op.op_id, cur_op->op.info_bit,
cur_op->op.op_data[0], cur_op->op.op_data[1],
cur_op->op.op_data[2], cur_op->op.op_data[3]);
}
osal_dump_thread_state(p_thread->threadName);
osal_op_history_print(&(ctx->op_history), p_thread->threadName);
msg_opq_dump("ActiveOpQ", &ctx->active_op_q);
return 0;
}
int msg_thread_init(struct msg_thread_ctx *ctx,
const char *thread_name, const msg_opid_func *funcs,
int op_size)
{
int r = 0, i;
P_OSAL_THREAD p_thread;
osal_memset(ctx, 0, sizeof(struct msg_thread_ctx));
ctx->op_func = funcs;
ctx->op_func_size = op_size;
/* init thread inst */
p_thread = &ctx->thread;
osal_strncpy(p_thread->threadName, thread_name,
sizeof(p_thread->threadName));
p_thread->pThreadData = (void *) ctx;
p_thread->pThreadFunc = (void *) msg_evt_thread;
r = osal_thread_create(p_thread);
if (r) {
pr_err("osal_thread_create(0x%p) fail(%d)\n", p_thread, r);
return -1;
}
osal_event_init(&ctx->evt);
osal_sleepable_lock_init(&ctx->active_op_q.lock);
osal_sleepable_lock_init(&ctx->free_op_q.lock);
/* Initialize op queue */
MSG_OP_INIT(&ctx->free_op_q, MSG_THREAD_OP_BUF_SIZE);
MSG_OP_INIT(&ctx->active_op_q, MSG_THREAD_OP_BUF_SIZE);
/* Put all to free Q */
for (i = 0; i < MSG_THREAD_OP_BUF_SIZE; i++) {
osal_signal_init(&(ctx->op_q_inst[i].signal));
msg_evt_put_op_to_free_queue(ctx, &(ctx->op_q_inst[i]));
}
osal_op_history_init(&ctx->op_history, 16);
r = osal_thread_run(p_thread);
if (r) {
pr_err("osal_thread_run(evt_thread 0x%p) fail(%d)\n",
p_thread, r);
return -2;
}
return r;
}
int msg_thread_deinit(struct msg_thread_ctx *ctx)
{
int r, i;
P_OSAL_THREAD p_thraed = &ctx->thread;
r = osal_thread_stop(p_thraed);
if (r) {
pr_err("osal_thread_stop(0x%p) fail(%d)\n", p_thraed, r);
return -1;
}
for (i = 0; i < MSG_THREAD_OP_BUF_SIZE; i++)
osal_signal_deinit(&(ctx->op_q_inst[i].signal));
osal_sleepable_lock_deinit(&ctx->free_op_q.lock);
osal_sleepable_lock_deinit(&ctx->active_op_q.lock);
r = osal_thread_destroy(p_thraed);
if (r) {
pr_err("osal_thread_stop(0x%p) fail(%d)\n", p_thraed, r);
return -2;
}
osal_memset(ctx, 0, sizeof(struct msg_thread_ctx));
pr_debug("[%s] DONE\n", __func__);
return 0;
}

1595
package/mtk/drivers/conninfra/src/base/osal.c
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File diff suppressed because it is too large Load Diff

150
package/mtk/drivers/conninfra/src/base/ring.c
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@ -1,150 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
#include "ring.h"
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/bug.h>
void ring_init(void *base, unsigned int max_size, unsigned int read,
unsigned int write, struct ring *ring)
{
WARN_ON(!base);
/* making sure max_size is power of 2 */
WARN_ON(!max_size || (max_size & (max_size - 1)));
/* making sure write largger than read */
WARN_ON(read > write);
ring->base = base;
ring->read = read;
ring->write = write;
ring->max_size = max_size;
}
void ring_dump(const char *title, struct ring *ring)
{
pr_info("[%s] ring:{write=%d, read=%d, max_size=%d}\n",
title, ring->write, ring->read, ring->max_size);
}
void ring_dump_segment(const char *title, struct ring_segment *seg)
{
pr_info("[%s] seg:{ring_pt=0x%p, data_pos=%d, sz=%d, remain=%d}\n",
title, seg->ring_pt, seg->data_pos,
seg->sz, seg->remain);
}
/*
* Function prepares the ring_segment and
* returns the number of valid bytes for read.
*/
unsigned int ring_read_prepare(unsigned int sz,
struct ring_segment *seg,
struct ring *ring)
{
unsigned int wt = ring->write;
unsigned int rd = ring->read;
memset(seg, 0, sizeof(struct ring_segment));
if (sz > wt - rd)
sz = wt - rd;
seg->remain = sz;
/* ring_dump(__func__, ring); */
/* ring_dump_segment(__func__, seg); */
return seg->remain;
}
/*
* Function prepares the ring_segment and
* returns the number of bytes available for write.
*/
unsigned int ring_write_prepare(unsigned int sz,
struct ring_segment *seg,
struct ring *ring)
{
unsigned int wt = ring->write;
unsigned int rd = ring->read;
memset(seg, 0, sizeof(struct ring_segment));
if (sz > ring->max_size - (wt - rd))
sz = ring->max_size - (wt - rd);
seg->remain = sz;
/* ring_dump(__func__, ring); */
/* ring_dump_segment(__func__, seg); */
return seg->remain;
}
unsigned int ring_overwrite_prepare(unsigned int sz, struct ring_segment *seg,
struct ring *ring)
{
unsigned int wt = ring->write;
unsigned int rd = ring->read;
memset(seg, 0, sizeof(struct ring_segment));
if (sz > ring->max_size - (wt - rd))
ring->read += sz - (ring->max_size - (wt - rd));
seg->remain = sz;
/* ring_dump(__func__, ring); */
/* ring_dump_segment(__func__, seg); */
return seg->remain;
}
void __ring_segment_prepare(unsigned int from, unsigned int sz,
struct ring_segment *seg,
struct ring *ring)
{
unsigned int ring_pos = from & (ring->max_size - 1);
seg->ring_pt = ring->base + ring_pos;
seg->data_pos = (seg->sz ? seg->data_pos + seg->sz : 0);
if (ring_pos + sz <= ring->max_size)
seg->sz = sz;
else
seg->sz = ring->max_size - ring_pos;
seg->remain -= seg->sz;
/* ring_dump(__func__, ring); */
/* ring_dump_segment(__func__, seg); */
}
void _ring_segment_prepare(unsigned int from,
struct ring_segment *seg,
struct ring *ring)
{
__ring_segment_prepare(from, seg->remain, seg, ring);
}
void _ring_segment_prepare_item(unsigned int from,
struct ring_segment *seg,
struct ring *ring)
{
unsigned int size;
size = (seg->remain ? 1 : 0);
__ring_segment_prepare(from, size, seg, ring);
}
void _ring_read_commit(struct ring_segment *seg, struct ring *ring)
{
ring->read += seg->sz;
/* ring_dump(__func__, ring); */
/* ring_dump_segment(__func__, seg); */
}
void _ring_write_commit(struct ring_segment *seg, struct ring *ring)
{
ring->write += seg->sz;
/* ring_dump(__func__, ring); */
/* ring_dump_segment(__func__, seg); */
}

1244
package/mtk/drivers/conninfra/src/core/conninfra_core.c
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File diff suppressed because it is too large Load Diff

193
package/mtk/drivers/conninfra/src/core/include/conninfra_core.h
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@ -1,193 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _CONNINFRA_CORE_H_
#define _CONNINFRA_CORE_H_
#include <linux/semaphore.h>
#include <linux/platform_device.h>
#include <linux/workqueue.h>
#include <linux/time.h>
#include "osal.h"
#include "msg_thread.h"
#include "conninfra.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
#define CHIP_RST_REASON_MAX_LEN 128
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
typedef enum _ENUM_DRV_STS_ {
DRV_STS_POWER_OFF = 0, /* initial state */
DRV_STS_POWER_ON = 1, /* powered on */
DRV_STS_MAX
} ENUM_DRV_STS, *P_ENUM_DRV_STS;
enum chip_rst_status {
CHIP_RST_NONE = 0,
CHIP_RST_START = 1,
CHIP_RST_PRE_CB = 2,
CHIP_RST_RESET = 3,
CHIP_RST_POST_CB = 4,
CHIP_RST_DONE = 5
};
struct subsys_drv_inst {
ENUM_DRV_STS drv_status; /* Controlled driver status */
unsigned int rst_state;
struct sub_drv_ops_cb ops_cb;
struct msg_thread_ctx msg_ctx;
};
/*
* state of conninfra
*
*/
struct conninfra_ctx {
ENUM_DRV_STS infra_drv_status;
struct subsys_drv_inst drv_inst[CONNDRV_TYPE_MAX];
/*struct spinlock infra_lock;*/
spinlock_t infra_lock;
OSAL_SLEEPABLE_LOCK core_lock;
/* chip reset */
enum chip_rst_status rst_status;
spinlock_t rst_lock;
struct semaphore rst_sema;
atomic_t rst_state;
enum consys_drv_type trg_drv;
char trg_reason[CHIP_RST_REASON_MAX_LEN];
struct msg_thread_ctx msg_ctx;
struct msg_thread_ctx cb_ctx;
unsigned int hw_ver;
unsigned int fw_ver;
unsigned int ip_ver;
};
//typedef enum _ENUM_CONNINFRA_CORE_OPID_T {
typedef enum {
CONNINFRA_OPID_PWR_ON = 0,
CONNINFRA_OPID_PWR_OFF = 1,
CONNINFRA_OPID_RFSPI_READ = 2,
CONNINFRA_OPID_RFSPI_WRITE = 3,
CONNINFRA_OPID_ADIE_TOP_CK_EN_ON = 4,
CONNINFRA_OPID_ADIE_TOP_CK_EN_OFF = 5,
CONNINFRA_OPID_SPI_CLOCK_SWITCH = 6,
CONNINFRA_OPID_FORCE_CONNINFRA_WAKUP = 7,
CONNINFRA_OPID_FORCE_CONNINFRA_SLEEP = 8,
CONNINFRA_OPID_DUMP_POWER_STATE = 9,
CONNINFRA_OPID_MAX
} conninfra_core_opid;
/* For the operation which may callback subsys driver */
typedef enum {
CONNINFRA_CB_OPID_CHIP_RST = 0,
CONNINFRA_CB_OPID_MAX
} conninfra_core_cb_opid;
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
extern int conninfra_core_init(void);
extern int conninfra_core_deinit(void);
int conninfra_core_power_on(enum consys_drv_type type);
int conninfra_core_power_off(enum consys_drv_type type);
int conninfra_core_lock_rst(void);
int conninfra_core_unlock_rst(void);
int conninfra_core_trg_chip_rst(enum consys_drv_type drv, char *reason);
int conninfra_core_subsys_ops_reg(enum consys_drv_type type, struct sub_drv_ops_cb *cb);
int conninfra_core_subsys_ops_unreg(enum consys_drv_type type);
/* reg control */
/* NOTE: NOT thread-safe
* return value
* 1 : Yes, 0: NO
*/
int conninfra_core_reg_readable(void);
int conninfra_core_reg_readable_no_lock(void);
int conninfra_core_is_bus_hang(void);
int conninfra_core_is_consys_reg(phys_addr_t addr);
int conninfra_core_reg_read(unsigned long address, unsigned int *value, unsigned int mask);
int conninfra_core_reg_write(unsigned long address, unsigned int value, unsigned int mask);
int conninfra_core_is_rst_locking(void);
int conninfra_core_spi_read(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data);
int conninfra_core_spi_write(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data);
int conninfra_core_adie_top_ck_en_on(enum consys_drv_type type);
int conninfra_core_adie_top_ck_en_off(enum consys_drv_type type);
int conninfra_core_force_conninfra_wakeup(void);
int conninfra_core_force_conninfra_sleep(void);
int conninfra_core_spi_clock_switch(enum connsys_spi_speed_type type);
int conninfra_core_dump_power_state(void);
int conninfra_core_pmic_event_cb(unsigned int, unsigned int);
int conninfra_core_debug_dump(void);
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#endif /* _CONNINFRA_CORE_H_ */

216
package/mtk/drivers/conninfra/src/include/conninfra.h
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@ -1,216 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _CONNINFRA_H_
#define _CONNINFRA_H_
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
#define AIDE_NUM_MAX 2
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
enum consys_drv_type {
CONNDRV_TYPE_BT = 0,
CONNDRV_TYPE_FM = 1,
CONNDRV_TYPE_GPS = 2,
CONNDRV_TYPE_WIFI = 3,
CONNDRV_TYPE_CONNINFRA = 4,
CONNDRV_TYPE_MAX
};
/* HW-specific, need sync with FW. DO NOT MODIFY */
enum sys_spi_subsystem
{
SYS_SPI_WF1 = 0x00,
SYS_SPI_WF = 0x01,
SYS_SPI_BT = 0x02,
SYS_SPI_FM = 0x03,
SYS_SPI_GPS = 0x04,
SYS_SPI_TOP = 0x05,
SYS_SPI_WF2 = 0x06,
SYS_SPI_WF3 = 0x07,
SYS_SPI_2ND_ADIE_WF1 = 0x10,
SYS_SPI_2ND_ADIE_WF = 0x11,
SYS_SPI_2ND_ADIE_BT = 0x12,
SYS_SPI_2ND_ADIE_FM = 0x13,
SYS_SPI_2ND_ADIE_GPS = 0x14,
SYS_SPI_2ND_ADIE_TOP = 0x15,
SYS_SPI_2ND_ADIE_WF2 = 0x16,
SYS_SPI_2ND_ADIE_WF3 = 0x17,
SYS_SPI_MAX
};
enum connsys_spi_speed_type {
CONNSYS_SPI_SPEED_26M,
CONNSYS_SPI_SPEED_64M,
CONNSYS_SPI_SPEED_MAX
};
/* Conninfra driver allocate EMI for FW and WFDAM
* (FW includes: BT, WIFI and their MCU)
* +-----------+ +
* | | |
* | FW | |
* | | |
* +-----------+ v
* | |
* | | FW_WFDMA
* | | ^
* | WFDMA | |
* | | |
* | | |
* +-----------+ +
*
* MCIF region is provided by MD
* +-----------+
* | |
* | |
* | MCIF |
* | |
* +-----------+
*/
enum connsys_emi_type
{
CONNSYS_EMI_FW = 0,
CONNSYS_EMI_MAX,
};
#define CONNINFRA_SPI_OP_FAIL 0x1
#define CONNINFRA_CB_RET_CAL_PASS_POWER_OFF 0x0
#define CONNINFRA_CB_RET_CAL_PASS_POWER_ON 0x2
#define CONNINFRA_CB_RET_CAL_FAIL_POWER_OFF 0x1
#define CONNINFRA_CB_RET_CAL_FAIL_POWER_ON 0x3
#define CONNINFRA_BUS_CLOCK_WPLL 0x1
#define CONNINFRA_BUS_CLOCK_ALL (CONNINFRA_BUS_CLOCK_WPLL)
/* bus hang error define */
#define CONNINFRA_INFRA_BUS_HANG 0x1
#define CONNINFRA_AP2CONN_RX_SLP_PROT_ERR 0x2
#define CONNINFRA_AP2CONN_TX_SLP_PROT_ERR 0x4
#define CONNINFRA_AP2CONN_CLK_ERR 0x8
#define CONNINFRA_INFRA_BUS_HANG_IRQ 0x10
#define CONNINFRA_ERR_RST_ONGOING -0x7788
#define CONNINFRA_ERR_WAKEUP_FAIL -0x5566
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/* SPI clock switch */
int conninfra_spi_clock_switch(enum connsys_spi_speed_type type);
/* A-die top_ck_en control, only for MT6885 */
int conninfra_adie_top_ck_en_on(enum consys_drv_type type);
int conninfra_adie_top_ck_en_off(enum consys_drv_type type);
/* RFSPI */
int conninfra_spi_read(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data);
int conninfra_spi_write(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data);
/* EMI */
void conninfra_get_emi_phy_addr(enum connsys_emi_type type, phys_addr_t* base, unsigned int *size);
/* power on/off */
int conninfra_pwr_on(enum consys_drv_type drv_type);
int conninfra_pwr_off(enum consys_drv_type drv_type);
/* To setup config relative data, ex: debug flag */
void conninfra_config_setup(void);
/*
* 0 : NO hang
* > 0 : HANG!!
* CONNINFRA_ERR_RST_ONGOING: whole chip reset is ongoing
*/
int conninfra_is_bus_hang(void);
/* chip reset
* return:
* <0: error
* =0: triggered
* =1: ongoing
*/
int conninfra_trigger_whole_chip_rst(enum consys_drv_type drv, char *reason);
int conninfra_debug_dump(void);
struct whole_chip_rst_cb {
int (*pre_whole_chip_rst)(enum consys_drv_type drv, char *reason);
int (*post_whole_chip_rst)(void);
};
/* driver state query */
/* VCN control */
/* Thermal */
/* Config */
/* semaphore */
/* calibration */
struct sub_drv_ops_cb {
/* chip reset */
struct whole_chip_rst_cb rst_cb;
};
int conninfra_sub_drv_ops_register(enum consys_drv_type drv_type, struct sub_drv_ops_cb *cb);
int conninfra_sub_drv_ops_unregister(enum consys_drv_type drv_type);
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#endif /* _CONNINFRA_H_ */

663
package/mtk/drivers/conninfra/src/platform/consys_hw.c
View File

@ -1,663 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include <linux/delay.h>
#include <linux/of_device.h>
#include <linux/of_reserved_mem.h>
#include "osal.h"
#include "consys_hw.h"
#include "emi_mng.h"
#include "pmic_mng.h"
#include "consys_reg_mng.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
static int mtk_conninfra_probe(struct platform_device *pdev);
static int mtk_conninfra_remove(struct platform_device *pdev);
static int mtk_conninfra_suspend(struct platform_device *pdev, pm_message_t state);
static int mtk_conninfra_resume(struct platform_device *pdev);
static int consys_hw_init(struct platform_device *pdev);
static int consys_hw_deinit(void);
static int _consys_hw_conninfra_wakeup(void);
static int _consys_hw_conninfra_sleep(void);
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
extern const struct of_device_id apconninfra_of_ids[];
static struct platform_driver mtk_conninfra_dev_drv = {
.probe = mtk_conninfra_probe,
.remove = mtk_conninfra_remove,
.suspend = mtk_conninfra_suspend,
.resume = mtk_conninfra_resume,
.driver = {
.name = "mtk_conninfra",
.owner = THIS_MODULE,
.of_match_table = apconninfra_of_ids,
},
};
struct consys_hw_env conn_hw_env[AIDE_NUM_MAX];
const struct consys_hw_ops_struct *consys_hw_ops;
struct platform_device *g_pdev;
int g_conninfra_wakeup_ref_cnt;
struct work_struct ap_resume_work;
struct conninfra_dev_cb *g_conninfra_dev_cb;
const struct conninfra_plat_data *g_conninfra_plat_data = NULL;
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
struct platform_device *get_consys_device(void)
{
return g_pdev;
}
int consys_hw_get_clock_schematic(void)
{
if (consys_hw_ops->consys_plt_co_clock_type)
return consys_hw_ops->consys_plt_co_clock_type();
else
pr_err("consys_hw_ops->consys_co_clock_type not supported\n");
return -1;
}
unsigned int consys_hw_chipid_get(void)
{
if (g_conninfra_plat_data && g_conninfra_plat_data->chip_id)
return g_conninfra_plat_data->chip_id;
else if (consys_hw_ops->consys_plt_soc_chipid_get)
return consys_hw_ops->consys_plt_soc_chipid_get();
else
pr_err("consys_plt_soc_chipid_get not supported\n");
return 0;
}
unsigned int consys_hw_get_hw_ver(void)
{
if (consys_hw_ops->consys_plt_get_hw_ver)
return consys_hw_ops->consys_plt_get_hw_ver();
return 0;
}
int consys_hw_reg_readable(void)
{
return consys_reg_mng_reg_readable();
}
int consys_hw_is_connsys_reg(phys_addr_t addr)
{
return consys_reg_mng_is_connsys_reg(addr);
}
int consys_hw_is_bus_hang(void)
{
return consys_reg_mng_is_bus_hang();
}
int consys_hw_dump_bus_status(void)
{
return consys_reg_mng_dump_bus_status();
}
int consys_hw_dump_cpupcr(enum conn_dump_cpupcr_type dump_type, int times, unsigned long interval_us)
{
return consys_reg_mng_dump_cpupcr(dump_type, times, interval_us);
}
int consys_hw_pwr_on(unsigned int curr_status, unsigned int on_radio)
{
//unsigned int next_status = (curr_status | (0x1 << on_radio));
/* first power on */
if (curr_status == 0) {
/* POS PART 0:
* Set PMIC to turn on the power that AFE WBG circuit in D-die,
* OSC or crystal component, and A-die need.
*/
if (consys_hw_ops->consys_plt_xtal_ctrl_fast_mode)
consys_hw_ops->consys_plt_xtal_ctrl_fast_mode();
if (consys_hw_ops->consys_plt_connsys_sw_reset_ctrl)
consys_hw_ops->consys_plt_connsys_sw_reset_ctrl(false);
/* POS PART 1:
* 1. Pinmux setting
* 2. Turn on MTCMOS
* 3. Enable AHB bus
*/
if (consys_hw_ops->consys_plt_set_if_pinmux)
consys_hw_ops->consys_plt_set_if_pinmux(true);
udelay(500);
if (consys_hw_ops->consys_plt_tx_rx_bus_slp_prot_ctrl)
consys_hw_ops->consys_plt_tx_rx_bus_slp_prot_ctrl(true);
if (consys_hw_ops->consys_plt_polling_consys_chipid)
consys_hw_ops->consys_plt_polling_consys_chipid();
/* POS PART 2:
* 1. Set connsys EMI mapping
* 2. d_die_cfg
* 3. spi_master_cfg
* 4. a_die_cfg
* 5. afe_wbg_cal
* 6. patch default value
* 7. CONN_INFRA low power setting (srcclken wait time, mtcmos HW ctl...)
*/
if (consys_hw_ops->consys_plt_bus_clock_ctrl)
consys_hw_ops->consys_plt_bus_clock_ctrl(on_radio, CONNINFRA_BUS_CLOCK_ALL);
emi_mng_set_remapping_reg();
emi_mng_set_region_protection();
if (consys_hw_ops->consys_plt_d_die_cfg)
consys_hw_ops->consys_plt_d_die_cfg();
if (consys_hw_ops->consys_plt_conninfra_sysram_hw_ctrl)
consys_hw_ops->consys_plt_conninfra_sysram_hw_ctrl();
if (consys_hw_ops->consys_plt_spi_master_cfg)
consys_hw_ops->consys_plt_spi_master_cfg();
#ifndef CONFIG_FPGA_EARLY_PORTING
if (consys_hw_ops->consys_plt_adie_type_check)
consys_hw_ops->consys_plt_adie_type_check();
if (consys_hw_ops->consys_plt_a_die_cfg)
consys_hw_ops->consys_plt_a_die_cfg();
#endif
if (consys_hw_ops->consys_plt_afe_wbg_cal)
consys_hw_ops->consys_plt_afe_wbg_cal();
if (consys_hw_ops->consys_plt_subsys_pll_initial)
consys_hw_ops->consys_plt_subsys_pll_initial();
if (consys_hw_ops->consys_plt_osc_legacy_mode)
consys_hw_ops->consys_plt_osc_legacy_mode();
#ifndef CONFIG_FPGA_EARLY_PORTING
if (consys_hw_ops->consys_plt_top_pwr_ctrl)
consys_hw_ops->consys_plt_top_pwr_ctrl();
#endif
if (consys_hw_ops->consys_plt_conn_infra_bus_timeout)
consys_hw_ops->consys_plt_conn_infra_bus_timeout();
if (consys_hw_ops->consys_plt_clkgen_wpll_hw_ctrl)
consys_hw_ops->consys_plt_clkgen_wpll_hw_ctrl();
/* POS PART 3:
* 1. A-die low power setting
* 2. bgfsys power on(BT/GPS on)
*/
consys_hw_force_conninfra_wakeup();
#ifndef CONFIG_FPGA_EARLY_PORTING
consys_hw_adie_top_ck_en_on(on_radio);
//consys_hw_adie_top_ck_en_off(on_radio);
#endif
consys_hw_force_conninfra_sleep();
}else {
switch (on_radio) {
case CONNDRV_TYPE_WIFI:
/* Power on WFSYS PART 0:
* 1. wake up conn_infra
* 2. turn on MTCMOS power switch of "wfsys_top_on" and "wfsys_top_off" circuit in D-die ("wfsys_top_off" is turned on by "wfsys_top_on" automatically)
* 3. enable AHB bus(WF2conn/conn2WF)
* 4. downlad CONNSYS EMI code
* 5. patch default value
*/
if (consys_hw_ops->consys_plt_conninfra_wf_wakeup)
consys_hw_ops->consys_plt_conninfra_wf_wakeup();
if (consys_hw_ops->consys_plt_conn_wmcpu_sw_reset)
consys_hw_ops->consys_plt_conn_wmcpu_sw_reset(true);
if (consys_hw_ops->consys_plt_wf_bus_slp_prot_ctrl)
consys_hw_ops->consys_plt_wf_bus_slp_prot_ctrl(false);
if (consys_hw_ops->consys_plt_wfsys_top_on_ctrl)
consys_hw_ops->consys_plt_wfsys_top_on_ctrl(true);
if (consys_hw_ops->consys_plt_wfsys_bus_slp_prot_check)
consys_hw_ops->consys_plt_wfsys_bus_slp_prot_check(true);
if (consys_hw_ops->consys_plt_wfsys_bus_timeout_ctrl)
consys_hw_ops->consys_plt_wfsys_bus_timeout_ctrl();
if (consys_hw_ops->consys_plt_conn_wmcpu_sw_reset)
consys_hw_ops->consys_plt_conn_wmcpu_sw_reset(false);
#ifndef CONFIG_FPGA_EARLY_PORTING
if (consys_hw_ops->consys_plt_conn_wmcpu_idle_loop_check)
consys_hw_ops->consys_plt_conn_wmcpu_idle_loop_check();
if (consys_hw_ops->consys_plt_adie_type_cfg)
consys_hw_ops->consys_plt_adie_type_cfg();
#endif
/* No sleep requiremenct for rebb AP */
#if 0
if (consys_hw_ops->consys_plt_conninfra_wf_sleep)
consys_hw_ops->consys_plt_conninfra_wf_sleep();
#endif
break;
default:
pr_err("Not support type now (on_radio = %d)\n", on_radio);
break;
}
}
return 0;
}
int consys_hw_pwr_off(unsigned int curr_status, unsigned int off_radio)
{
//int ret = 0;
unsigned int next_status = curr_status & ~(0x1 << off_radio);
if (next_status == 0) {
pr_info("Last pwoer off: %d\n", off_radio);
/* Power off CONNSYS PART 0:
* 1. A-die low power setting
*/
consys_hw_force_conninfra_wakeup();
#ifndef CONFIG_FPGA_EARLY_PORTING
//consys_hw_adie_top_ck_en_off(off_radio);
#endif
consys_hw_force_conninfra_sleep();
/* Power off CONNSYS PART 1:
* 1. disable AXI bus
* 2. turn off MTCMOS power switch of "conn_top_on" and "conn_top_off" circuit in D-die
*/
if (consys_hw_ops->consys_plt_tx_rx_bus_slp_prot_ctrl)
consys_hw_ops->consys_plt_tx_rx_bus_slp_prot_ctrl(false);
if (consys_hw_ops->consys_plt_connsys_sw_reset_ctrl)
consys_hw_ops->consys_plt_connsys_sw_reset_ctrl(true);
udelay(1);
} else {
switch (off_radio) {
case CONNDRV_TYPE_WIFI:
/* Power off WFSYS PART 1:
* 1. disable AXI bus(wf2conn/conn2wf)
* 2. turn off MTCMOS power switch of "wf_top_on" and "wf_top_off" circuit in D-die ("wf_top_off" is turned off by "wf_top_on" automatically)
*/
if (consys_hw_ops->consys_plt_conninfra_wf_wakeup)
consys_hw_ops->consys_plt_conninfra_wf_wakeup();
if (consys_hw_ops->consys_plt_wf_bus_slp_prot_ctrl)
consys_hw_ops->consys_plt_wf_bus_slp_prot_ctrl(true);
if (consys_hw_ops->consys_plt_wfsys_bus_slp_prot_check)
consys_hw_ops->consys_plt_wfsys_bus_slp_prot_check(false);
if (consys_hw_ops->consys_plt_wpll_ctrl)
consys_hw_ops->consys_plt_wpll_ctrl(false);
if (consys_hw_ops->consys_plt_wfsys_top_on_ctrl)
consys_hw_ops->consys_plt_wfsys_top_on_ctrl(false);
if (consys_hw_ops->consys_plt_wpll_ctrl)
consys_hw_ops->consys_plt_wpll_ctrl(true);
consys_hw_adie_top_ck_en_off(off_radio);
if (consys_hw_ops->consys_plt_conninfra_wf_req_clr)
consys_hw_ops->consys_plt_conninfra_wf_req_clr();
if (consys_hw_ops->consys_plt_conninfra_wf_sleep)
consys_hw_ops->consys_plt_conninfra_wf_sleep();
break;
default:
consys_hw_force_conninfra_wakeup();
consys_hw_adie_top_ck_en_off(off_radio);
consys_hw_force_conninfra_sleep();
break;
}
}
return 0;
}
int consys_hw_wifi_power_ctl(unsigned int enable)
{
return pmic_mng_wifi_power_ctrl(enable);
}
int consys_hw_bt_power_ctl(unsigned int enable)
{
return pmic_mng_bt_power_ctrl(enable);
}
int consys_hw_gps_power_ctl(unsigned int enable)
{
return pmic_mng_gps_power_ctrl(enable);
}
int consys_hw_fm_power_ctl(unsigned int enable)
{
return pmic_mng_fm_power_ctrl(enable);
}
int consys_hw_dump_power_state(void)
{
if (consys_hw_ops && consys_hw_ops->consys_plt_power_state)
consys_hw_ops->consys_plt_power_state();
return 0;
}
int consys_hw_spi_read(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data)
{
if (consys_hw_ops->consys_plt_spi_read)
return consys_hw_ops->consys_plt_spi_read(subsystem, addr, data);
return -1;
}
int consys_hw_spi_write(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data)
{
if (consys_hw_ops->consys_plt_spi_write)
return consys_hw_ops->consys_plt_spi_write(subsystem, addr, data);
return -1;
}
int consys_hw_adie_top_ck_en_on(enum consys_drv_type type)
{
if (consys_hw_ops->consys_plt_adie_top_ck_en_on_off_ctrl)
return consys_hw_ops->consys_plt_adie_top_ck_en_on_off_ctrl(type, 1);
return -1;
}
int consys_hw_adie_top_ck_en_off(enum consys_drv_type type)
{
if (consys_hw_ops->consys_plt_adie_top_ck_en_on_off_ctrl)
return consys_hw_ops->consys_plt_adie_top_ck_en_on_off_ctrl(type, 0);
return -1;
}
static int _consys_hw_conninfra_wakeup(void)
{
int ref = g_conninfra_wakeup_ref_cnt;
bool wakeup = false, ret;
if (consys_hw_ops->consys_plt_conninfra_wakeup) {
if (g_conninfra_wakeup_ref_cnt == 0) {
ret = consys_hw_ops->consys_plt_conninfra_wakeup();
if (ret) {
pr_err("wakeup fail!! ret=[%d]\n", ret);
return ret;
}
wakeup = true;
}
g_conninfra_wakeup_ref_cnt++;
}
pr_info("conninfra_wakeup refcnt=[%d]->[%d] %s\n",
ref, g_conninfra_wakeup_ref_cnt, (wakeup ? "wakeup!!" : ""));
return 0;
}
static int _consys_hw_conninfra_sleep(void)
{
int ref = g_conninfra_wakeup_ref_cnt;
bool sleep = false;
if (consys_hw_ops->consys_plt_conninfra_sleep &&
--g_conninfra_wakeup_ref_cnt == 0) {
sleep = true;
consys_hw_ops->consys_plt_conninfra_sleep();
}
if (g_conninfra_wakeup_ref_cnt < 0)
g_conninfra_wakeup_ref_cnt = 0;
pr_info("conninfra_sleep refcnt=[%d]->[%d] %s\n",
ref, g_conninfra_wakeup_ref_cnt, (sleep ? "sleep!!" : ""));
return 0;
}
int consys_hw_force_conninfra_wakeup(void)
{
return _consys_hw_conninfra_wakeup();
}
int consys_hw_force_conninfra_sleep(void)
{
return _consys_hw_conninfra_sleep();
}
int consys_hw_spi_clock_switch(enum connsys_spi_speed_type type)
{
if (consys_hw_ops->consys_plt_spi_clock_switch)
return consys_hw_ops->consys_plt_spi_clock_switch(type);
return -1;
}
int consys_hw_pmic_event_cb(unsigned int id, unsigned int event)
{
pmic_mng_event_cb(id, event);
return 0;
}
int mtk_conninfra_probe(struct platform_device *pdev)
{
int ret = -1;
if (pdev)
g_pdev = pdev;
else {
pr_err("pdev is NULL\n");
return -1;
}
g_conninfra_plat_data = (const struct conninfra_plat_data*)of_device_get_match_data(&pdev->dev);
if (g_conninfra_plat_data == NULL) {
pr_err("Get platform data fail.\n");
return -2;
}
if (consys_hw_ops == NULL)
consys_hw_ops = (const struct consys_hw_ops_struct*)g_conninfra_plat_data->hw_ops;
if (consys_hw_ops == NULL) {
pr_err("Get HW op fail\n");
return -3;
}
/* Read device node */
if (consys_reg_mng_init(pdev, g_conninfra_plat_data) != 0) {
pr_err("consys_plt_read_reg_from_dts fail\n");
return -4;
}
if (consys_hw_ops->consys_plt_clk_get_from_dts) {
if (consys_hw_ops->consys_plt_clk_get_from_dts(pdev) != 0) {
pr_err("consys_plt_clk_get_from_dts fail\n");
return -5;
}
}
/* HW operation init */
if (consys_hw_init(pdev) != 0) {
pr_err("consys_hw_init fail\n");
return -6;
}
/* emi mng init */
ret = emi_mng_init(pdev, g_conninfra_plat_data);
if (ret) {
pr_err("emi_mng init fail, %d\n", ret);
return -7;
}
ret = pmic_mng_init(pdev, g_conninfra_dev_cb, g_conninfra_plat_data);
if (ret) {
pr_err("pmic_mng init fail, %d\n", ret);
return -8;
}
return ret;
}
int mtk_conninfra_remove(struct platform_device *pdev)
{
int ret;
ret = pmic_mng_deinit();
pr_info("pmic_mng_deinit ret=%d\n", ret);
ret = emi_mng_deinit();
pr_info("emi_mng_deinit ret=%d\n", ret);
if (consys_hw_ops->consys_plt_clk_detach)
consys_hw_ops->consys_plt_clk_detach();
else
pr_err("consys_plt_clk_detach is null\n");
ret = consys_reg_mng_deinit();
pr_info("consys_reg_mng_deinit ret=%d\n", ret);
ret = consys_hw_deinit();
pr_info("consys_hw_deinit ret=%d\n", ret);
if (g_pdev)
g_pdev = NULL;
return 0;
}
int mtk_conninfra_suspend(struct platform_device *pdev, pm_message_t state)
{
return 0;
}
int mtk_conninfra_resume(struct platform_device *pdev)
{
/* suspend callback is in atomic context, use schedule work to execute STEP */
schedule_work(&ap_resume_work);
return 0;
}
static void consys_hw_ap_resume_handler(struct work_struct *work)
{
if (g_conninfra_dev_cb && g_conninfra_dev_cb->conninfra_resume_cb)
(*g_conninfra_dev_cb->conninfra_resume_cb)();
}
int consys_hw_init(struct platform_device *pdev)
{
int iRet = 0;
if (consys_hw_ops->consys_plt_hw_init)
iRet = consys_hw_ops->consys_plt_hw_init();
return iRet;
}
int consys_hw_deinit(void)
{
return 0;
}
int mtk_conninfra_drv_init(struct conninfra_dev_cb *dev_cb)
{
int iRet = 0;
g_conninfra_dev_cb = dev_cb;
pr_info("Before platform_driver_register\n");
iRet = platform_driver_register(&mtk_conninfra_dev_drv);
if (iRet)
pr_err("Conninfra platform driver registered failed(%d)\n", iRet);
pr_info("After platform_driver_register\n");
INIT_WORK(&ap_resume_work, consys_hw_ap_resume_handler);
return iRet;
}
int mtk_conninfra_drv_deinit(void)
{
platform_driver_unregister(&mtk_conninfra_dev_drv);
g_conninfra_dev_cb = NULL;
return 0;
}

39
package/mtk/drivers/conninfra/src/platform/consys_hw_plat_data.c
View File

@ -1,39 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
#include <linux/of_device.h>
#include "consys_hw.h"
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/* Platform data */
#ifdef CONNINFRA_APSOC_MT7986
extern struct conninfra_plat_data mt7986_plat_data;
const struct of_device_id apconninfra_of_ids[] = {
{
.compatible = "mediatek,mt7986-consys",
.data = (void*)&mt7986_plat_data,
},
{}
};
#endif
#ifdef CONNINFRA_APSOC_MT7981
extern struct conninfra_plat_data mt7981_plat_data;
const struct of_device_id apconninfra_of_ids[] = {
{
.compatible = "mediatek,mt7981-consys",
.data = (void*)&mt7981_plat_data,
},
{}
};
#endif

148
package/mtk/drivers/conninfra/src/platform/consys_reg_mng.c
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@ -1,148 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include "consys_hw.h"
#include "consys_reg_mng.h"
#include "consys_reg_util.h"
const struct consys_reg_mng_ops* g_consys_reg_ops = NULL;
int consys_reg_mng_reg_readable(void)
{
if (g_consys_reg_ops &&
g_consys_reg_ops->consys_reg_mng_check_reable)
return g_consys_reg_ops->consys_reg_mng_check_reable();
return -1;
}
int consys_reg_mng_is_connsys_reg(phys_addr_t addr)
{
if (g_consys_reg_ops &&
g_consys_reg_ops->consys_reg_mng_is_consys_reg)
return g_consys_reg_ops->consys_reg_mng_is_consys_reg(addr);
return -1;
}
int consys_reg_mng_is_bus_hang(void)
{
if (g_consys_reg_ops &&
g_consys_reg_ops->consys_reg_mng_is_bus_hang)
return g_consys_reg_ops->consys_reg_mng_is_bus_hang();
return -1;
}
int consys_reg_mng_dump_bus_status(void)
{
if (g_consys_reg_ops &&
g_consys_reg_ops->consys_reg_mng_dump_bus_status)
return g_consys_reg_ops->consys_reg_mng_dump_bus_status();
return -1;
}
int consys_reg_mng_dump_conninfra_status(void)
{
if (g_consys_reg_ops &&
g_consys_reg_ops->consys_reg_mng_dump_conninfra_status)
return g_consys_reg_ops->consys_reg_mng_dump_conninfra_status();
return -1;
}
int consys_reg_mng_dump_cpupcr(enum conn_dump_cpupcr_type dump_type, int times, unsigned long interval_us)
{
if (g_consys_reg_ops &&
g_consys_reg_ops->consys_reg_mng_dump_cpupcr)
return g_consys_reg_ops->consys_reg_mng_dump_cpupcr(dump_type, times, interval_us);
return -1;
}
int consys_reg_mng_init(struct platform_device *pdev, const struct conninfra_plat_data* plat_data)
{
int ret = 0;
if (g_consys_reg_ops == NULL)
g_consys_reg_ops = (const struct consys_reg_mng_ops*)plat_data->reg_ops;
if (g_consys_reg_ops &&
g_consys_reg_ops->consys_reg_mng_init)
ret = g_consys_reg_ops->consys_reg_mng_init(pdev);
else
ret = EFAULT;
return ret;
}
int consys_reg_mng_deinit(void)
{
if (g_consys_reg_ops&&
g_consys_reg_ops->consys_reg_mng_deinit)
g_consys_reg_ops->consys_reg_mng_deinit();
return 0;
}
int consys_reg_mng_reg_read(unsigned long addr, unsigned int *value, unsigned int mask)
{
void __iomem *vir_addr = NULL;
vir_addr = ioremap_nocache(addr, 0x100);
if (!vir_addr) {
pr_err("ioremap fail\n");
return -1;
}
*value = (unsigned int)CONSYS_REG_READ(vir_addr) & mask;
pr_info("[%x] mask=[%x]\n", *value, mask);
iounmap(vir_addr);
return 0;
}
int consys_reg_mng_reg_write(unsigned long addr, unsigned int value, unsigned int mask)
{
void __iomem *vir_addr = NULL;
vir_addr = ioremap_nocache(addr, 0x100);
if (!vir_addr) {
pr_err("ioremap fail\n");
return -1;
}
CONSYS_REG_WRITE_MASK(vir_addr, value, mask);
iounmap(vir_addr);
return 0;
}
int consys_reg_mng_is_host_csr(unsigned long addr)
{
if (g_consys_reg_ops &&
g_consys_reg_ops->consys_reg_mng_is_host_csr)
return g_consys_reg_ops->consys_reg_mng_is_host_csr(addr);
return -1;
}

158
package/mtk/drivers/conninfra/src/platform/emi_mng.c
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@ -1,158 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#include <linux/of.h>
#include <linux/of_reserved_mem.h>
#include <linux/io.h>
#include <linux/types.h>
#include "osal.h"
#include "consys_hw.h"
#include "emi_mng.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
unsigned long long gConEmiSize = 0;
phys_addr_t gConEmiPhyBase = 0x0;
const struct consys_platform_emi_ops* consys_platform_emi_ops = NULL;
struct consys_emi_addr_info connsys_emi_addr_info = {
.emi_ap_phy_base = 0,
.emi_ap_phy_size = 0,
.fw_emi_size = 0,
};
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
int emi_mng_set_region_protection(void)
{
if (consys_platform_emi_ops &&
consys_platform_emi_ops->consys_ic_emi_set_region_protection)
return consys_platform_emi_ops->consys_ic_emi_set_region_protection();
return -1;
}
int emi_mng_set_remapping_reg(void)
{
if (consys_platform_emi_ops &&
consys_platform_emi_ops->consys_ic_emi_set_remapping_reg)
return consys_platform_emi_ops->consys_ic_emi_set_remapping_reg();
return -1;
}
struct consys_emi_addr_info* emi_mng_get_phy_addr(void)
{
return &connsys_emi_addr_info;
}
int emi_mng_init(struct platform_device *pdev, const struct conninfra_plat_data* plat_data)
{
unsigned int fw_emi_size = 0;
#ifdef CONFIG_CONNINFRA_EMI_SUPPORT
struct device_node *np;
struct reserved_mem *rmem;
np = of_parse_phandle(pdev->dev.of_node, "memory-region", 0);
if (!np) {
pr_info("[%s] memory region not found.\n", __func__);
return -1;
}
rmem = of_reserved_mem_lookup(np);
if (!rmem) {
pr_info("[%s] no memory-region\n", __func__);
return -1;
} else {
gConEmiPhyBase = rmem->base;
gConEmiSize = rmem->size;
}
#else
pr_info("Conninfra not support EMI reservation for %04x\n", plat_data->chip_id);
#endif /* CONFIG_CONNINFRA_EMI_SUPPORT */
if (consys_platform_emi_ops == NULL) {
consys_platform_emi_ops = (const struct consys_platform_emi_ops*)plat_data->platform_emi_ops;
}
if (consys_platform_emi_ops && consys_platform_emi_ops->consys_ic_emi_get_fw_emi_size)
fw_emi_size = consys_platform_emi_ops->consys_ic_emi_get_fw_emi_size();
pr_info("[emi_mng_init] gConEmiPhyBase = [0x%llx] size = [0x%llx] fw size = [0x%x] ops=[%p]\n",
gConEmiPhyBase, gConEmiSize, fw_emi_size, consys_platform_emi_ops);
if (gConEmiPhyBase) {
connsys_emi_addr_info.emi_ap_phy_base = gConEmiPhyBase;
connsys_emi_addr_info.emi_ap_phy_size = gConEmiSize;
connsys_emi_addr_info.fw_emi_size = fw_emi_size;
} else {
pr_err("consys emi memory address gConEmiPhyBase invalid\n");
}
return 0;
}
int emi_mng_deinit(void)
{
return 0;
}

255
package/mtk/drivers/conninfra/src/platform/include/consys_hw.h
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@ -1,255 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_CONSYS_HW_H_
#define _PLATFORM_CONSYS_HW_H_
#include <linux/platform_device.h>
#include "conninfra.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
#define CONN_SEMA_GET_SUCCESS 0
#define CONN_SEMA_GET_FAIL 1
#define CONN_SEMA_TIMEOUT (1*1000) /* 1ms */
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
struct conninfra_dev_cb {
int (*conninfra_suspend_cb) (void);
int (*conninfra_resume_cb) (void);
int (*conninfra_pmic_event_notifier) (unsigned int, unsigned int);
};
typedef int(*CONSYS_PLT_HW_INIT)(void);
typedef int(*CONSYS_PLT_XTAL_CTRL_FAST_MODE)(void);
typedef int(*CONSYS_PLT_CONNSYS_SW_RESET_CTRL)(bool bassert);
typedef void(*CONSYS_PLT_SET_IF_PINMUX)(bool enable);
typedef int(*CONSYS_PLT_TX_RX_BUS_SLP_PROT_CTRL)(bool enable);
typedef int(*CONSYS_PLT_POLLING_CONSYS_CHIPID)(void);
typedef int(*CONSYS_PLT_BUS_CLOCK_CTRL)(enum consys_drv_type drv_type, unsigned int bus_clock);
typedef int(*CONSYS_PLT_D_DIE_CFG)(void);
typedef int(*CONSYS_PLT_CONNINFRA_SYSRAM_HW_CTRL)(void);
typedef int(*CONSYS_PLT_SPI_MASTER_CFG)(void);
typedef int(*CONSYS_PLT_A_DIE_CFG)(void);
typedef int(*CONSYS_PLT_AFE_WBG_CAL)(void);
typedef int(*CONSYS_PLT_SUBSYS_PLL_INITIAL)(void);
typedef int(*CONSYS_PLT_OSC_LEGACY_MODE)(void);
typedef int(*CONSYS_PLT_TOP_PWR_CTRL)(void);
typedef int(*CONSYS_PLT_CONN_INFRA_BUS_TIMEOUT)(void);
typedef int(*CONSYS_PLT_CLKGEN_WPLL_HW_CTRL)(void);
typedef int(*CONSYS_PLT_CONNINFRA_TOP_WAKEUP) (void);
typedef int(*CONSYS_PLT_CONNINFRA_TOP_SLEEP) (void);
typedef int(*CONSYS_PLT_ADIE_TOP_CK_EN_ON_OFF_CTRL)(enum consys_drv_type type, unsigned char on);
typedef int(*CONSYS_PLT_CONNINFRA_WF_WAKEUP) (void);
typedef int(*CONSYS_PLT_CONNINFRA_WF_SLEEP) (void);
typedef int(*CONSYS_PLT_CONN_WMCPU_SW_RESET) (bool bassert);
typedef int(*CONSYS_PLT_WF_BUS_SLP_PROT_CTRL)(bool enable);
typedef int(*CONSYS_PLT_WFSYS_TOP_ON_CTRL) (bool enable);
typedef int(*CONSYS_PLT_WFSYS_BUS_SLP_PROT_CHECK)(bool enable);
typedef int(*CONSYS_PLT_WFSYS_BUS_TIMEOUT_CTRL) (void);
typedef int(*CONSYS_PLT_CONN_WMCPU_IDLE_LOOP_CHECK) (void);
typedef int(*CONSYS_PLT_WPLL_CTRL)(bool enable);
typedef int(*CONSYS_PLT_CONNINFRA_WF_REQ_CLR) (void);
typedef int(*CONSYS_PLT_CLK_GET_FROM_DTS) (struct platform_device *pdev);
typedef int(*CONSYS_PLT_CLK_DETACH) (void);
typedef int(*CONSYS_PLT_CO_CLOCK_TYPE) (void);
typedef unsigned int(*CONSYS_PLT_SOC_CHIPID_GET) (void);
typedef unsigned int(*CONSYS_PLT_GET_HW_VER)(void);
typedef int(*CONSYS_PLT_SPI_READ)(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data);
typedef int(*CONSYS_PLT_SPI_WRITE)(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data);
typedef int(*CONSYS_PLT_SPI_CLOCK_SWITCH)(enum connsys_spi_speed_type type);
typedef int(*CONSYS_PLT_POWER_STATE)(void);
typedef int(*CONSYS_PLT_AIDE_TYPE_CHECK)(void);
typedef int(*CONSYS_PLT_AIDE_TYPE_CFG)(void);
struct consys_hw_ops_struct {
/* HW init */
CONSYS_PLT_HW_INIT consys_plt_hw_init;
/* Power on/off CONNSYS PART (by Conn_infra Driver) */
CONSYS_PLT_XTAL_CTRL_FAST_MODE consys_plt_xtal_ctrl_fast_mode;
CONSYS_PLT_CONNSYS_SW_RESET_CTRL consys_plt_connsys_sw_reset_ctrl;
CONSYS_PLT_SET_IF_PINMUX consys_plt_set_if_pinmux;
CONSYS_PLT_TX_RX_BUS_SLP_PROT_CTRL consys_plt_tx_rx_bus_slp_prot_ctrl;
CONSYS_PLT_POLLING_CONSYS_CHIPID consys_plt_polling_consys_chipid;
CONSYS_PLT_BUS_CLOCK_CTRL consys_plt_bus_clock_ctrl;
CONSYS_PLT_D_DIE_CFG consys_plt_d_die_cfg;
CONSYS_PLT_CONNINFRA_SYSRAM_HW_CTRL consys_plt_conninfra_sysram_hw_ctrl;
CONSYS_PLT_SPI_MASTER_CFG consys_plt_spi_master_cfg;
CONSYS_PLT_A_DIE_CFG consys_plt_a_die_cfg;
CONSYS_PLT_AFE_WBG_CAL consys_plt_afe_wbg_cal;
CONSYS_PLT_SUBSYS_PLL_INITIAL consys_plt_subsys_pll_initial;
CONSYS_PLT_OSC_LEGACY_MODE consys_plt_osc_legacy_mode;
CONSYS_PLT_TOP_PWR_CTRL consys_plt_top_pwr_ctrl;
CONSYS_PLT_CONN_INFRA_BUS_TIMEOUT consys_plt_conn_infra_bus_timeout;
CONSYS_PLT_CLKGEN_WPLL_HW_CTRL consys_plt_clkgen_wpll_hw_ctrl;
CONSYS_PLT_CONNINFRA_TOP_WAKEUP consys_plt_conninfra_wakeup;
CONSYS_PLT_CONNINFRA_TOP_SLEEP consys_plt_conninfra_sleep;
CONSYS_PLT_ADIE_TOP_CK_EN_ON_OFF_CTRL consys_plt_adie_top_ck_en_on_off_ctrl;
CONSYS_PLT_WPLL_CTRL consys_plt_wpll_ctrl;
/* Power on/off WFSYS PART 0 (by WF Driver) */
CONSYS_PLT_CONNINFRA_WF_WAKEUP consys_plt_conninfra_wf_wakeup;
CONSYS_PLT_CONNINFRA_WF_SLEEP consys_plt_conninfra_wf_sleep;
CONSYS_PLT_CONN_WMCPU_SW_RESET consys_plt_conn_wmcpu_sw_reset;
CONSYS_PLT_WF_BUS_SLP_PROT_CTRL consys_plt_wf_bus_slp_prot_ctrl;
CONSYS_PLT_WFSYS_TOP_ON_CTRL consys_plt_wfsys_top_on_ctrl;
CONSYS_PLT_WFSYS_BUS_SLP_PROT_CHECK consys_plt_wfsys_bus_slp_prot_check;
CONSYS_PLT_WFSYS_BUS_TIMEOUT_CTRL consys_plt_wfsys_bus_timeout_ctrl;
CONSYS_PLT_CONN_WMCPU_IDLE_LOOP_CHECK consys_plt_conn_wmcpu_idle_loop_check;
CONSYS_PLT_CONNINFRA_WF_REQ_CLR consys_plt_conninfra_wf_req_clr;
/* load from dts */
CONSYS_PLT_CLK_GET_FROM_DTS consys_plt_clk_get_from_dts;
CONSYS_PLT_CLK_DETACH consys_plt_clk_detach;
/* clock */
CONSYS_PLT_CO_CLOCK_TYPE consys_plt_co_clock_type;
CONSYS_PLT_SOC_CHIPID_GET consys_plt_soc_chipid_get;
/* debug */
CONSYS_PLT_GET_HW_VER consys_plt_get_hw_ver;
/* For SPI operation */
CONSYS_PLT_SPI_READ consys_plt_spi_read;
CONSYS_PLT_SPI_WRITE consys_plt_spi_write;
/* For SPI clock switch */
CONSYS_PLT_SPI_CLOCK_SWITCH consys_plt_spi_clock_switch;
/* power state */
CONSYS_PLT_POWER_STATE consys_plt_power_state;
/* others */
CONSYS_PLT_AIDE_TYPE_CHECK consys_plt_adie_type_check;
CONSYS_PLT_AIDE_TYPE_CFG consys_plt_adie_type_cfg;
};
struct consys_hw_env {
bool valid;
unsigned int adie_hw_version;
unsigned int adie_id;
int is_rc_mode;
};
struct conninfra_plat_data {
const unsigned int chip_id;
const void* hw_ops;
const void* reg_ops;
const void* platform_emi_ops;
const void* platform_pmic_ops;
};
extern struct consys_hw_env conn_hw_env[AIDE_NUM_MAX];
extern struct consys_base_addr conn_reg;
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
int mtk_conninfra_drv_init(struct conninfra_dev_cb *dev_cb);
int mtk_conninfra_drv_deinit(void);
int consys_hw_pwr_on(unsigned int curr_status, unsigned int on_radio);
int consys_hw_pwr_off(unsigned int curr_status, unsigned int off_radio);
int consys_hw_wifi_power_ctl(unsigned int enable);
int consys_hw_bt_power_ctl(unsigned int enable);
int consys_hw_gps_power_ctl(unsigned int enable);
int consys_hw_fm_power_ctl(unsigned int enable);
int consys_hw_pmic_event_cb(unsigned int id, unsigned int event);
unsigned int consys_hw_chipid_get(void);
int consys_hw_get_clock_schematic(void);
unsigned int consys_hw_get_hw_ver(void);
/*******************************************************************************
* tempoary for STEP
********************************************************************************
*/
/*
* return
* 1 : can read
* 0 : can't read
* -1: not consys register
*/
int consys_hw_reg_readable(void);
int consys_hw_is_connsys_reg(phys_addr_t addr);
/*
* 0 means NO hang
* > 0 means hang!!
*/
int consys_hw_is_bus_hang(void);
int consys_hw_dump_bus_status(void);
int consys_hw_spi_read(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data);
int consys_hw_spi_write(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data);
int consys_hw_adie_top_ck_en_on(enum consys_drv_type type);
int consys_hw_adie_top_ck_en_off(enum consys_drv_type type);
/* NOTE: debug only*/
int consys_hw_force_conninfra_wakeup(void);
int consys_hw_force_conninfra_sleep(void);
int consys_hw_spi_clock_switch(enum connsys_spi_speed_type type);
struct platform_device *get_consys_device(void);
struct consys_base_addr *get_conn_reg_base_addr(void);
int consys_hw_dump_power_state(void);
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#endif /* _PLATFORM_CONSYS_HW_H_ */

28
package/mtk/drivers/conninfra/src/platform/include/consys_reg_base.h
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@ -1,28 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_CONSYS_REG_BASE_H_
#define _PLATFORM_CONSYS_REG_BASE_H_
struct consys_reg_base_addr {
unsigned long phy_addr;
unsigned long long size;
unsigned long vir_addr;
};
#endif /* _PLATFORM_CONSYS_REG_BASE_H_ */

57
package/mtk/drivers/conninfra/src/platform/include/consys_reg_mng.h
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@ -1,57 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_CONSYS_REG_MNG_H_
#define _PLATFORM_CONSYS_REG_MNG_H_
#include <linux/platform_device.h>
#include "consys_hw.h"
enum conn_dump_cpupcr_type
{
CONN_DUMP_CPUPCR_TYPE_BT = 1,
CONN_DUMP_CPUPCR_TYPE_WF = 2,
CONN_DUMP_CPUPCR_TYPE_ALL = 3,
};
struct consys_reg_mng_ops {
int(*consys_reg_mng_init) (struct platform_device *pdev);
int(*consys_reg_mng_deinit) (void);
int(*consys_reg_mng_check_reable) (void);
int(*consys_reg_mng_is_consys_reg) (unsigned int addr);
int(*consys_reg_mng_is_bus_hang) (void);
int(*consys_reg_mng_dump_bus_status) (void);
int(*consys_reg_mng_dump_conninfra_status) (void);
int(*consys_reg_mng_dump_cpupcr) (enum conn_dump_cpupcr_type, int times, unsigned long interval_us);
int(*consys_reg_mng_is_host_csr) (unsigned long addr);
};
int consys_reg_mng_init(struct platform_device *pdev, const struct conninfra_plat_data* plat_data);
int consys_reg_mng_deinit(void);
int consys_reg_mng_reg_readable(void);
int consys_reg_mng_is_connsys_reg(phys_addr_t addr);
int consys_reg_mng_reg_read(unsigned long addr, unsigned int *value, unsigned int mask);
int consys_reg_mng_reg_write(unsigned long addr, unsigned int value, unsigned int mask);
int consys_reg_mng_is_bus_hang(void);
int consys_reg_mng_dump_bus_status(void);
int consys_reg_mng_dump_conninfra_status(void);
int consys_reg_mng_dump_cpupcr(enum conn_dump_cpupcr_type dump_type, int times, unsigned long interval_us);
int consys_reg_mng_is_host_csr(unsigned long addr);
#endif /* _PLATFORM_CONSYS_REG_MNG_H_ */

174
package/mtk/drivers/conninfra/src/platform/include/consys_reg_util.h
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@ -1,174 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_CONSYS_REG_UTIL_H_
#define _PLATFORM_CONSYS_REG_UTIL_H_
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/* platform dependent */
#include "plat_def.h"
#ifndef BIT
#define BIT(x) (1<<(x))
#endif
#define KBYTE (1024*sizeof(char))
#ifndef GENMASK
#define GENMASK(h, l) \
(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
#endif
#define GET_BIT_MASK(value, mask) ((value) & (mask))
#define SET_BIT_MASK(pdest, value, mask) (*(pdest) = (GET_BIT_MASK(*(pdest), ~(mask)) | GET_BIT_MASK(value, mask)))
#define GET_BIT_RANGE(data, end, begin) ((data) & GENMASK(end, begin))
#define SET_BIT_RANGE(pdest, data, end, begin) (SET_BIT_MASK(pdest, data, GENMASK(end, begin)))
#define CONSYS_SET_BIT(REG, BITVAL) (*((volatile unsigned int *)(REG)) |= ((unsigned int)(BITVAL)))
#define CONSYS_CLR_BIT(REG, BITVAL) ((*(volatile unsigned int *)(REG)) &= ~((unsigned int)(BITVAL)))
#define CONSYS_CLR_BIT_WITH_KEY(REG, BITVAL, KEY) {\
unsigned int val = (*(volatile unsigned int *)(REG)); \
val &= ~((unsigned int)(BITVAL)); \
val |= ((unsigned int)(KEY)); \
(*(volatile unsigned int *)(REG)) = val;\
}
#define CONSYS_REG_READ(addr) (*((volatile unsigned int *)(addr)))
#define CONSYS_REG_READ_BIT(addr, BITVAL) (*((volatile unsigned int *)(addr)) & ((unsigned int)(BITVAL)))
#define CONSYS_REG_WRITE(addr, data) mt_reg_sync_writel(data, addr)
#define CONSYS_REG_WRITE_RANGE(reg, data, end, begin) {\
unsigned int val = CONSYS_REG_READ(reg); \
SET_BIT_RANGE(&val, data, end, begin); \
CONSYS_REG_WRITE(reg, val); \
}
#define CONSYS_REG_WRITE_MASK(reg, data, mask) {\
unsigned int val = CONSYS_REG_READ(reg); \
SET_BIT_MASK(&val, data, mask); \
CONSYS_REG_WRITE(reg, val); \
}
/*
* Write value with value_offset bits of right shift and size bits,
* to the reg_offset-th bit of address reg
* value -----------XXXXXXXXXXXX-------------------
* |<--size-->|<--value_offset-->|
* reg -------------OOOOOOOOOOOO-----------------
* |<--size-->|<--reg_offset-->|
* result -------------XXXXXXXXXXXX-----------------
*/
#define CONSYS_REG_WRITE_OFFSET_RANGE(reg, value, reg_offset, value_offset, size) ({\
unsigned int data = (value) >> (value_offset); \
data = GET_BIT_RANGE(data, size, 0); \
data = data << (reg_offset); \
CONSYS_REG_WRITE_RANGE(reg, data, ((reg_offset) + ((size) - 1)), reg_offset); \
})
#define CONSYS_REG_WRITE_BIT(reg, offset, val) CONSYS_REG_WRITE_OFFSET_RANGE(reg, ((val) & 1), offset, 0, 1)
#define CONSYS_REG_BIT_POLLING(addr, bit_index, exp_val, loop, delay, success) {\
unsigned int polling_count = 0; \
unsigned int reg_value = 0; \
success = 0; \
reg_value = (CONSYS_REG_READ_BIT(addr, (0x1 << bit_index)) >> bit_index); \
while (reg_value != exp_val) { \
if (polling_count > loop) { \
success = -1; \
break; \
} \
reg_value = (CONSYS_REG_READ_BIT(addr, (0x1 << bit_index)) >> bit_index); \
udelay(delay); \
polling_count++; \
} \
}
#define CONSYS_REG_POLLING_LARGER_OR_EQUAL(addr, mask, bit_index, exp_val, loop, delay, success) {\
unsigned int polling_count = 0; \
unsigned int reg_value = 0; \
success = 0; \
reg_value = ((CONSYS_REG_READ(addr) & mask) >> bit_index); \
while (reg_value < exp_val) { \
if (polling_count > loop) { \
success = -1; \
break; \
} \
reg_value = ((CONSYS_REG_READ(addr) & mask) >> bit_index); \
udelay(delay); \
polling_count++; \
} \
}
#define CONSYS_REG_POLLING_EQUAL(addr, mask, bit_index, exp_val, loop, delay, success) {\
unsigned int polling_count = 0; \
unsigned int reg_value = 0; \
success = 0; \
reg_value = ((CONSYS_REG_READ(addr) & mask) >> bit_index); \
while (reg_value != exp_val) { \
if (polling_count > loop) { \
success = -1; \
break; \
} \
reg_value = ((CONSYS_REG_READ(addr) & mask) >> bit_index); \
udelay(delay); \
polling_count++; \
} \
}
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#endif /* _PLATFORM_CONSYS_REG_UTIL_H_ */

99
package/mtk/drivers/conninfra/src/platform/include/emi_mng.h
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_EMI_MNG_H_
#define _PLATFORM_EMI_MNG_H_
#include <linux/platform_device.h>
#include <linux/types.h>
#include "osal.h"
#include "consys_hw.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
struct consys_emi_addr_info {
/* This include BT/WF FW and WFDMA */
phys_addr_t emi_ap_phy_base;
unsigned int emi_ap_phy_size;
unsigned int fw_emi_size;
};
typedef int(*CONSYS_IC_EMI_SET_REGION_PROTECTION) (void);
typedef int(*CONSYS_IC_EMI_SET_REMAPPING_REG) (void);
typedef unsigned int (*CONSYS_IC_GET_FW_EMI_SIZE)(void);
struct consys_platform_emi_ops {
CONSYS_IC_EMI_SET_REGION_PROTECTION consys_ic_emi_set_region_protection;
CONSYS_IC_EMI_SET_REMAPPING_REG consys_ic_emi_set_remapping_reg;
CONSYS_IC_GET_FW_EMI_SIZE consys_ic_emi_get_fw_emi_size;
};
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
int emi_mng_init(struct platform_device *pdev, const struct conninfra_plat_data* plat_data);
int emi_mng_deinit(void);
int emi_mng_set_region_protection(void);
int emi_mng_set_remapping_reg(void);
struct consys_emi_addr_info* emi_mng_get_phy_addr(void);
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#endif /* _PLATFORM_EMI_MNG_H_ */

31
package/mtk/drivers/conninfra/src/platform/include/plat_def.h
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_DEF_H_
#define _PLATFORM_DEF_H_
#include <linux/delay.h>
#include <linux/io.h>
#define mt_reg_sync_writel(v, a) \
do { \
writel((v), (void __force __iomem *)((a))); \
mb(); \
} while (0)
#endif /* _PLATFORM_DEF_H_ */

110
package/mtk/drivers/conninfra/src/platform/include/pmic_mng.h
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_PMIC_MNG_H_
#define _PLATFORM_PMIC_MNG_H_
#include <linux/platform_device.h>
#include "consys_hw.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
typedef int(*CONSYS_PMIC_GET_FROM_DTS) (
struct platform_device *pdev,
struct conninfra_dev_cb* dev_cb);
typedef int(*CONSYS_PMIC_COMMON_POWER_CTRL) (unsigned int enable);
typedef int(*CONSYS_PMIC_WIFI_POWER_CTRL) (unsigned int enable);
typedef int(*CONSYS_PMIC_BT_POWER_CTRL) (unsigned int enable);
typedef int(*CONSYS_PMIC_GPS_POWER_CTRL) (unsigned int enable);
typedef int(*CONSYS_PMIC_FM_POWER_CTRL) (unsigned int enable);
typedef int(*CONSYS_PMIC_EVENT_NOTIFIER) (unsigned int id, unsigned int event);
struct consys_platform_pmic_ops {
CONSYS_PMIC_GET_FROM_DTS consys_pmic_get_from_dts;
/* vcn 18 */
CONSYS_PMIC_COMMON_POWER_CTRL consys_pmic_common_power_ctrl;
CONSYS_PMIC_WIFI_POWER_CTRL consys_pmic_wifi_power_ctrl;
CONSYS_PMIC_BT_POWER_CTRL consys_pmic_bt_power_ctrl;
CONSYS_PMIC_GPS_POWER_CTRL consys_pmic_gps_power_ctrl;
CONSYS_PMIC_FM_POWER_CTRL consys_pmic_fm_power_ctrl;
CONSYS_PMIC_EVENT_NOTIFIER consys_pmic_event_notifier;
};
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
int pmic_mng_init(
struct platform_device *pdev,
struct conninfra_dev_cb* dev_cb,
const struct conninfra_plat_data* plat_data);
int pmic_mng_deinit(void);
int pmic_mng_common_power_ctrl(unsigned int enable);
int pmic_mng_wifi_power_ctrl(unsigned int enable);
int pmic_mng_bt_power_ctrl(unsigned int enable);
int pmic_mng_gps_power_ctrl(unsigned int enable);
int pmic_mng_fm_power_ctrl(unsigned int enable);
int pmic_mng_event_cb(unsigned int id, unsigned int event);
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#endif /* _PLATFORM_PMIC_MNG_H_ */

59
package/mtk/drivers/conninfra/src/platform/mt7981/include/mt7981.h
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@ -1,59 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7981_H_
#define _PLATFORM_MT7981_H_
enum
{
ADIE_TYPE_NONE = 0,
ADIE_TYPE_ONE,
ADIE_TYPE_TWO,
ADIE_TYPE_NUM_MAX
};
enum conn_semaphore_type
{
CONN_SEMA_CHIP_POWER_ON_INDEX = 0,
CONN_SEMA_CALIBRATION_INDEX = 1,
CONN_SEMA_FW_DL_INDEX = 2,
CONN_SEMA_CLOCK_SWITCH_INDEX = 3,
CONN_SEMA_CCIF_INDEX = 4,
CONN_SEMA_COEX_INDEX = 5,
CONN_SEMA_USB_EP0_INDEX = 6,
CONN_SEMA_USB_SHARED_INFO_INDEX = 7,
CONN_SEMA_USB_SUSPEND_INDEX = 8,
CONN_SEMA_USB_RESUME_INDEX = 9,
CONN_SEMA_PCIE_INDEX = 10,
CONN_SEMA_RFSPI_INDEX = 11,
CONN_SEMA_EFUSE_INDEX = 12,
CONN_SEMA_THERMAL_INDEX = 13,
CONN_SEMA_FLASH_INDEX = 14,
CONN_SEMA_DEBUG_INDEX = 15,
CONN_SEMA_WIFI_LP_INDEX = 16,
CONN_SEMA_PATCH_DL_INDEX = 17,
CONN_SEMA_SHARED_VAR_INDEX = 18,
CONN_SEMA_CONN_INFRA_COMMON_SYSRAM_INDEX = 19,
CONN_SEMA_NUM_MAX = 32 /* can't be omitted */
};
unsigned int consys_soc_chipid_get(void);
unsigned int consys_get_hw_ver(void);
#endif /* _PLATFORM_MT7981_H_ */

132
package/mtk/drivers/conninfra/src/platform/mt7981/include/mt7981_consys_reg.h
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@ -1,132 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7981_CONSYS_REG_H_
#define _PLATFORM_MT7981_CONSYS_REG_H_
#include "consys_reg_base.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
enum consys_base_addr_index {
TOP_MISC_BASE = 0, /* top_misc */
TOPRGU_BASE = 1, /* TOPRGU */
GPIO_BASE = 2, /* GPIO */
IOCFG_TM_BASE = 3, /* IOCFG_TM */
IOCFG_LT_BASE = 4, /* IOCFG_LT */
INFRACFG_AO_BASE = 5, /* infracfg_ao_auto_gen_reg */
CONN_INFRA_CFG_BASE = 6, /* conn_infra_cfg */
CONN_INFRA_SYSRAM_BASE = 7, /* conn_infra_sysram */
CONN_INFRA_CLKGEN_ON_TOP_BASE = 8, /* conn_infra_clkgen_on_top */
CONN_HOST_CSR_TOP_BASE = 9, /* conn_host_csr_top */
CONN_INFRA_BUS_CR_BASE = 10, /* conn_infra_bus_cr */
CONN_INFRA_RGU_BASE = 11, /* conn_infra_rgu */
CONN_WT_SLP_CTL_REG_BASE = 12, /* conn_wt_slp_ctl_reg */
INST2_CONN_WT_SLP_CTL_REG_BASE = 13, /* Inst2_conn_wt_slp_ctl_reg */
CONN_RF_SPI_MST_REG_BASE = 14, /* conn_rf_spi_mst_reg */
INST2_CONN_RF_SPI_MST_REG_BASE = 15, /* Inst2_conn_rf_spi_mst_reg */
CONN_SEMAPHORE_BASE = 16, /* conn_semaphore */
CONN_AFE_CTL_BASE = 17, /* conn_afe_ctl */
CONN_AFE_CTL_2ND_BASE = 18, /* conn_afe_ctl_2nd */
WF_TOP_SLPPROT_ON_BASE = 19, /* wf_top_slpprot_on by remapping to 0x81020000 */
WF_TOP_CFG_BASE = 20, /* wf_top_cfg by remapping to 0x80020000 */
WF_MCU_CONFIG_LS_BASE = 21, /* wf_mcu_confg_ls by remapping to 0x88000000 */
WF_MCU_BUS_CR_BASE = 22, /* wf_mcu_bus_cr by remapping to 0x830C0XXX */
WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_BASE = 23, /* wf_mcusys_infra_bus_full_u_debug_ctrl_ao by remapping to 0x810F0000 */
WF_TOP_CFG_ON_BASE = 24, /* wf_top_cfg_on by remapping to 0x81021000 */
CONSYS_BASE_ADDR_MAX
};
struct consys_base_addr {
struct consys_reg_base_addr reg_base_addr[CONSYS_BASE_ADDR_MAX];
};
extern struct consys_base_addr conn_reg;
#define REG_TOP_MISC_ADDR conn_reg.reg_base_addr[TOP_MISC_BASE].vir_addr
#define REG_TOP_RGU_ADDR conn_reg.reg_base_addr[TOPRGU_BASE].vir_addr
#define REG_GPIO_BASE_ADDR conn_reg.reg_base_addr[GPIO_BASE].vir_addr
#define REG_IOCFG_TM_ADDR conn_reg.reg_base_addr[IOCFG_TM_BASE].vir_addr
#define REG_IOCFG_LT_ADDR conn_reg.reg_base_addr[IOCFG_LT_BASE].vir_addr
#define REG_INFRACFG_AO_ADDR conn_reg.reg_base_addr[INFRACFG_AO_BASE].vir_addr
#define REG_CONN_INFRA_CFG_ADDR conn_reg.reg_base_addr[CONN_INFRA_CFG_BASE].vir_addr
#define REG_CONN_INFRA_SYSRAM_ADDR conn_reg.reg_base_addr[CONN_INFRA_SYSRAM_BASE].vir_addr
#define REG_CONN_INFRA_CLKGEN_ON_TOP_ADDR conn_reg.reg_base_addr[CONN_INFRA_CLKGEN_ON_TOP_BASE].vir_addr
#define REG_CONN_HOST_CSR_TOP_ADDR conn_reg.reg_base_addr[CONN_HOST_CSR_TOP_BASE].vir_addr
#define REG_CONN_INFRA_BUS_CR_ADDR conn_reg.reg_base_addr[CONN_INFRA_BUS_CR_BASE].vir_addr
#define REG_CONN_INFRA_RGU_ADDR conn_reg.reg_base_addr[CONN_INFRA_RGU_BASE].vir_addr
#define REG_CONN_WT_SLP_CTL_REG_ADDR conn_reg.reg_base_addr[CONN_WT_SLP_CTL_REG_BASE].vir_addr
#define REG_INST2_CONN_WT_SLP_CTL_REG_ADDR conn_reg.reg_base_addr[INST2_CONN_WT_SLP_CTL_REG_BASE].vir_addr
#define REG_CONN_RF_SPI_MST_REG_ADDR conn_reg.reg_base_addr[CONN_RF_SPI_MST_REG_BASE].vir_addr
#define REG_INST2_CONN_RF_SPI_MST_REG_ADDR conn_reg.reg_base_addr[INST2_CONN_RF_SPI_MST_REG_BASE].vir_addr
#define REG_CONN_SEMAPHORE_ADDR conn_reg.reg_base_addr[CONN_SEMAPHORE_BASE].vir_addr
#define REG_CONN_AFE_CTL_ADDR conn_reg.reg_base_addr[CONN_AFE_CTL_BASE].vir_addr
#define REG_CONN_AFE_CTL_2ND_ADDR conn_reg.reg_base_addr[CONN_AFE_CTL_2ND_BASE].vir_addr
#define REG_WF_TOP_SLPPROT_ON_ADDR conn_reg.reg_base_addr[WF_TOP_SLPPROT_ON_BASE].vir_addr
#define REG_WF_TOP_CFG_ADDR conn_reg.reg_base_addr[WF_TOP_CFG_BASE].vir_addr
#define REG_WF_MCU_CONFIG_LS_ADDR conn_reg.reg_base_addr[WF_MCU_CONFIG_LS_BASE].vir_addr
#define REG_WF_MCU_BUS_CR_ADDR conn_reg.reg_base_addr[WF_MCU_BUS_CR_BASE].vir_addr
#define REG_WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_ADDR conn_reg.reg_base_addr[WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_BASE].vir_addr
#define REG_WF_TOP_CFG_ON_ADDR conn_reg.reg_base_addr[WF_TOP_CFG_ON_BASE].vir_addr
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
struct consys_base_addr* get_conn_reg_base_addr(void);
#endif /* _PLATFORM_MT7981_CONSYS_REG_H_ */

243
package/mtk/drivers/conninfra/src/platform/mt7981/include/mt7981_consys_reg_offset.h
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@ -1,243 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7981_CONSYS_REG_OFFSET_H_
#define _PLATFORM_MT7981_CONSYS_REG_OFFSET_H_
/**********************************************************************/
/* Base: TOP_MISC (0x11D1_0000) */
/**********************************************************************/
#define CONNSYS_MISC 0x0114
#define TOP_MISC_RSRV_ALL1_3 0x021C
/**********************************************************************/
/* Base: TOP RGU (0x1001_C000) */
/**********************************************************************/
#define TOP_RGU_WDT_SWSYSRST 0x0018
/**********************************************************************/
/* Base: GPIO (0x11D0_0000) */
/**********************************************************************/
#define GPIO_MODE5 0x0350
#define GPIO_MODE6 0x0360
#define GPIO_MODE7 0x0370
/**********************************************************************/
/* Base: IOCFG_TM (0x11F0_0000) */
/**********************************************************************/
#define IOCFG_TM_DRV_CFG0 0x0000
#define IOCFG_TM_DRV_CFG1 0x0010
/**********************************************************************/
/* Base: IOCFG_LT (0x11F1_0000) */
/**********************************************************************/
#define IOCFG_LT_DRV_CFG0 0x0000
#define IOCFG_LT_DRV_CFG1 0x0010
/**********************************************************************/
/* Base: INFRACFG_AO (0x1000_3000) */
/**********************************************************************/
#define CONN2AP_GALS_SLPPROT 0x00D0
#define AP2CONN_GALS_SLPPROT 0x00D4
/**********************************************************************/
/* Base: CONN_INFRA_CFG (0x1800_1000) */
/**********************************************************************/
#define CONN_INFRA_CFG_IP_VERSION 0x0000
#define EFUSE 0x0020
#define ADIE_CTL 0x0030
#define CONN_INFRA_CFG_PWRCTRL0 0x0200
#define CONN_INFRA_CFG_RC_CTL_0 0x0380
#define OSC_CTL_0 0x0300
#define EMI_CTL_WF 0x0414
#define CONN_INFRA_WF_SLP_CTRL 0x0540
#define CONN_INFRA_WF_SLP_STATUS 0x0544
/**********************************************************************/
/* Base: CONN_INFRA_SYSRAM (0x1805_0000) */
/**********************************************************************/
#define SYSRAM_BASE_ADDR 0x0000
/**********************************************************************/
/* Base: CONN_INFRA_CLKGEN_ON_TOP (0x1800_9000) */
/**********************************************************************/
#define CKGEN_BUS_WPLL_DIV_1 0x0008
#define CKGEN_BUS_WPLL_DIV_2 0x000C
#define CKGEN_RFSPI_WPLL_DIV 0x0040
#define CKGEN_BUS 0x0A00
/**********************************************************************/
/* Base: CONN_HOST_CSR_TOP (0x1806_0000) */
/**********************************************************************/
#define CONN_INFRA_WAKEPU_TOP 0x01A0
#define CONN_INFRA_WAKEPU_WF 0x01A4
#define CONN2AP_REMAP_MCU_EMI 0x01C4
#define CONN2AP_REMAP_WF_PERI 0x01D4
#define CONN2AP_RSVD_PERI_REGION1 0x01D8
#define DBG_DUMMY_3 0x02CC
/**********************************************************************/
/* Base: CONN_INFRA_BUS_CR (0x1800_E000) */
/**********************************************************************/
#define CONN_INFRA_BUS_OFF_TIMEOUT_CTRL 0x0300
#define CONN_INFRA_BUS_ON_TIMEOUT_CTRL 0x031C
#define CONN2AP_EMI_PATH_ADDR_START 0x0360
#define CONN2AP_EMI_PATH_ADDR_END 0x0364
/**********************************************************************/
/* Base: CONN_INFRA_RGU (0x1800_0000) */
/**********************************************************************/
#define WFSYS_ON_TOP_PWR_CTL 0x0010
#define BGFYS_ON_TOP_PWR_CTL 0x0020
#define SYSRAM_HWCTL_PDN 0x0050
#define SYSRAM_HWCTL_SLP 0x0054
#define WFSYS_CPU_SW_RST_B 0x0120
/**********************************************************************/
/* Base: CONN_WT_SLP_CTL_REG (0x1800_5000) */
/* Base: INST2_CONN_WT_SLP_CTL_REG (0x1808_5000) */
/**********************************************************************/
#define WB_WF_CK_ADDR 0x0070
#define WB_WF_WAKE_ADDR 0x0074
#define WB_WF_ZPS_ADDR 0x0078
#define WB_TOP_CK_ADDR 0x0084
#define WB_WF_B0_CMD_ADDR 0x008C
#define WB_WF_B1_CMD_ADDR 0x0090
#define WB_SLP_TOP_CK_0 0x0120
#define WB_SLP_TOP_CK_1 0x0124
/**********************************************************************/
/* Base: CONN_RF_SPI_MST_REG (0x1800_4000) */
/* Base: INST2_CONN_RF_SPI_MST_REG (0x1808_4000) */
/**********************************************************************/
#define SPI_STA 0x0000
#define SPI_WF_ADDR 0x0010
#define SPI_WF_WDAT 0x0014
#define SPI_WF_RDAT 0x0018
#define SPI_BT_ADDR 0x0020
#define SPI_BT_WDAT 0x0024
#define SPI_BT_RDAT 0x0028
#define SPI_FM_ADDR 0x0030
#define SPI_FM_WDAT 0x0034
#define SPI_FM_RDAT 0x0038
#define SPI_GPS_ADDR 0x0040
#define SPI_GPS_WDAT 0x0044
#define SPI_GPS_RDAT 0x0048
#define SPI_TOP_ADDR 0x0050
#define SPI_TOP_WDAT 0x0054
#define SPI_TOP_RDAT 0x0058
/**********************************************************************/
/* Base: CONN_SEMAPHORE_BASE (0x1807_0000) */
/**********************************************************************/
#define CONN_SEMA00_M2_OWN_STA 0x2000
#define CONN_SEMA00_M2_OWN_REL 0x2200
#define CONN_SEMA_OWN_BY_M0_STA_REP 0x0400
#define CONN_SEMA_OWN_BY_M1_STA_REP 0x1400
#define CONN_SEMA_OWN_BY_M2_STA_REP 0x2400
#define CONN_SEMA_OWN_BY_M3_STA_REP 0x3400
#define CONN_SEMA_OWN_BY_M4_STA_REP 0x4400
#define CONN_SEMA_OWN_BY_M5_STA_REP 0x5400
#define CONN_SEMA_OWN_BY_M6_STA_REP 0x6400
#define CONN_SEMA_OWN_BY_M7_STA_REP 0x7400
/**********************************************************************/
/* Base: CONN_AFE_CTL_BASE (0x1800_3000) */
/* Base: CONN_AFE_CTL_2ND_BASE (0x1808_3000) */
/**********************************************************************/
#define RG_DIG_EN_01 0x0000
#define RG_DIG_EN_02 0x0004
#define RG_DIG_EN_03 0x0008
#define RG_DIG_TOP_01 0x000C
#define RG_PLL_STB_TIME 0x00F4
/**********************************************************************/
/* Base: WF_TOP_SLPPROT_ON_BASE (0x8102_0000 remap to 0x184C_0000) */
/**********************************************************************/
#define WF_TOP_SLPPROT_ON_STATUS_READ 0x300C
/**********************************************************************/
/* Base: WF_TOP_CFG_BASE (0x8002_0000 remap to 0x184B_0000) */
/**********************************************************************/
#define WF_TOP_CFG_IP_VERSION 0x0010
/**********************************************************************/
/* Base: WF_MCU_CONFIG_LS_BASE (0x8800_0000 remap to 0x184F_0000) */
/**********************************************************************/
#define BUSHANGCR 0x0440
/**********************************************************************/
/* Base: WF_MCU_BUS_CR_BASE (0x830C_0XXX remap to 0x1840_0XXX) */
/**********************************************************************/
#define AP2WF_REMAP_1 0x0120
/**********************************************************************/
/* Base: WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_BASE (0x810F_0000 remap to 0x1850_0000) */
/**********************************************************************/
#define WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_WFMCU_PWA_CTRL0 0x0000
/**********************************************************************/
/* Base: WF_TOP_CFG_ON_BASE (0x8102_1000 remap to 0x184C_0000) */
/**********************************************************************/
#define ROMCODE_INDEX 0x1604
/**********************************************************************/
/* A-die CR */
/**********************************************************************/
#define ATOP_CHIP_ID 0x02C
#define ATOP_TOP_CLK_EN 0xA00
#define ATOP_RG_ENCAL_WBTAC_IF_SW 0x070
#define ATOP_RG_WRI_CK_SELECT 0x4AC
#define ATOP_EFUSE_CTRL_1 0x108
#define ATOP_EFUSE_CTRL_2 0x148
#define ATOP_EFUSE_CTRL_3 0x14C
#define ATOP_EFUSE_CTRL_4 0x15C
#define ATOP_EFUSE_RDATA0 0x130
#define ATOP_EFUSE_RDATA1 0x134
#define ATOP_EFUSE_RDATA2 0x138
#define ATOP_EFUSE_RDATA3 0x13C
#define ATOP_RG_EFUSE_CFG5 0x144
#define ATOP_THADC_ANALOG 0x3A6
#define ATOP_THADC_SLOP 0x3A7
#define ATOP_RG_TOP_THADC_BG 0x034
#define ATOP_RG_TOP_THADC_00 0x038
#define ATOP_XTAL_TRIM_FLOW 0x3AC
#define ATOP_XTAL_CR_C1_SEL_AXM_80M_OSC 0x390
#define ATOP_XTAL_CR_C1_SEL_AXM_40M_OSC 0x391
#define ATOP_XTAL_CR_C1_SEL_AXM_TRIM1_80M_OSC 0x398
#define ATOP_XTAL_CR_C1_SEL_AXM_TRIM1_40M_OSC 0x399
#define ATOP_RG_STRAP_PIN_IN 0x4FC
#define ATOP_RG_XO_01 0x65C
#define ATOP_RG_XO_03 0x664
#define ATOP_7975_XTAL_CALIBRATION 0x3A1
#define ATOP_7975_XTAL_TRIM2_COMPENSATION 0x3A2
#define ATOP_7975_XTAL_TRIM3_COMPENSATION 0x3A3
#define ATOP_7975_XTAL_TRIM4_COMPENSATION 0x3A4
#define ATOP_7975_XTAL_TRIM_FLOW 0x3A5
#define ATOP_7975_CR_C1_C2_A94 0xA94
#define ATOP_7975_CR_C1_C2_A18 0xA18
#define ATOP_7975_CR_C1_C2_A84 0xA84
#define ATOP_7975_CR_C1_C2_AA4 0xAA4
#endif /* _PLATFORM_MT7981_CONSYS_REG_OFFSET_H_ */

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package/mtk/drivers/conninfra/src/platform/mt7981/include/mt7981_emi.h
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7981_EMI_H_
#define _PLATFORM_MT7981_EMI_H_
#include "osal.h"
#include "emi_mng.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
struct consys_platform_emi_ops* get_consys_platform_emi_ops(void);
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#endif /* _PLATFORM_MT7981_EMI_H_ */

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package/mtk/drivers/conninfra/src/platform/mt7981/include/mt7981_pmic.h
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7981_PMIC_H_
#define _PLATFORM_MT7981_PMIC_H_
#include "osal.h"
#include "pmic_mng.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
struct consys_platform_pmic_ops* get_consys_platform_pmic_ops(void);
#endif /* _PLATFORM_MT7981_PMIC_H_ */

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package/mtk/drivers/conninfra/src/platform/mt7981/include/mt7981_pos.h
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7981_POS_H_
#define _PLATFORM_MT7981_POS_H_
int consys_plt_hw_init(void);
int consys_xtal_ctrl_fast_mode(void);
int consys_sw_reset_ctrl(bool bassert);
int consys_tx_rx_bus_slp_prot_ctrl(bool enable);
void consys_set_if_pinmux(bool enable);
int consys_polling_chipid(void);
int consys_plt_adie_type_cfg(void);
int consys_bus_clock_ctrl(enum consys_drv_type drv_type, unsigned int bus_clock);
int consys_emi_set_remapping_reg(void);
int consys_emi_set_region_protection(void);
int connsys_d_die_cfg(void);
int connsys_conninfra_sysram_hw_ctrl(void);
int connsys_spi_master_cfg(void);
int consys_sema_acquire_timeout(unsigned int index, unsigned int usec);
void consys_sema_release(unsigned int index);
int consys_spi_read(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data);
int consys_spi_write(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data);
int consys_spi_write_offset_range(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int value,
unsigned int reg_offset, unsigned int value_offset, unsigned int size);
int connsys_a_die_cfg(void);
int connsys_afe_wbg_cal(void);
int connsys_subsys_pll_initial(void);
int connsys_osc_legacy_mode(void);
int connsys_top_pwr_ctrl(void);
int connsys_conn_infra_bus_timeout(void);
int connsys_clkgen_wpll_hw_ctrl(void);
int consys_conninfra_top_wakeup(void);
int consys_conninfra_top_sleep(void);
int consys_adie_top_ck_en_on_off_ctrl(enum consys_drv_type type, unsigned char on);
int consys_conninfra_wf_wakeup(void);
int consys_conninfra_wf_sleep(void);
int consys_conn_wmcpu_sw_reset(bool bassert);
int consys_wf_bus_slp_prot_ctrl(bool enable);
int consys_wfsys_top_on_ctrl(bool enable);
int consys_wfsys_bus_slp_prot_check(bool enable);
int consys_wfsys_bus_timeout_ctrl(void);
int consys_wmcpu_idle_loop_check(void);
int consys_wpll_ctrl(bool enable);
int consys_conninfra_wf_req_clr(void);
#endif /* _PLATFORM_MT7981_POS_H_ */

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package/mtk/drivers/conninfra/src/platform/mt7981/mt7981.c
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include <linux/delay.h>
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include "osal.h"
#include "conninfra.h"
#include "consys_hw.h"
#include "consys_reg_mng.h"
#include "consys_reg_util.h"
#include "mt7981.h"
#include "mt7981_pos.h"
#include "emi_mng.h"
#include "mt7981_consys_reg.h"
#include "mt7981_consys_reg_offset.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
#define PLATFORM_SOC_CHIP 0x7981
#define CONN_IP_VER 0x02090000
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
struct consys_hw_ops_struct g_consys_hw_ops_mt7981 = {
/* HW init */
.consys_plt_hw_init = consys_plt_hw_init,
/* POS */
.consys_plt_xtal_ctrl_fast_mode = consys_xtal_ctrl_fast_mode,
.consys_plt_connsys_sw_reset_ctrl = consys_sw_reset_ctrl,
.consys_plt_set_if_pinmux = consys_set_if_pinmux,
.consys_plt_tx_rx_bus_slp_prot_ctrl = consys_tx_rx_bus_slp_prot_ctrl,
.consys_plt_polling_consys_chipid = consys_polling_chipid,
.consys_plt_bus_clock_ctrl = consys_bus_clock_ctrl,
.consys_plt_d_die_cfg = connsys_d_die_cfg,
.consys_plt_conninfra_sysram_hw_ctrl = connsys_conninfra_sysram_hw_ctrl,
.consys_plt_spi_master_cfg = connsys_spi_master_cfg,
.consys_plt_a_die_cfg = connsys_a_die_cfg,
.consys_plt_afe_wbg_cal = connsys_afe_wbg_cal,
.consys_plt_subsys_pll_initial = connsys_subsys_pll_initial,
.consys_plt_osc_legacy_mode = connsys_osc_legacy_mode,
.consys_plt_top_pwr_ctrl = connsys_top_pwr_ctrl,
.consys_plt_conn_infra_bus_timeout = connsys_conn_infra_bus_timeout,
.consys_plt_clkgen_wpll_hw_ctrl = connsys_clkgen_wpll_hw_ctrl,
.consys_plt_conninfra_wakeup = consys_conninfra_top_wakeup,
.consys_plt_conninfra_sleep = consys_conninfra_top_sleep,
.consys_plt_adie_top_ck_en_on_off_ctrl = consys_adie_top_ck_en_on_off_ctrl,
.consys_plt_conninfra_wf_wakeup = consys_conninfra_wf_wakeup,
.consys_plt_conninfra_wf_sleep = consys_conninfra_wf_sleep,
.consys_plt_conn_wmcpu_sw_reset = consys_conn_wmcpu_sw_reset,
.consys_plt_wf_bus_slp_prot_ctrl = consys_wf_bus_slp_prot_ctrl,
.consys_plt_wfsys_top_on_ctrl = consys_wfsys_top_on_ctrl,
.consys_plt_wfsys_bus_slp_prot_check = consys_wfsys_bus_slp_prot_check,
.consys_plt_wfsys_bus_timeout_ctrl = consys_wfsys_bus_timeout_ctrl,
.consys_plt_conn_wmcpu_idle_loop_check = consys_wmcpu_idle_loop_check,
.consys_plt_wpll_ctrl = consys_wpll_ctrl,
.consys_plt_conninfra_wf_req_clr = consys_conninfra_wf_req_clr,
/* load from dts */
/* TODO: mtcmos should move to a independent module */
.consys_plt_clk_get_from_dts = NULL,
.consys_plt_clk_detach = NULL,
/* clock */
.consys_plt_soc_chipid_get = consys_soc_chipid_get,
/* debug */
.consys_plt_get_hw_ver = consys_get_hw_ver,
.consys_plt_spi_read = consys_spi_read,
.consys_plt_spi_write = consys_spi_write,
.consys_plt_spi_clock_switch = NULL,
.consys_plt_power_state = NULL,
/* others */
.consys_plt_adie_type_cfg = consys_plt_adie_type_cfg,
};
/* For mt7981 */
extern struct consys_hw_ops_struct g_consys_hw_ops_mt7981;
extern struct consys_reg_mng_ops g_dev_consys_reg_ops_mt7981;
extern struct consys_platform_emi_ops g_consys_platform_emi_ops_mt7981;
extern struct consys_platform_pmic_ops g_consys_platform_pmic_ops_mt7981;
const struct conninfra_plat_data mt7981_plat_data = {
.chip_id = PLATFORM_SOC_CHIP,
.hw_ops = &g_consys_hw_ops_mt7981,
.reg_ops = &g_dev_consys_reg_ops_mt7981,
.platform_emi_ops = &g_consys_platform_emi_ops_mt7981,
.platform_pmic_ops = &g_consys_platform_pmic_ops_mt7981,
};
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
unsigned int consys_soc_chipid_get(void)
{
return PLATFORM_SOC_CHIP;
}
unsigned int consys_get_hw_ver(void)
{
return CONN_IP_VER;
}

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package/mtk/drivers/conninfra/src/platform/mt7981/mt7981_consys_reg.c
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/random.h>
#include "consys_reg_mng.h"
#include "mt7981_consys_reg.h"
#include "mt7981_consys_reg_offset.h"
#include "consys_hw.h"
#include "consys_reg_util.h"
#define CFG_REG_LOAD_FROM_DTS_CTRL 0
static int consys_reg_init(struct platform_device *pdev);
static int consys_reg_deinit(void);
struct consys_base_addr conn_reg = {
.reg_base_addr[TOP_MISC_BASE] = {0x11D10000, 0x1000, 0},
.reg_base_addr[TOPRGU_BASE] = {0x1001C000, 0x1000, 0},
.reg_base_addr[GPIO_BASE] = {0x11D00000, 0x1000, 0},
.reg_base_addr[IOCFG_TM_BASE] = {0x11F00000, 0x1000, 0},
.reg_base_addr[IOCFG_LT_BASE] = {0x11F10000, 0x1000, 0},
.reg_base_addr[INFRACFG_AO_BASE] = {0x10003000, 0x1000, 0},
.reg_base_addr[CONN_INFRA_CFG_BASE] = {0x18001000, 0x1000, 0},
.reg_base_addr[CONN_INFRA_SYSRAM_BASE] = {0x18050000, 0x1000, 0},
.reg_base_addr[CONN_INFRA_CLKGEN_ON_TOP_BASE] = {0x18009000, 0x1000, 0},
.reg_base_addr[CONN_HOST_CSR_TOP_BASE] = {0x18060000, 0x1000, 0},
.reg_base_addr[CONN_INFRA_BUS_CR_BASE] = {0x1800E000, 0x1000, 0},
.reg_base_addr[CONN_INFRA_RGU_BASE] = {0x18000000, 0x1000, 0},
.reg_base_addr[CONN_WT_SLP_CTL_REG_BASE] = {0x18005000, 0x1000, 0},
.reg_base_addr[INST2_CONN_WT_SLP_CTL_REG_BASE] = {0x18085000, 0x1000, 0},
.reg_base_addr[CONN_RF_SPI_MST_REG_BASE] = {0x18004000, 0x1000, 0},
.reg_base_addr[INST2_CONN_RF_SPI_MST_REG_BASE] = {0x18084000, 0x1000, 0},
.reg_base_addr[CONN_SEMAPHORE_BASE] = {0x18070000, 0x10000, 0},
.reg_base_addr[CONN_AFE_CTL_BASE] = {0x18003000, 0x1000, 0},
.reg_base_addr[CONN_AFE_CTL_2ND_BASE] = {0x18083000, 0x1000, 0},
.reg_base_addr[WF_TOP_SLPPROT_ON_BASE] = {0x184C0000, 0x10000, 0},
.reg_base_addr[WF_TOP_CFG_BASE] = {0x184B0000, 0x1000, 0},
.reg_base_addr[WF_MCU_CONFIG_LS_BASE] = {0x184F0000, 0x1000, 0},
.reg_base_addr[WF_MCU_BUS_CR_BASE] = {0x18400000, 0x1000, 0},
.reg_base_addr[WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_BASE] = {0x18500000, 0x1000, 0},
.reg_base_addr[WF_TOP_CFG_ON_BASE] = {0x184C0000, 0x10000, 0},
};
const char* consys_base_addr_index_to_str[CONSYS_BASE_ADDR_MAX] = {
"TOP_MISC_BASE",
"TOPRGU_BASE",
"GPIO_BASE",
"IOCFG_TR_BASE",
"IOCFG_TL_BASE",
"INFRACFG_AO_BASE",
"CONN_INFRA_CFG_BASE",
"CONN_INFRA_SYSRAM_BASE",
"CONN_INFRA_CLKGEN_ON_TOP_BASE",
"CONN_HOST_CSR_TOP_BASE",
"CONN_INFRA_BUS_CR_BASE",
"CONN_INFRA_RGU_BASE",
"CONN_WT_SLP_CTL_REG_BASE",
"INST2_CONN_WT_SLP_CTL_REG_BASE",
"CONN_RF_SPI_MST_REG_BASE",
"INST2_CONN_RF_SPI_MST_REG_BASE",
"CONN_SEMAPHORE_BASE",
"CONN_AFE_CTL_BASE",
"CONN_AFE_CTL_2ND_BASE",
"WF_TOP_SLPPROT_ON_BASE",
"WF_TOP_CFG_BASE",
"WF_MCU_CONFIG_LS_BASE",
"WF_MCU_BUS_CR_BASE",
"WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_BASE",
"WF_TOP_CFG_ON_BASE"
};
struct consys_reg_mng_ops g_dev_consys_reg_ops_mt7981 = {
.consys_reg_mng_init = consys_reg_init,
.consys_reg_mng_deinit = consys_reg_deinit,
.consys_reg_mng_check_reable = NULL,
.consys_reg_mng_is_consys_reg = NULL,
.consys_reg_mng_is_bus_hang = NULL,
.consys_reg_mng_dump_bus_status = NULL,
.consys_reg_mng_dump_conninfra_status = NULL,
.consys_reg_mng_dump_cpupcr = NULL,
.consys_reg_mng_is_host_csr = NULL,
};
struct consys_base_addr* get_conn_reg_base_addr()
{
return &conn_reg;
}
static int consys_reg_init(struct platform_device *pdev)
{
int ret = -1;
struct device_node *node = NULL;
struct consys_reg_base_addr *base_addr = NULL;
int i = 0;
node = pdev->dev.of_node;
if (node) {
#if (CFG_REG_LOAD_FROM_DTS_CTRL == 1)
struct resource res;
int flag;
for (i = 0; i < CONSYS_BASE_ADDR_MAX; i++) {
base_addr = &conn_reg.reg_base_addr[i];
ret = of_address_to_resource(node, i, &res);
if (ret) {
pr_err("Get Reg Index(%d-%s) failed\n", i, consys_base_addr_index_to_str[i]);
continue;
}
base_addr->phy_addr = res.start;
base_addr->vir_addr = (unsigned long)of_iomap(node, i);
of_get_address(node, i, &(base_addr->size), &flag);
#if 0
pr_info("Get Index(%d-%s) phy_addr(0x%zx) vir_addr=(0x%zx) size=(0x%zx)\n",
i, consys_base_addr_index_to_str[i], base_addr->phy_addr,
base_addr->vir_addr, base_addr->size);
#endif
}
#else
for (i = 0; i < CONSYS_BASE_ADDR_MAX; i++) {
base_addr = &conn_reg.reg_base_addr[i];
if (base_addr->vir_addr == 0)
base_addr->vir_addr = (unsigned long)ioremap(base_addr->phy_addr, base_addr->size);
pr_info("Get Index(%d-%s) phy_addr(0x%zx) vir_addr=(0x%zx) size=(0x%zx)\n",
i, consys_base_addr_index_to_str[i], base_addr->phy_addr,
base_addr->vir_addr, base_addr->size);
}
#endif
} else {
pr_err("[%s] can't find CONSYS compatible node\n", __func__);
return ret;
}
return 0;
}
static int consys_reg_deinit(void)
{
int i = 0;
for (i = 0; i < CONSYS_BASE_ADDR_MAX; i++) {
if (conn_reg.reg_base_addr[i].vir_addr) {
pr_info("[%d] Unmap %s (0x%zx)\n", i, consys_base_addr_index_to_str[i],
conn_reg.reg_base_addr[i].vir_addr);
iounmap((void __iomem*)conn_reg.reg_base_addr[i].vir_addr);
conn_reg.reg_base_addr[i].vir_addr = 0;
}
}
return 0;
}

50
package/mtk/drivers/conninfra/src/platform/mt7981/mt7981_emi.c
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@ -1,50 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/of_reserved_mem.h>
#include "mt7981_emi.h"
#include "mt7981.h"
#include "mt7981_consys_reg.h"
#include "consys_hw.h"
#include "consys_reg_util.h"
#include "mt7981_pos.h"
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
unsigned int consys_emi_get_fw_emi_size(void)
{
return 0x100000;
}
struct consys_platform_emi_ops g_consys_platform_emi_ops_mt7981 = {
.consys_ic_emi_set_region_protection = consys_emi_set_region_protection,
.consys_ic_emi_set_remapping_reg = consys_emi_set_remapping_reg,
.consys_ic_emi_get_fw_emi_size = consys_emi_get_fw_emi_size,
};
struct consys_platform_emi_ops* get_consys_platform_emi_ops(void)
{
return &g_consys_platform_emi_ops_mt7981;
}

95
package/mtk/drivers/conninfra/src/platform/mt7981/mt7981_pmic.c
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@ -1,95 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/of_reserved_mem.h>
#include <linux/regulator/consumer.h>
#include <linux/notifier.h>
#include "consys_hw.h"
#include "consys_reg_util.h"
#include "osal.h"
#include "mt7981_pmic.h"
#include "mt7981_pos.h"
#include "mt7981_consys_reg.h"
#include "mt7981_consys_reg_offset.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
struct consys_platform_pmic_ops g_consys_platform_pmic_ops_mt7981 = {
.consys_pmic_get_from_dts = NULL,
.consys_pmic_common_power_ctrl = NULL,
.consys_pmic_wifi_power_ctrl = NULL,
.consys_pmic_bt_power_ctrl = NULL,
.consys_pmic_gps_power_ctrl = NULL,
.consys_pmic_fm_power_ctrl = NULL,
.consys_pmic_event_notifier = NULL,
};
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
struct consys_platform_pmic_ops* get_consys_platform_pmic_ops(void)
{
return &g_consys_platform_pmic_ops_mt7981;
}

1715
package/mtk/drivers/conninfra/src/platform/mt7981/mt7981_pos.c
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File diff suppressed because it is too large Load Diff

59
package/mtk/drivers/conninfra/src/platform/mt7986/include/mt7986.h
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@ -1,59 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7986_H_
#define _PLATFORM_MT7986_H_
enum
{
ADIE_TYPE_NONE = 0,
ADIE_TYPE_ONE,
ADIE_TYPE_TWO,
ADIE_TYPE_NUM_MAX
};
enum conn_semaphore_type
{
CONN_SEMA_CHIP_POWER_ON_INDEX = 0,
CONN_SEMA_CALIBRATION_INDEX = 1,
CONN_SEMA_FW_DL_INDEX = 2,
CONN_SEMA_CLOCK_SWITCH_INDEX = 3,
CONN_SEMA_CCIF_INDEX = 4,
CONN_SEMA_COEX_INDEX = 5,
CONN_SEMA_USB_EP0_INDEX = 6,
CONN_SEMA_USB_SHARED_INFO_INDEX = 7,
CONN_SEMA_USB_SUSPEND_INDEX = 8,
CONN_SEMA_USB_RESUME_INDEX = 9,
CONN_SEMA_PCIE_INDEX = 10,
CONN_SEMA_RFSPI_INDEX = 11,
CONN_SEMA_EFUSE_INDEX = 12,
CONN_SEMA_THERMAL_INDEX = 13,
CONN_SEMA_FLASH_INDEX = 14,
CONN_SEMA_DEBUG_INDEX = 15,
CONN_SEMA_WIFI_LP_INDEX = 16,
CONN_SEMA_PATCH_DL_INDEX = 17,
CONN_SEMA_SHARED_VAR_INDEX = 18,
CONN_SEMA_CONN_INFRA_COMMON_SYSRAM_INDEX = 19,
CONN_SEMA_NUM_MAX = 32 /* can't be omitted */
};
unsigned int consys_soc_chipid_get(void);
unsigned int consys_get_hw_ver(void);
#endif /* _PLATFORM_MT7986_H_ */

132
package/mtk/drivers/conninfra/src/platform/mt7986/include/mt7986_consys_reg.h
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@ -1,132 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7986_CONSYS_REG_H_
#define _PLATFORM_MT7986_CONSYS_REG_H_
#include "consys_reg_base.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
enum consys_base_addr_index {
TOP_MISC_BASE = 0, /* top_misc */
TOPRGU_BASE = 1, /* TOPRGU */
GPIO_BASE = 2, /* GPIO */
IOCFG_TR_BASE = 3, /* IOCFG_TR */
IOCFG_TL_BASE = 4, /* IOCFG_TL */
INFRACFG_AO_BASE = 5, /* infracfg_ao_auto_gen_reg */
CONN_INFRA_CFG_BASE = 6, /* conn_infra_cfg */
CONN_INFRA_SYSRAM_BASE = 7, /* conn_infra_sysram */
CONN_INFRA_CLKGEN_ON_TOP_BASE = 8, /* conn_infra_clkgen_on_top */
CONN_HOST_CSR_TOP_BASE = 9, /* conn_host_csr_top */
CONN_INFRA_BUS_CR_BASE = 10, /* conn_infra_bus_cr */
CONN_INFRA_RGU_BASE = 11, /* conn_infra_rgu */
CONN_WT_SLP_CTL_REG_BASE = 12, /* conn_wt_slp_ctl_reg */
INST2_CONN_WT_SLP_CTL_REG_BASE = 13, /* Inst2_conn_wt_slp_ctl_reg */
CONN_RF_SPI_MST_REG_BASE = 14, /* conn_rf_spi_mst_reg */
INST2_CONN_RF_SPI_MST_REG_BASE = 15, /* Inst2_conn_rf_spi_mst_reg */
CONN_SEMAPHORE_BASE = 16, /* conn_semaphore */
CONN_AFE_CTL_BASE = 17, /* conn_afe_ctl */
CONN_AFE_CTL_2ND_BASE = 18, /* conn_afe_ctl_2nd */
WF_TOP_SLPPROT_ON_BASE = 19, /* wf_top_slpprot_on by remapping to 0x81020000 */
WF_TOP_CFG_BASE = 20, /* wf_top_cfg by remapping to 0x80020000 */
WF_MCU_CONFIG_LS_BASE = 21, /* wf_mcu_confg_ls by remapping to 0x88000000 */
WF_MCU_BUS_CR_BASE = 22, /* wf_mcu_bus_cr by remapping to 0x830C0XXX */
WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_BASE = 23, /* wf_mcusys_infra_bus_full_u_debug_ctrl_ao by remapping to 0x810F0000 */
WF_TOP_CFG_ON_BASE = 24, /* wf_top_cfg_on by remapping to 0x81021000 */
CONSYS_BASE_ADDR_MAX
};
struct consys_base_addr {
struct consys_reg_base_addr reg_base_addr[CONSYS_BASE_ADDR_MAX];
};
extern struct consys_base_addr conn_reg;
#define REG_TOP_MISC_ADDR conn_reg.reg_base_addr[TOP_MISC_BASE].vir_addr
#define REG_TOP_RGU_ADDR conn_reg.reg_base_addr[TOPRGU_BASE].vir_addr
#define REG_GPIO_BASE_ADDR conn_reg.reg_base_addr[GPIO_BASE].vir_addr
#define REG_IOCFG_TR_ADDR conn_reg.reg_base_addr[IOCFG_TR_BASE].vir_addr
#define REG_IOCFG_TL_ADDR conn_reg.reg_base_addr[IOCFG_TL_BASE].vir_addr
#define REG_INFRACFG_AO_ADDR conn_reg.reg_base_addr[INFRACFG_AO_BASE].vir_addr
#define REG_CONN_INFRA_CFG_ADDR conn_reg.reg_base_addr[CONN_INFRA_CFG_BASE].vir_addr
#define REG_CONN_INFRA_SYSRAM_ADDR conn_reg.reg_base_addr[CONN_INFRA_SYSRAM_BASE].vir_addr
#define REG_CONN_INFRA_CLKGEN_ON_TOP_ADDR conn_reg.reg_base_addr[CONN_INFRA_CLKGEN_ON_TOP_BASE].vir_addr
#define REG_CONN_HOST_CSR_TOP_ADDR conn_reg.reg_base_addr[CONN_HOST_CSR_TOP_BASE].vir_addr
#define REG_CONN_INFRA_BUS_CR_ADDR conn_reg.reg_base_addr[CONN_INFRA_BUS_CR_BASE].vir_addr
#define REG_CONN_INFRA_RGU_ADDR conn_reg.reg_base_addr[CONN_INFRA_RGU_BASE].vir_addr
#define REG_CONN_WT_SLP_CTL_REG_ADDR conn_reg.reg_base_addr[CONN_WT_SLP_CTL_REG_BASE].vir_addr
#define REG_INST2_CONN_WT_SLP_CTL_REG_ADDR conn_reg.reg_base_addr[INST2_CONN_WT_SLP_CTL_REG_BASE].vir_addr
#define REG_CONN_RF_SPI_MST_REG_ADDR conn_reg.reg_base_addr[CONN_RF_SPI_MST_REG_BASE].vir_addr
#define REG_INST2_CONN_RF_SPI_MST_REG_ADDR conn_reg.reg_base_addr[INST2_CONN_RF_SPI_MST_REG_BASE].vir_addr
#define REG_CONN_SEMAPHORE_ADDR conn_reg.reg_base_addr[CONN_SEMAPHORE_BASE].vir_addr
#define REG_CONN_AFE_CTL_ADDR conn_reg.reg_base_addr[CONN_AFE_CTL_BASE].vir_addr
#define REG_CONN_AFE_CTL_2ND_ADDR conn_reg.reg_base_addr[CONN_AFE_CTL_2ND_BASE].vir_addr
#define REG_WF_TOP_SLPPROT_ON_ADDR conn_reg.reg_base_addr[WF_TOP_SLPPROT_ON_BASE].vir_addr
#define REG_WF_TOP_CFG_ADDR conn_reg.reg_base_addr[WF_TOP_CFG_BASE].vir_addr
#define REG_WF_MCU_CONFIG_LS_ADDR conn_reg.reg_base_addr[WF_MCU_CONFIG_LS_BASE].vir_addr
#define REG_WF_MCU_BUS_CR_ADDR conn_reg.reg_base_addr[WF_MCU_BUS_CR_BASE].vir_addr
#define REG_WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_ADDR conn_reg.reg_base_addr[WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_BASE].vir_addr
#define REG_WF_TOP_CFG_ON_ADDR conn_reg.reg_base_addr[WF_TOP_CFG_ON_BASE].vir_addr
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
struct consys_base_addr* get_conn_reg_base_addr(void);
#endif /* _PLATFORM_MT7986_CONSYS_REG_H_ */

243
package/mtk/drivers/conninfra/src/platform/mt7986/include/mt7986_consys_reg_offset.h
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@ -1,243 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7986_CONSYS_REG_OFFSET_H_
#define _PLATFORM_MT7986_CONSYS_REG_OFFSET_H_
/**********************************************************************/
/* Base: TOP_MISC (0x11D1_0000) */
/**********************************************************************/
#define CONNSYS_MISC 0x0114
#define TOP_MISC_RSRV_ALL1_3 0x021C
/**********************************************************************/
/* Base: TOP RGU (0x1001_C000) */
/**********************************************************************/
#define TOP_RGU_WDT_SWSYSRST 0x0018
/**********************************************************************/
/* Base: GPIO (0x1001_F000) */
/**********************************************************************/
#define GPIO_MODE9 0x0390
#define GPIO_MODE10 0x03A0
#define GPIO_MODE11 0x03B0
#define GPIO_MODE12 0x03C0
/**********************************************************************/
/* Base: IOCFG_TR (0x11F0_0000) */
/**********************************************************************/
#define IOCFG_TR_DRV_CFG0 0x0000
#define IOCFG_TR_DRV_CFG1 0x0010
/**********************************************************************/
/* Base: IOCFG_TL (0x11F1_0000) */
/**********************************************************************/
#define IOCFG_TL_DRV_CFG0 0x0000
#define IOCFG_TL_DRV_CFG1 0x0010
/**********************************************************************/
/* Base: INFRACFG_AO (0x1000_3000) */
/**********************************************************************/
#define CONN2AP_GALS_SLPPROT 0x00D0
#define AP2CONN_GALS_SLPPROT 0x00D4
/**********************************************************************/
/* Base: CONN_INFRA_CFG (0x1800_1000) */
/**********************************************************************/
#define CONN_INFRA_CFG_IP_VERSION 0x0000
#define EFUSE 0x0020
#define ADIE_CTL 0x0030
#define CONN_INFRA_CFG_PWRCTRL0 0x0200
#define CONN_INFRA_CFG_RC_CTL_0 0x0380
#define OSC_CTL_0 0x0300
#define EMI_CTL_WF 0x0414
#define CONN_INFRA_WF_SLP_CTRL 0x0540
#define CONN_INFRA_WF_SLP_STATUS 0x0544
/**********************************************************************/
/* Base: CONN_INFRA_SYSRAM (0x1805_0000) */
/**********************************************************************/
#define SYSRAM_BASE_ADDR 0x0000
/**********************************************************************/
/* Base: CONN_INFRA_CLKGEN_ON_TOP (0x1800_9000) */
/**********************************************************************/
#define CKGEN_BUS_WPLL_DIV_1 0x0008
#define CKGEN_BUS_WPLL_DIV_2 0x000C
#define CKGEN_RFSPI_WPLL_DIV 0x0040
#define CKGEN_BUS 0x0A00
/**********************************************************************/
/* Base: CONN_HOST_CSR_TOP (0x1806_0000) */
/**********************************************************************/
#define CONN_INFRA_WAKEPU_TOP 0x01A0
#define CONN_INFRA_WAKEPU_WF 0x01A4
#define CONN2AP_REMAP_MCU_EMI 0x01C4
#define CONN2AP_REMAP_WF_PERI 0x01D4
#define DBG_DUMMY_3 0x02CC
/**********************************************************************/
/* Base: CONN_INFRA_BUS_CR (0x1800_E000) */
/**********************************************************************/
#define CONN_INFRA_BUS_OFF_TIMEOUT_CTRL 0x0300
#define CONN_INFRA_BUS_ON_TIMEOUT_CTRL 0x031C
#define CONN2AP_EMI_PATH_ADDR_START 0x0360
#define CONN2AP_EMI_PATH_ADDR_END 0x0364
/**********************************************************************/
/* Base: CONN_INFRA_RGU (0x1800_0000) */
/**********************************************************************/
#define WFSYS_ON_TOP_PWR_CTL 0x0010
#define BGFYS_ON_TOP_PWR_CTL 0x0020
#define SYSRAM_HWCTL_PDN 0x0050
#define SYSRAM_HWCTL_SLP 0x0054
#define WFSYS_CPU_SW_RST_B 0x0120
/**********************************************************************/
/* Base: CONN_WT_SLP_CTL_REG (0x1800_5000) */
/* Base: INST2_CONN_WT_SLP_CTL_REG (0x1808_5000) */
/**********************************************************************/
#define WB_WF_CK_ADDR 0x0070
#define WB_WF_WAKE_ADDR 0x0074
#define WB_WF_ZPS_ADDR 0x0078
#define WB_TOP_CK_ADDR 0x0084
#define WB_WF_B0_CMD_ADDR 0x008C
#define WB_WF_B1_CMD_ADDR 0x0090
#define WB_SLP_TOP_CK_0 0x0120
#define WB_SLP_TOP_CK_1 0x0124
/**********************************************************************/
/* Base: CONN_RF_SPI_MST_REG (0x1800_4000) */
/* Base: INST2_CONN_RF_SPI_MST_REG (0x1808_4000) */
/**********************************************************************/
#define SPI_STA 0x0000
#define SPI_WF_ADDR 0x0010
#define SPI_WF_WDAT 0x0014
#define SPI_WF_RDAT 0x0018
#define SPI_BT_ADDR 0x0020
#define SPI_BT_WDAT 0x0024
#define SPI_BT_RDAT 0x0028
#define SPI_FM_ADDR 0x0030
#define SPI_FM_WDAT 0x0034
#define SPI_FM_RDAT 0x0038
#define SPI_GPS_ADDR 0x0040
#define SPI_GPS_WDAT 0x0044
#define SPI_GPS_RDAT 0x0048
#define SPI_TOP_ADDR 0x0050
#define SPI_TOP_WDAT 0x0054
#define SPI_TOP_RDAT 0x0058
/**********************************************************************/
/* Base: CONN_SEMAPHORE_BASE (0x1807_0000) */
/**********************************************************************/
#define CONN_SEMA00_M2_OWN_STA 0x2000
#define CONN_SEMA00_M2_OWN_REL 0x2200
#define CONN_SEMA_OWN_BY_M0_STA_REP 0x0400
#define CONN_SEMA_OWN_BY_M1_STA_REP 0x1400
#define CONN_SEMA_OWN_BY_M2_STA_REP 0x2400
#define CONN_SEMA_OWN_BY_M3_STA_REP 0x3400
#define CONN_SEMA_OWN_BY_M4_STA_REP 0x4400
#define CONN_SEMA_OWN_BY_M5_STA_REP 0x5400
#define CONN_SEMA_OWN_BY_M6_STA_REP 0x6400
#define CONN_SEMA_OWN_BY_M7_STA_REP 0x7400
/**********************************************************************/
/* Base: CONN_AFE_CTL_BASE (0x1800_3000) */
/* Base: CONN_AFE_CTL_2ND_BASE (0x1808_3000) */
/**********************************************************************/
#define RG_DIG_EN_01 0x0000
#define RG_DIG_EN_02 0x0004
#define RG_DIG_EN_03 0x0008
#define RG_DIG_TOP_01 0x000C
#define RG_PLL_STB_TIME 0x00F4
/**********************************************************************/
/* Base: WF_TOP_SLPPROT_ON_BASE (0x8102_0000 remap to 0x184C_0000) */
/**********************************************************************/
#define WF_TOP_SLPPROT_ON_STATUS_READ 0x300C
/**********************************************************************/
/* Base: WF_TOP_CFG_BASE (0x8002_0000 remap to 0x184B_0000) */
/**********************************************************************/
#define WF_TOP_CFG_IP_VERSION 0x0010
/**********************************************************************/
/* Base: WF_MCU_CONFIG_LS_BASE (0x8800_0000 remap to 0x184F_0000) */
/**********************************************************************/
#define BUSHANGCR 0x0440
/**********************************************************************/
/* Base: WF_MCU_BUS_CR_BASE (0x830C_0XXX remap to 0x1840_0XXX) */
/**********************************************************************/
#define AP2WF_REMAP_1 0x0120
/**********************************************************************/
/* Base: WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_BASE (0x810F_0000 remap to 0x1850_0000) */
/**********************************************************************/
#define WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_WFMCU_PWA_CTRL0 0x0000
/**********************************************************************/
/* Base: WF_TOP_CFG_ON_BASE (0x8102_1000 remap to 0x184C_0000) */
/**********************************************************************/
#define ROMCODE_INDEX 0x1604
/**********************************************************************/
/* A-die CR */
/**********************************************************************/
#define ATOP_CHIP_ID 0x02C
#define ATOP_TOP_CLK_EN 0xA00
#define ATOP_RG_ENCAL_WBTAC_IF_SW 0x070
#define ATOP_RG_WRI_CK_SELECT 0x4AC
#define ATOP_EFUSE_CTRL_1 0x108
#define ATOP_EFUSE_CTRL_2 0x148
#define ATOP_EFUSE_CTRL_3 0x14C
#define ATOP_EFUSE_CTRL_4 0x15C
#define ATOP_EFUSE_RDATA0 0x130
#define ATOP_EFUSE_RDATA1 0x134
#define ATOP_EFUSE_RDATA2 0x138
#define ATOP_EFUSE_RDATA3 0x13C
#define ATOP_RG_EFUSE_CFG5 0x144
#define ATOP_THADC_ANALOG 0x3A6
#define ATOP_THADC_SLOP 0x3A7
#define ATOP_RG_TOP_THADC_BG 0x034
#define ATOP_RG_TOP_THADC_00 0x038
#define ATOP_XTAL_TRIM_FLOW 0x3AC
#define ATOP_XTAL_CR_C1_SEL_AXM_80M_OSC 0x390
#define ATOP_XTAL_CR_C1_SEL_AXM_40M_OSC 0x391
#define ATOP_XTAL_CR_C1_SEL_AXM_TRIM1_80M_OSC 0x398
#define ATOP_XTAL_CR_C1_SEL_AXM_TRIM1_40M_OSC 0x399
#define ATOP_RG_STRAP_PIN_IN 0x4FC
#define ATOP_RG_XO_01 0x65C
#define ATOP_RG_XO_03 0x664
#define ATOP_7975_XTAL_CALIBRATION 0x3A1
#define ATOP_7975_XTAL_TRIM2_COMPENSATION 0x3A2
#define ATOP_7975_XTAL_TRIM3_COMPENSATION 0x3A3
#define ATOP_7975_XTAL_TRIM4_COMPENSATION 0x3A4
#define ATOP_7975_XTAL_TRIM_FLOW 0x3A5
#define ATOP_7975_CR_C1_C2_A94 0xA94
#define ATOP_7975_CR_C1_C2_A18 0xA18
#define ATOP_7975_CR_C1_C2_A84 0xA84
#define ATOP_7975_CR_C1_C2_AA4 0xAA4
#define ATOP_7975_CO_CLK 0xA1C
#endif /* _PLATFORM_MT7986_CONSYS_REG_OFFSET_H_ */

72
package/mtk/drivers/conninfra/src/platform/mt7986/include/mt7986_emi.h
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7986_EMI_H_
#define _PLATFORM_MT7986_EMI_H_
#include "osal.h"
#include "emi_mng.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
struct consys_platform_emi_ops* get_consys_platform_emi_ops(void);
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
#endif /* _PLATFORM_MT7986_EMI_H_ */

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package/mtk/drivers/conninfra/src/platform/mt7986/include/mt7986_pmic.h
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7986_PMIC_H_
#define _PLATFORM_MT7986_PMIC_H_
#include "osal.h"
#include "pmic_mng.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
struct consys_platform_pmic_ops* get_consys_platform_pmic_ops(void);
#endif /* _PLATFORM_MT7986_PMIC_H_ */

64
package/mtk/drivers/conninfra/src/platform/mt7986/include/mt7986_pos.h
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#ifndef _PLATFORM_MT7986_POS_H_
#define _PLATFORM_MT7986_POS_H_
int consys_plt_hw_init(void);
int consys_xtal_ctrl_fast_mode(void);
int consys_sw_reset_ctrl(bool bassert);
int consys_tx_rx_bus_slp_prot_ctrl(bool enable);
void consys_set_if_pinmux(bool enable);
int consys_polling_chipid(void);
int consys_plt_adie_type_check(void);
int consys_plt_adie_type_cfg(void);
int consys_bus_clock_ctrl(enum consys_drv_type drv_type, unsigned int bus_clock);
int consys_emi_set_remapping_reg(void);
int consys_emi_set_region_protection(void);
int connsys_d_die_cfg(void);
int connsys_conninfra_sysram_hw_ctrl(void);
int connsys_spi_master_cfg(void);
int consys_sema_acquire_timeout(unsigned int index, unsigned int usec);
void consys_sema_release(unsigned int index);
int consys_spi_read(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data);
int consys_spi_write(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data);
int consys_spi_write_offset_range(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int value,
unsigned int reg_offset, unsigned int value_offset, unsigned int size);
int connsys_a_die_cfg(void);
int connsys_afe_wbg_cal(void);
int connsys_subsys_pll_initial(void);
int connsys_osc_legacy_mode(void);
int connsys_top_pwr_ctrl(void);
int connsys_conn_infra_bus_timeout(void);
int connsys_clkgen_wpll_hw_ctrl(void);
int consys_conninfra_top_wakeup(void);
int consys_conninfra_top_sleep(void);
int consys_adie_top_ck_en_on_off_ctrl(enum consys_drv_type type, unsigned char on);
int consys_conninfra_wf_wakeup(void);
int consys_conninfra_wf_sleep(void);
int consys_conn_wmcpu_sw_reset(bool bassert);
int consys_wf_bus_slp_prot_ctrl(bool enable);
int consys_wfsys_top_on_ctrl(bool enable);
int consys_wfsys_bus_slp_prot_check(bool enable);
int consys_wfsys_bus_timeout_ctrl(void);
int consys_wmcpu_idle_loop_check(void);
int consys_wpll_ctrl(bool enable);
int consys_conninfra_wf_req_clr(void);
#endif /* _PLATFORM_MT7986_POS_H_ */

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package/mtk/drivers/conninfra/src/platform/mt7986/mt7986.c
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include <linux/delay.h>
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include "osal.h"
#include "conninfra.h"
#include "consys_hw.h"
#include "consys_reg_mng.h"
#include "consys_reg_util.h"
#include "mt7986.h"
#include "mt7986_pos.h"
#include "emi_mng.h"
#include "mt7986_consys_reg.h"
#include "mt7986_consys_reg_offset.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
#define PLATFORM_SOC_CHIP 0x7986
#define CONN_IP_VER 0x02070000
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
struct consys_hw_ops_struct g_consys_hw_ops_mt7986 = {
/* HW init */
.consys_plt_hw_init = consys_plt_hw_init,
/* POS */
.consys_plt_xtal_ctrl_fast_mode = consys_xtal_ctrl_fast_mode,
.consys_plt_connsys_sw_reset_ctrl = consys_sw_reset_ctrl,
.consys_plt_set_if_pinmux = consys_set_if_pinmux,
.consys_plt_tx_rx_bus_slp_prot_ctrl = consys_tx_rx_bus_slp_prot_ctrl,
.consys_plt_polling_consys_chipid = consys_polling_chipid,
.consys_plt_bus_clock_ctrl = consys_bus_clock_ctrl,
.consys_plt_d_die_cfg = connsys_d_die_cfg,
.consys_plt_conninfra_sysram_hw_ctrl = connsys_conninfra_sysram_hw_ctrl,
.consys_plt_spi_master_cfg = connsys_spi_master_cfg,
.consys_plt_a_die_cfg = connsys_a_die_cfg,
.consys_plt_afe_wbg_cal = connsys_afe_wbg_cal,
.consys_plt_subsys_pll_initial = connsys_subsys_pll_initial,
.consys_plt_osc_legacy_mode = connsys_osc_legacy_mode,
.consys_plt_top_pwr_ctrl = connsys_top_pwr_ctrl,
.consys_plt_conn_infra_bus_timeout = connsys_conn_infra_bus_timeout,
.consys_plt_clkgen_wpll_hw_ctrl = connsys_clkgen_wpll_hw_ctrl,
.consys_plt_conninfra_wakeup = consys_conninfra_top_wakeup,
.consys_plt_conninfra_sleep = consys_conninfra_top_sleep,
.consys_plt_adie_top_ck_en_on_off_ctrl = consys_adie_top_ck_en_on_off_ctrl,
.consys_plt_conninfra_wf_wakeup = consys_conninfra_wf_wakeup,
.consys_plt_conninfra_wf_sleep = consys_conninfra_wf_sleep,
.consys_plt_conn_wmcpu_sw_reset = consys_conn_wmcpu_sw_reset,
.consys_plt_wf_bus_slp_prot_ctrl = consys_wf_bus_slp_prot_ctrl,
.consys_plt_wfsys_top_on_ctrl = consys_wfsys_top_on_ctrl,
.consys_plt_wfsys_bus_slp_prot_check = consys_wfsys_bus_slp_prot_check,
.consys_plt_wfsys_bus_timeout_ctrl = consys_wfsys_bus_timeout_ctrl,
.consys_plt_conn_wmcpu_idle_loop_check = consys_wmcpu_idle_loop_check,
.consys_plt_wpll_ctrl = consys_wpll_ctrl,
.consys_plt_conninfra_wf_req_clr = consys_conninfra_wf_req_clr,
/* load from dts */
/* TODO: mtcmos should move to a independent module */
.consys_plt_clk_get_from_dts = NULL,
.consys_plt_clk_detach = NULL,
/* clock */
.consys_plt_soc_chipid_get = consys_soc_chipid_get,
/* debug */
.consys_plt_get_hw_ver = consys_get_hw_ver,
.consys_plt_spi_read = consys_spi_read,
.consys_plt_spi_write = consys_spi_write,
.consys_plt_spi_clock_switch = NULL,
.consys_plt_power_state = NULL,
/* others */
.consys_plt_adie_type_check = consys_plt_adie_type_check,
.consys_plt_adie_type_cfg = consys_plt_adie_type_cfg,
};
/* For mt7986 */
extern struct consys_hw_ops_struct g_consys_hw_ops_mt7986;
extern struct consys_reg_mng_ops g_dev_consys_reg_ops_mt7986;
extern struct consys_platform_emi_ops g_consys_platform_emi_ops_mt7986;
extern struct consys_platform_pmic_ops g_consys_platform_pmic_ops_mt7986;
const struct conninfra_plat_data mt7986_plat_data = {
.chip_id = PLATFORM_SOC_CHIP,
.hw_ops = &g_consys_hw_ops_mt7986,
.reg_ops = &g_dev_consys_reg_ops_mt7986,
.platform_emi_ops = &g_consys_platform_emi_ops_mt7986,
.platform_pmic_ops = &g_consys_platform_pmic_ops_mt7986,
};
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
unsigned int consys_soc_chipid_get(void)
{
return PLATFORM_SOC_CHIP;
}
unsigned int consys_get_hw_ver(void)
{
return CONN_IP_VER;
}

172
package/mtk/drivers/conninfra/src/platform/mt7986/mt7986_consys_reg.c
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/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/random.h>
#include "consys_reg_mng.h"
#include "mt7986_consys_reg.h"
#include "mt7986_consys_reg_offset.h"
#include "consys_hw.h"
#include "consys_reg_util.h"
#define CFG_REG_LOAD_FROM_DTS_CTRL 0
static int consys_reg_init(struct platform_device *pdev);
static int consys_reg_deinit(void);
struct consys_base_addr conn_reg = {
.reg_base_addr[TOP_MISC_BASE] = {0x11D10000, 0x1000, 0},
.reg_base_addr[TOPRGU_BASE] = {0x1001C000, 0x1000, 0},
.reg_base_addr[GPIO_BASE] = {0x1001F000, 0x1000, 0},
.reg_base_addr[IOCFG_TR_BASE] = {0x11F00000, 0x1000, 0},
.reg_base_addr[IOCFG_TL_BASE] = {0x11F10000, 0x1000, 0},
.reg_base_addr[INFRACFG_AO_BASE] = {0x10003000, 0x1000, 0},
.reg_base_addr[CONN_INFRA_CFG_BASE] = {0x18001000, 0x1000, 0},
.reg_base_addr[CONN_INFRA_SYSRAM_BASE] = {0x18050000, 0x1000, 0},
.reg_base_addr[CONN_INFRA_CLKGEN_ON_TOP_BASE] = {0x18009000, 0x1000, 0},
.reg_base_addr[CONN_HOST_CSR_TOP_BASE] = {0x18060000, 0x1000, 0},
.reg_base_addr[CONN_INFRA_BUS_CR_BASE] = {0x1800E000, 0x1000, 0},
.reg_base_addr[CONN_INFRA_RGU_BASE] = {0x18000000, 0x1000, 0},
.reg_base_addr[CONN_WT_SLP_CTL_REG_BASE] = {0x18005000, 0x1000, 0},
.reg_base_addr[INST2_CONN_WT_SLP_CTL_REG_BASE] = {0x18085000, 0x1000, 0},
.reg_base_addr[CONN_RF_SPI_MST_REG_BASE] = {0x18004000, 0x1000, 0},
.reg_base_addr[INST2_CONN_RF_SPI_MST_REG_BASE] = {0x18084000, 0x1000, 0},
.reg_base_addr[CONN_SEMAPHORE_BASE] = {0x18070000, 0x10000, 0},
.reg_base_addr[CONN_AFE_CTL_BASE] = {0x18003000, 0x1000, 0},
.reg_base_addr[CONN_AFE_CTL_2ND_BASE] = {0x18083000, 0x1000, 0},
.reg_base_addr[WF_TOP_SLPPROT_ON_BASE] = {0x184C0000, 0x10000, 0},
.reg_base_addr[WF_TOP_CFG_BASE] = {0x184B0000, 0x1000, 0},
.reg_base_addr[WF_MCU_CONFIG_LS_BASE] = {0x184F0000, 0x1000, 0},
.reg_base_addr[WF_MCU_BUS_CR_BASE] = {0x18400000, 0x1000, 0},
.reg_base_addr[WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_BASE] = {0x18500000, 0x1000, 0},
.reg_base_addr[WF_TOP_CFG_ON_BASE] = {0x184C0000, 0x10000, 0},
};
const char* consys_base_addr_index_to_str[CONSYS_BASE_ADDR_MAX] = {
"TOP_MISC_BASE",
"TOPRGU_BASE",
"GPIO_BASE",
"IOCFG_TR_BASE",
"IOCFG_TL_BASE",
"INFRACFG_AO_BASE",
"CONN_INFRA_CFG_BASE",
"CONN_INFRA_SYSRAM_BASE",
"CONN_INFRA_CLKGEN_ON_TOP_BASE",
"CONN_HOST_CSR_TOP_BASE",
"CONN_INFRA_BUS_CR_BASE",
"CONN_INFRA_RGU_BASE",
"CONN_WT_SLP_CTL_REG_BASE",
"INST2_CONN_WT_SLP_CTL_REG_BASE",
"CONN_RF_SPI_MST_REG_BASE",
"INST2_CONN_RF_SPI_MST_REG_BASE",
"CONN_SEMAPHORE_BASE",
"CONN_AFE_CTL_BASE",
"CONN_AFE_CTL_2ND_BASE",
"WF_TOP_SLPPROT_ON_BASE",
"WF_TOP_CFG_BASE",
"WF_MCU_CONFIG_LS_BASE",
"WF_MCU_BUS_CR_BASE",
"WF_MCUSYS_INFRA_BUS_FULL_U_DEBUG_CTRL_AO_BASE",
"WF_TOP_CFG_ON_BASE"
};
struct consys_reg_mng_ops g_dev_consys_reg_ops_mt7986 = {
.consys_reg_mng_init = consys_reg_init,
.consys_reg_mng_deinit = consys_reg_deinit,
.consys_reg_mng_check_reable = NULL,
.consys_reg_mng_is_consys_reg = NULL,
.consys_reg_mng_is_bus_hang = NULL,
.consys_reg_mng_dump_bus_status = NULL,
.consys_reg_mng_dump_conninfra_status = NULL,
.consys_reg_mng_dump_cpupcr = NULL,
.consys_reg_mng_is_host_csr = NULL,
};
struct consys_base_addr* get_conn_reg_base_addr()
{
return &conn_reg;
}
static int consys_reg_init(struct platform_device *pdev)
{
int ret = -1;
struct device_node *node = NULL;
struct consys_reg_base_addr *base_addr = NULL;
int i = 0;
node = pdev->dev.of_node;
if (node) {
#if (CFG_REG_LOAD_FROM_DTS_CTRL == 1)
struct resource res;
int flag;
for (i = 0; i < CONSYS_BASE_ADDR_MAX; i++) {
base_addr = &conn_reg.reg_base_addr[i];
ret = of_address_to_resource(node, i, &res);
if (ret) {
pr_err("Get Reg Index(%d-%s) failed\n", i, consys_base_addr_index_to_str[i]);
continue;
}
base_addr->phy_addr = res.start;
base_addr->vir_addr = (unsigned long)of_iomap(node, i);
of_get_address(node, i, &(base_addr->size), &flag);
#if 0
pr_info("Get Index(%d-%s) phy_addr(0x%zx) vir_addr=(0x%zx) size=(0x%zx)\n",
i, consys_base_addr_index_to_str[i], base_addr->phy_addr,
base_addr->vir_addr, base_addr->size);
#endif
}
#else
for (i = 0; i < CONSYS_BASE_ADDR_MAX; i++) {
base_addr = &conn_reg.reg_base_addr[i];
if (base_addr->vir_addr == 0)
base_addr->vir_addr = (unsigned long)ioremap(base_addr->phy_addr, base_addr->size);
pr_info("Get Index(%d-%s) phy_addr(0x%zx) vir_addr=(0x%zx) size=(0x%zx)\n",
i, consys_base_addr_index_to_str[i], base_addr->phy_addr,
base_addr->vir_addr, base_addr->size);
}
#endif
} else {
pr_err("[%s] can't find CONSYS compatible node\n", __func__);
return ret;
}
return 0;
}
static int consys_reg_deinit(void)
{
int i = 0;
for (i = 0; i < CONSYS_BASE_ADDR_MAX; i++) {
if (conn_reg.reg_base_addr[i].vir_addr) {
pr_info("[%d] Unmap %s (0x%zx)\n", i, consys_base_addr_index_to_str[i],
conn_reg.reg_base_addr[i].vir_addr);
iounmap((void __iomem*)conn_reg.reg_base_addr[i].vir_addr);
conn_reg.reg_base_addr[i].vir_addr = 0;
}
}
return 0;
}

50
package/mtk/drivers/conninfra/src/platform/mt7986/mt7986_emi.c
View File

@ -1,50 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/of_reserved_mem.h>
#include "mt7986_emi.h"
#include "mt7986.h"
#include "mt7986_consys_reg.h"
#include "consys_hw.h"
#include "consys_reg_util.h"
#include "mt7986_pos.h"
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
unsigned int consys_emi_get_fw_emi_size(void)
{
return 0x100000;
}
struct consys_platform_emi_ops g_consys_platform_emi_ops_mt7986 = {
.consys_ic_emi_set_region_protection = consys_emi_set_region_protection,
.consys_ic_emi_set_remapping_reg = consys_emi_set_remapping_reg,
.consys_ic_emi_get_fw_emi_size = consys_emi_get_fw_emi_size,
};
struct consys_platform_emi_ops* get_consys_platform_emi_ops(void)
{
return &g_consys_platform_emi_ops_mt7986;
}

95
package/mtk/drivers/conninfra/src/platform/mt7986/mt7986_pmic.c
View File

@ -1,95 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/of_reserved_mem.h>
#include <linux/regulator/consumer.h>
#include <linux/notifier.h>
#include "consys_hw.h"
#include "consys_reg_util.h"
#include "osal.h"
#include "mt7986_pmic.h"
#include "mt7986_pos.h"
#include "mt7986_consys_reg.h"
#include "mt7986_consys_reg_offset.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
struct consys_platform_pmic_ops g_consys_platform_pmic_ops_mt7986 = {
.consys_pmic_get_from_dts = NULL,
.consys_pmic_common_power_ctrl = NULL,
.consys_pmic_wifi_power_ctrl = NULL,
.consys_pmic_bt_power_ctrl = NULL,
.consys_pmic_gps_power_ctrl = NULL,
.consys_pmic_fm_power_ctrl = NULL,
.consys_pmic_event_notifier = NULL,
};
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
struct consys_platform_pmic_ops* get_consys_platform_pmic_ops(void)
{
return &g_consys_platform_pmic_ops_mt7986;
}

2043
package/mtk/drivers/conninfra/src/platform/mt7986/mt7986_pos.c
View File

File diff suppressed because it is too large Load Diff

145
package/mtk/drivers/conninfra/src/platform/pmic_mng.c
View File

@ -1,145 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#include "consys_hw.h"
#include "pmic_mng.h"
#include "osal.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
const struct consys_platform_pmic_ops* consys_platform_pmic_ops = NULL;
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
int pmic_mng_init(
struct platform_device *pdev,
struct conninfra_dev_cb* dev_cb,
const struct conninfra_plat_data* plat_data)
{
if (consys_platform_pmic_ops == NULL) {
consys_platform_pmic_ops = (const struct consys_platform_pmic_ops*)plat_data->platform_pmic_ops;
}
if (consys_platform_pmic_ops && consys_platform_pmic_ops->consys_pmic_get_from_dts)
consys_platform_pmic_ops->consys_pmic_get_from_dts(pdev, dev_cb);
return 0;
}
int pmic_mng_deinit(void)
{
return 0;
}
int pmic_mng_common_power_ctrl(unsigned int enable)
{
int ret = 0;
if (consys_platform_pmic_ops &&
consys_platform_pmic_ops->consys_pmic_common_power_ctrl)
ret = consys_platform_pmic_ops->consys_pmic_common_power_ctrl(enable);
return ret;
}
int pmic_mng_wifi_power_ctrl(unsigned int enable)
{
int ret = 0;
if (consys_platform_pmic_ops &&
consys_platform_pmic_ops->consys_pmic_wifi_power_ctrl)
ret = consys_platform_pmic_ops->consys_pmic_wifi_power_ctrl(enable);
return ret;
}
int pmic_mng_bt_power_ctrl(unsigned int enable)
{
int ret = 0;
if (consys_platform_pmic_ops &&
consys_platform_pmic_ops->consys_pmic_bt_power_ctrl)
ret = consys_platform_pmic_ops->consys_pmic_bt_power_ctrl(enable);
return ret;
}
int pmic_mng_gps_power_ctrl(unsigned int enable)
{
int ret = 0;
if (consys_platform_pmic_ops &&
consys_platform_pmic_ops->consys_pmic_gps_power_ctrl)
ret = consys_platform_pmic_ops->consys_pmic_gps_power_ctrl(enable);
return ret;
}
int pmic_mng_fm_power_ctrl(unsigned int enable)
{
int ret = 0;
if (consys_platform_pmic_ops &&
consys_platform_pmic_ops->consys_pmic_fm_power_ctrl)
ret = consys_platform_pmic_ops->consys_pmic_fm_power_ctrl(enable);
return ret;
}
int pmic_mng_event_cb(unsigned int id, unsigned int event)
{
if (consys_platform_pmic_ops &&
consys_platform_pmic_ops->consys_pmic_event_notifier)
consys_platform_pmic_ops->consys_pmic_event_notifier(id, event);
return 0;
}

263
package/mtk/drivers/conninfra/src/src/conninfra.c
View File

@ -1,263 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#define pr_fmt(fmt) KBUILD_MODNAME "@(%s:%d) " fmt, __func__, __LINE__
#include <linux/platform_device.h>
#include <linux/cdev.h>
#include <linux/module.h>
#include <linux/fb.h>
#include <linux/workqueue.h>
#include <linux/delay.h>
#include <linux/ratelimit.h>
#include "conninfra.h"
#include "emi_mng.h"
#include "conninfra_core.h"
#include "consys_hw.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
#define CONNINFRA_RST_RATE_LIMIT 0
#if CONNINFRA_RST_RATE_LIMIT
DEFINE_RATELIMIT_STATE(g_rs, HZ, 1);
#define DUMP_LOG() if (__ratelimit(&g_rs)) \
pr_info("rst is ongoing\n")
#else
#define DUMP_LOG()
#endif
struct conninfra_rst_data {
enum consys_drv_type drv;
char *reason;
};
struct conninfra_rst_data rst_data;
void conninfra_get_emi_phy_addr(enum connsys_emi_type type, phys_addr_t* base, unsigned int *size)
{
struct consys_emi_addr_info* addr_info = emi_mng_get_phy_addr();
switch (type) {
case CONNSYS_EMI_FW:
if (base)
*base = addr_info->emi_ap_phy_base;
if (size)
*size = addr_info->fw_emi_size;
break;
default:
pr_err("Wrong EMI type: %d\n", type);
if (base)
*base = 0x0;
if (size)
*size = 0;
break;
}
}
EXPORT_SYMBOL(conninfra_get_emi_phy_addr);
int conninfra_pwr_on(enum consys_drv_type drv_type)
{
pr_info("[%s] drv=[%d]\n", __func__, drv_type);
if (conninfra_core_is_rst_locking()) {
DUMP_LOG();
return CONNINFRA_ERR_RST_ONGOING;
}
return conninfra_core_power_on(drv_type);
}
EXPORT_SYMBOL(conninfra_pwr_on);
int conninfra_pwr_off(enum consys_drv_type drv_type)
{
if (conninfra_core_is_rst_locking()) {
DUMP_LOG();
return CONNINFRA_ERR_RST_ONGOING;
}
return conninfra_core_power_off(drv_type);
}
EXPORT_SYMBOL(conninfra_pwr_off);
int conninfra_is_bus_hang(void)
{
if (conninfra_core_is_rst_locking()) {
DUMP_LOG();
return CONNINFRA_ERR_RST_ONGOING;
}
return conninfra_core_is_bus_hang();
}
EXPORT_SYMBOL(conninfra_is_bus_hang);
int conninfra_trigger_whole_chip_rst(enum consys_drv_type who, char *reason)
{
/* use schedule worker to trigger ??? */
/* so that function can be returned immediately */
int r;
r = conninfra_core_lock_rst();
if (r >= CHIP_RST_START) {
/* reset is ongoing */
pr_warn("r=[%d] chip rst is ongoing\n", r);
return 1;
}
pr_info("rst lock [%d] [%d] reason=%s\n", r, who, reason);
conninfra_core_trg_chip_rst(who, reason);
return 0;
}
EXPORT_SYMBOL(conninfra_trigger_whole_chip_rst);
int conninfra_sub_drv_ops_register(enum consys_drv_type type,
struct sub_drv_ops_cb *cb)
{
/* type validation */
if (type < 0 || type >= CONNDRV_TYPE_MAX) {
pr_err("incorrect drv type [%d]\n", type);
return -EINVAL;
}
pr_info("----\n");
conninfra_core_subsys_ops_reg(type, cb);
return 0;
}
EXPORT_SYMBOL(conninfra_sub_drv_ops_register);
int conninfra_sub_drv_ops_unregister(enum consys_drv_type type)
{
/* type validation */
if (type < 0 || type >= CONNDRV_TYPE_MAX) {
pr_err("[%s] incorrect drv type [%d]\n", __func__, type);
return -EINVAL;
}
pr_info("----\n");
conninfra_core_subsys_ops_unreg(type);
return 0;
}
EXPORT_SYMBOL(conninfra_sub_drv_ops_unregister);
int conninfra_spi_read(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int *data)
{
if (conninfra_core_is_rst_locking()) {
DUMP_LOG();
return CONNINFRA_ERR_RST_ONGOING;
}
if (subsystem >= SYS_SPI_MAX) {
pr_err("wrong subsys %d\n", subsystem);
return -EINVAL;
}
conninfra_core_spi_read(subsystem, addr, data);
return 0;
}
EXPORT_SYMBOL(conninfra_spi_read);
int conninfra_spi_write(enum sys_spi_subsystem subsystem, unsigned int addr, unsigned int data)
{
if (conninfra_core_is_rst_locking()) {
DUMP_LOG();
return CONNINFRA_ERR_RST_ONGOING;
}
if (subsystem >= SYS_SPI_MAX) {
pr_err("wrong subsys %d\n", subsystem);
return -EINVAL;
}
conninfra_core_spi_write(subsystem, addr, data);
return 0;
}
EXPORT_SYMBOL(conninfra_spi_write);
int conninfra_adie_top_ck_en_on(enum consys_drv_type type)
{
if (conninfra_core_is_rst_locking()) {
DUMP_LOG();
return CONNINFRA_ERR_RST_ONGOING;
}
return conninfra_core_adie_top_ck_en_on(type);
}
EXPORT_SYMBOL(conninfra_adie_top_ck_en_on);
int conninfra_adie_top_ck_en_off(enum consys_drv_type type)
{
if (conninfra_core_is_rst_locking()) {
DUMP_LOG();
return CONNINFRA_ERR_RST_ONGOING;
}
return conninfra_core_adie_top_ck_en_off(type);
}
EXPORT_SYMBOL(conninfra_adie_top_ck_en_off);
int conninfra_spi_clock_switch(enum connsys_spi_speed_type type)
{
return conninfra_core_spi_clock_switch(type);
}
EXPORT_SYMBOL(conninfra_spi_clock_switch);
int conninfra_debug_dump(void)
{
return conninfra_core_debug_dump();
}
EXPORT_SYMBOL(conninfra_debug_dump);

344
package/mtk/drivers/conninfra/src/src/conninfra_dev.c
View File

@ -1,344 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
/*! \file
* \brief Declaration of library functions
*
* Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
*/
#include <linux/cdev.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/workqueue.h>
#include "conninfra.h"
#include "conninfra_core.h"
#include "consys_hw.h"
#include "emi_mng.h"
/*******************************************************************************
* C O M P I L E R F L A G S
********************************************************************************
*/
/*******************************************************************************
* M A C R O S
********************************************************************************
*/
#define CONNINFRA_DEV_MAJOR 164
#define CONNINFRA_DEV_NUM 1
#define CONNINFRA_DRVIER_NAME "conninfra_drv"
#define CONNINFRA_DEVICE_NAME "conninfra_dev"
#define CONNINFRA_DEV_IOC_MAGIC 0xc2
#define CONNINFRA_IOCTL_GET_CHIP_ID _IOR(CONNINFRA_DEV_IOC_MAGIC, 0, int)
#define CONNINFRA_DEV_INIT_TO_MS (2 * 1000)
/*******************************************************************************
* E X T E R N A L R E F E R E N C E S
********************************************************************************
*/
/*******************************************************************************
* C O N S T A N T S
********************************************************************************
*/
enum conninfra_init_status {
CONNINFRA_INIT_NOT_START,
CONNINFRA_INIT_START,
CONNINFRA_INIT_DONE,
};
static int g_conninfra_init_status = CONNINFRA_INIT_NOT_START;
static wait_queue_head_t g_conninfra_init_wq;
/*******************************************************************************
* D A T A T Y P E S
********************************************************************************
*/
/*******************************************************************************
* F U N C T I O N D E C L A R A T I O N S
********************************************************************************
*/
static int conninfra_dev_open(struct inode *inode, struct file *file);
static int conninfra_dev_close(struct inode *inode, struct file *file);
static ssize_t conninfra_dev_read(struct file *filp, char __user *buf,
size_t count, loff_t *f_pos);
static ssize_t conninfra_dev_write(struct file *filp,
const char __user *buf, size_t count,
loff_t *f_pos);
static long conninfra_dev_unlocked_ioctl(
struct file *filp, unsigned int cmd, unsigned long arg);
#ifdef CONFIG_COMPAT
static long conninfra_dev_compat_ioctl(
struct file *filp, unsigned int cmd, unsigned long arg);
#endif /* CONFIG_COMPAT */
static int conninfra_dev_suspend_cb(void);
static int conninfra_dev_resume_cb(void);
static int conninfra_dev_pmic_event_cb(unsigned int, unsigned int);
/*******************************************************************************
* P U B L I C D A T A
********************************************************************************
*/
/*******************************************************************************
* P R I V A T E D A T A
********************************************************************************
*/
struct class *pConninfraClass;
struct device *pConninfraDev;
static struct cdev gConninfraCdev;
const struct file_operations gConninfraDevFops = {
.open = conninfra_dev_open,
.release = conninfra_dev_close,
.read = conninfra_dev_read,
.write = conninfra_dev_write,
.unlocked_ioctl = conninfra_dev_unlocked_ioctl,
#ifdef CONFIG_COMPAT
.compat_ioctl = conninfra_dev_compat_ioctl,
#endif /* CONFIG_COMPAT */
};
static int gConnInfraMajor = CONNINFRA_DEV_MAJOR;
/* screen on/off notification */
static struct conninfra_dev_cb gConninfraDevCb = {
.conninfra_suspend_cb = conninfra_dev_suspend_cb,
.conninfra_resume_cb = conninfra_dev_resume_cb,
.conninfra_pmic_event_notifier = conninfra_dev_pmic_event_cb,
};
/*******************************************************************************
* F U N C T I O N S
********************************************************************************
*/
int conninfra_dev_open(struct inode *inode, struct file *file)
{
static DEFINE_RATELIMIT_STATE(_rs, HZ, 1);
if (!wait_event_timeout(g_conninfra_init_wq, g_conninfra_init_status == CONNINFRA_INIT_DONE,
msecs_to_jiffies(CONNINFRA_DEV_INIT_TO_MS))) {
if (__ratelimit(&_rs)) {
pr_warn("wait_event_timeout (%d)ms,(%lu)jiffies,return -EIO\n",
CONNINFRA_DEV_INIT_TO_MS, msecs_to_jiffies(CONNINFRA_DEV_INIT_TO_MS));
}
return -EIO;
}
pr_info("open major %d minor %d (pid %d)\n",
imajor(inode), iminor(inode), current->pid);
return 0;
}
int conninfra_dev_close(struct inode *inode, struct file *file)
{
pr_info("close major %d minor %d (pid %d)\n",
imajor(inode), iminor(inode), current->pid);
return 0;
}
ssize_t conninfra_dev_read(struct file *filp, char __user *buf,
size_t count, loff_t *f_pos)
{
return 0;
}
ssize_t conninfra_dev_write(struct file *filp,
const char __user *buf, size_t count, loff_t *f_pos)
{
return 0;
}
static long conninfra_dev_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
int retval = 0;
pr_info("[%s] cmd (%d),arg(%ld)\n", __func__, cmd, arg);
switch (cmd) {
case CONNINFRA_IOCTL_GET_CHIP_ID:
retval = consys_hw_chipid_get();
break;
}
return retval;
}
#ifdef CONFIG_COMPAT
static long conninfra_dev_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
long ret;
pr_info("[%s] cmd (%d)\n", __func__, cmd);
ret = conninfra_dev_unlocked_ioctl(filp, cmd, arg);
return ret;
}
#endif /* CONFIG_COMPAT */
static int conninfra_dev_suspend_cb(void)
{
return 0;
}
static int conninfra_dev_resume_cb(void)
{
conninfra_core_dump_power_state();
return 0;
}
static int conninfra_dev_pmic_event_cb(unsigned int id, unsigned int event)
{
conninfra_core_pmic_event_cb(id, event);
return 0;
}
/************************************************************************/
static int conninfra_dev_init(void)
{
dev_t devID = MKDEV(gConnInfraMajor, 0);
int cdevErr = -1;
int iret = 0;
g_conninfra_init_status = CONNINFRA_INIT_START;
init_waitqueue_head((wait_queue_head_t *)&g_conninfra_init_wq);
iret = register_chrdev_region(devID, CONNINFRA_DEV_NUM, CONNINFRA_DRVIER_NAME);
if (iret) {
pr_err("fail to register chrdev\n");
g_conninfra_init_status = CONNINFRA_INIT_NOT_START;
return -1;
}
cdev_init(&gConninfraCdev, &gConninfraDevFops);
gConninfraCdev.owner = THIS_MODULE;
cdevErr = cdev_add(&gConninfraCdev, devID, CONNINFRA_DEV_NUM);
if (cdevErr) {
pr_err("cdev_add() fails (%d)\n", cdevErr);
goto err1;
}
pConninfraClass = class_create(THIS_MODULE, CONNINFRA_DEVICE_NAME);
if (IS_ERR(pConninfraClass)) {
pr_err("class create fail, error code(%ld)\n", PTR_ERR(pConninfraClass));
goto err1;
}
pConninfraDev = device_create(pConninfraClass, NULL, devID, NULL, CONNINFRA_DEVICE_NAME);
if (IS_ERR(pConninfraDev)) {
pr_err("device create fail, error code(%ld)\n", PTR_ERR(pConninfraDev));
goto err2;
}
iret = mtk_conninfra_drv_init(&gConninfraDevCb);
if (iret) {
pr_err("init consys_hw fail, ret = %d\n", iret);
g_conninfra_init_status = CONNINFRA_INIT_NOT_START;
return -2;
}
iret = conninfra_core_init();
if (iret) {
pr_err("conninfra init fail\n");
g_conninfra_init_status = CONNINFRA_INIT_NOT_START;
return -3;
}
pr_info("ConnInfra Dev: init (%d)\n", iret);
g_conninfra_init_status = CONNINFRA_INIT_DONE;
#ifdef CONFIG_CONNINFRA_AUTO_UP
iret = conninfra_core_power_on(CONNDRV_TYPE_CONNINFRA);
if (iret) {
pr_err("conninfra auto load power on fail\n");
return -4;
}
#endif /* CONFIG_CONNINFRA_AUTO_UP */
return 0;
err2:
pr_err("[conninfra_dev_init] err2\n");
if (pConninfraClass) {
class_destroy(pConninfraClass);
pConninfraClass = NULL;
}
err1:
pr_err("[conninfra_dev_init] err1\n");
if (cdevErr == 0)
cdev_del(&gConninfraCdev);
if (iret == 0) {
unregister_chrdev_region(devID, CONNINFRA_DEV_NUM);
gConnInfraMajor = -1;
}
g_conninfra_init_status = CONNINFRA_INIT_NOT_START;
return -2;
}
static void conninfra_dev_deinit(void)
{
dev_t dev = MKDEV(gConnInfraMajor, 0);
int iret = 0;
#ifdef CONFIG_CONNINFRA_AUTO_UP
iret = conninfra_core_power_off(CONNDRV_TYPE_CONNINFRA);
if (iret) {
pr_err("conninfra auto load power off fail\n");
}
#endif /* CONFIG_CONNINFRA_AUTO_UP */
g_conninfra_init_status = CONNINFRA_INIT_NOT_START;
iret = conninfra_core_deinit();
iret = mtk_conninfra_drv_deinit();
if (pConninfraDev) {
device_destroy(pConninfraClass, dev);
pConninfraDev = NULL;
}
if (pConninfraClass) {
class_destroy(pConninfraClass);
pConninfraClass = NULL;
}
cdev_del(&gConninfraCdev);
unregister_chrdev_region(dev, CONNINFRA_DEV_NUM);
pr_info("ConnInfra: platform init (%d)\n", iret);
}
module_init(conninfra_dev_init);
module_exit(conninfra_dev_deinit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Willy.Yu @ CTD/SE5/CS5");
module_param(gConnInfraMajor, uint, 0644);