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mediatek: initial Banana Pi R3 Mini support

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potatoigit 2023-11-04 20:03:32 +08:00 committed by hanwckf
parent 3773906267
commit 38c8c837fc
18 changed files with 10324 additions and 0 deletions
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8032
defconfig/mt7986-ax4200-bpir3_mini.config Normal file
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46
package/firmware/bpir3_mini-properties/Makefile Normal file
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@ -0,0 +1,46 @@
#
# Copyright (C) 2016 MediaTek
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
include $(TOPDIR)/rules.mk
PKG_NAME:=bpir3_mini-properties
PKG_RELEASE:=1
PKG_LICENSE:=GPL-2.0
include $(INCLUDE_DIR)/package.mk
define Package/bpir3_mini-properties
SECTION:=BPI-R3-MINI Properties
CATEGORY:=BPI-R3-MINI Properties
TITLE:=PHYs firmware & fan control for BPI-R3-MINI
MENU:=1
endef
define Package/bpir3_mini-properties/description
This package install PHYs firmware & fan control for BPI-R3-MINI.
endef
define Package/bpir3_mini-properties/config
endef
define Build/Compile
endef
define Package/bpir3_mini-properties/install
$(INSTALL_DIR) $(1)/etc/
$(INSTALL_DIR) $(1)/etc/init.d/
$(INSTALL_DIR) $(1)/etc/rc.d/
$(INSTALL_DIR) $(1)/lib/firmware/
$(INSTALL_BIN) ./files/etc/init.d/fanspeed $(1)/etc/init.d/
$(INSTALL_BIN) ./files/etc/rc.d/S99xfanspeed $(1)/etc/rc.d/
$(INSTALL_BIN) ./files/etc/init.d/ltecalling $(1)/etc/init.d/
$(INSTALL_BIN) ./files/etc/rc.d/S99xltecalling $(1)/etc/rc.d/
$(INSTALL_BIN) ./files/lib/firmware/EthMD32.dm.bin $(1)/lib/firmware/
$(INSTALL_BIN) ./files/lib/firmware/EthMD32.DSP.bin $(1)/lib/firmware/
endef
$(eval $(call BuildPackage,bpir3_mini-properties))

45
package/firmware/bpir3_mini-properties/files/etc/init.d/fanspeed Executable file
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#!/bin/sh /etc/rc.common
if [ ! -f /sys/class/pwm/pwmchip0/export ]; then
exit 0
fi
### enable fan ###
echo 0 > /sys/class/pwm/pwmchip0/export
echo 10000 > /sys/class/pwm/pwmchip0/pwm0/period
echo 7000 > /sys/class/pwm/pwmchip0/pwm0/duty_cycle
echo normal > /sys/class/pwm/pwmchip0/pwm0/polarity
echo 1 > /sys/class/pwm/pwmchip0/pwm0/enable
while :
do
sleep 20
result=`cat /sys/class/thermal/thermal_zone0/temp`
temperature=$((result))
#echo $temperature
if [ ${temperature} -le 58000 ]; then
echo 5000 > /sys/class/pwm/pwmchip0/pwm0/duty_cycle
fi
if [ ${temperature} -ge 58000 ]; then
echo 5000 > /sys/class/pwm/pwmchip0/pwm0/duty_cycle
fi
if [ ${temperature} -ge 62000 ]; then
echo 4500 > /sys/class/pwm/pwmchip0/pwm0/duty_cycle
fi
if [ ${temperature} -ge 75000 ]; then
echo 3700 > /sys/class/pwm/pwmchip0/pwm0/duty_cycle
fi
if [ ${temperature} -ge 80000 ]; then
echo 2500 > /sys/class/pwm/pwmchip0/pwm0/duty_cycle
fi
if [ ${temperature} -ge 85000 ]; then
echo 1000 > /sys/class/pwm/pwmchip0/pwm0/duty_cycle
fi
done

10
package/firmware/bpir3_mini-properties/files/etc/init.d/ltecalling Executable file
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#!/bin/sh /etc/rc.common
if [ ! -f /sys/class/gpio/export ]; then
exit 0
fi
### enable M.2 5G RM500U-CN Module Power ###
echo 431 > /sys/class/gpio/export
echo out > /sys/class/gpio/gpio431/direction
echo 0 > /sys/class/gpio/gpio431/value

1
package/firmware/bpir3_mini-properties/files/etc/rc.d/S99xfanspeed Symbolic link
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../init.d/fanspeed

1
package/firmware/bpir3_mini-properties/files/etc/rc.d/S99xltecalling Symbolic link
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../init.d/ltecalling

BIN
package/firmware/bpir3_mini-properties/files/lib/firmware/EthMD32.DSP.bin Normal file
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package/firmware/bpir3_mini-properties/files/lib/firmware/EthMD32.dm.bin Normal file
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15
package/kernel/linux/modules/netdevices.mk
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@ -241,6 +241,21 @@ endef
$(eval $(call KernelPackage,phy-realtek))
define KernelPackage/phy-air-en8811h
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Airoha EN8811H PHY Driver
KCONFIG:=CONFIG_AIR_EN8811H_PHY
DEPENDS:=+kmod-libphy
FILES:=$(LINUX_DIR)/drivers/net/phy/air_en8811h.ko
AUTOLOAD:=$(call AutoLoad,20,air_en8811h,1)
endef
define KernelPackage/phy-air-en8811h/description
Supports the Airoha EN8811h PHY.
endef
$(eval $(call KernelPackage,phy-air-en8811h))
define KernelPackage/swconfig
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=switch configuration API

437
package/mtk/drivers/wifi-profile/files/mt7986/mt7986-ax4200.dbdc.b0.dat Normal file
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#The word of "Default" must not be removed
Default
AccessControlList0=
AccessControlList1=
AccessControlList10=
AccessControlList11=
AccessControlList12=
AccessControlList13=
AccessControlList14=
AccessControlList15=
AccessControlList2=
AccessControlList3=
AccessControlList4=
AccessControlList5=
AccessControlList6=
AccessControlList7=
AccessControlList8=
AccessControlList9=
AccessPolicy0=0
AccessPolicy1=0
AccessPolicy10=0
AccessPolicy11=0
AccessPolicy12=0
AccessPolicy13=0
AccessPolicy14=0
AccessPolicy15=0
AccessPolicy2=0
AccessPolicy3=0
AccessPolicy4=0
AccessPolicy5=0
AccessPolicy6=0
AccessPolicy7=0
AccessPolicy8=0
AccessPolicy9=0
AckPolicy=0;0;0;0
APACM=0;0;0;0
APAifsn=3;7;1;1
ApCliAuthMode=
ApCliBssid=
ApCliDefaultKeyID=
ApCliEnable=0
ApCliEncrypType=
ApCliKey1Str=
ApCliKey1Str1=
ApCliKey1Type=
ApCliKey2Str=
ApCliKey2Str1=
ApCliKey2Type=
ApCliKey3Str=
ApCliKey3Str1=
ApCliKey3Type=
ApCliKey4Str=
ApCliKey4Str1=
ApCliKey4Type=
ApCliSsid=
ApCliWirelessMode=
ApCliWPAPSK=
ApCliWPAPSK1=
ApCliMuOfdmaDlEnable=0
ApCliMuOfdmaUlEnable=0
ApCliMuMimoDlEnable=0
ApCliMuMimoUlEnable=0
APCwmax=6;10;4;3
APCwmin=4;4;3;2
APSDCapable=1
APTxop=0;0;94;47
AuthMode=OPEN
AutoChannelSelect=0
AutoChannelSkipList=
AutoProvisionEn=0
BandSteering=0
BasicRate=15
BeaconPeriod=100
BFBACKOFFenable=0
BgndScanSkipCh=
BGProtection=0
BndStrgBssIdx=
BSSACM=0;0;0;0
BSSAifsn=3;7;2;2
BSSCwmax=10;10;4;3
BSSCwmin=4;4;3;2
BssidNum=1
BSSTxop=0;0;94;47
BW_Enable=0
BW_Guarantee_Rate=
BW_Maximum_Rate=
BW_Priority=
BW_Root=0
CalCacheApply=0
CarrierDetect=0
Channel=6
ChannelGrp=
CountryCode=US
CountryRegion=0
CountryRegionABand=9
CP_SUPPORT=2
CSPeriod=6
DBDC_MODE=1
DebugFlags=0
DefaultKeyID=1
DfsCalibration=0
DfsFalseAlarmPrevent=1
DfsZeroWait=0
DfsZeroWaitCacTime=255
DisableOLBC=0
DtimPeriod=1
E2pAccessMode=2
EAPifname=br-lan
EDCCAEnable=1
CBP_COMPENSATION=-6:-6:-6:-6
EncrypType=NONE
EthConvertMode=dongle
EtherTrafficBand=0
Ethifname=
ETxBfEnCond=1
FineAGC=0
FixedTxMode=
ForceRoamSupport=
FragThreshold=2346
FreqDelta=0
FtSupport=0
GreenAP=0
G_BAND_256QAM=1
HideSSID=0
HT_AMSDU=1
AMSDU_NUM=8
HT_AutoBA=1
HT_BADecline=0
HT_BAWinSize=256
HT_BSSCoexistence=1
HT_BW=1
HT_DisallowTKIP=1
HT_EXTCHA=1
HT_GI=1
HT_HTC=1
HT_LDPC=1
HT_LinkAdapt=0
HT_MCS=33
HT_MpduDensity=4
HT_OpMode=0
HT_PROTECT=1
HT_RDG=0
HT_RxStream=2
HT_STBC=1
HT_TxStream=2
IcapMode=0
idle_timeout_interval=0
IEEE80211H=1
IEEE8021X=0
IgmpSnEnable=0
ITxBfEn=0
Key1Str=
Key1Str1=
Key1Str10=
Key1Str11=
Key1Str12=
Key1Str13=
Key1Str14=
Key1Str15=
Key1Str16=
Key1Str2=
Key1Str3=
Key1Str4=
Key1Str5=
Key1Str6=
Key1Str7=
Key1Str8=
Key1Str9=
Key1Type=0
Key2Str=
Key2Str1=
Key2Str10=
Key2Str11=
Key2Str12=
Key2Str13=
Key2Str14=
Key2Str15=
Key2Str16=
Key2Str2=
Key2Str3=
Key2Str4=
Key2Str5=
Key2Str6=
Key2Str7=
Key2Str8=
Key2Str9=
Key2Type=0
Key3Str=
Key3Str1=
Key3Str10=
Key3Str11=
Key3Str12=
Key3Str13=
Key3Str14=
Key3Str15=
Key3Str16=
Key3Str2=
Key3Str3=
Key3Str4=
Key3Str5=
Key3Str6=
Key3Str7=
Key3Str8=
Key3Str9=
Key3Type=0
Key4Str=
Key4Str1=
Key4Str10=
Key4Str11=
Key4Str12=
Key4Str13=
Key4Str14=
Key4Str15=
Key4Str16=
Key4Str2=
Key4Str3=
Key4Str4=
Key4Str5=
Key4Str6=
Key4Str7=
Key4Str8=
Key4Str9=
Key4Type=0
LinkTestSupport=0
MACRepeaterEn=
MACRepeaterOuiMode=2
MeshAuthMode=
MeshAutoLink=0
MeshDefaultkey=0
MeshEncrypType=
MeshId=
MeshWEPKEY=
MeshWPAKEY=
MUTxRxEnable=1
NoForwarding=0
NoForwardingBTNBSSID=0
own_ip_addr=192.168.1.1
PcieAspm=0
PERCENTAGEenable=0
PhyRateLimit=0
PMFMFPC=1
PMFMFPR=0
PMFSHA256=0
PMKCachePeriod=10
PowerUpCckOfdm=0:0:0:0:0:0:0
PowerUpHT20=0:0:0:0:0:0:0
PowerUpHT40=0:0:0:0:0:0:0
PowerUpVHT160=0:0:0:0:0:0:0
PowerUpVHT20=0:0:0:0:0:0:0
PowerUpVHT40=0:0:0:0:0:0:0
PowerUpVHT80=0:0:0:0:0:0:0
PreAntSwitch=
PreAuth=0
PreAuthifname=br-lan
RadioLinkSelection=0
RadioOn=1
RADIUS_Acct_Key=
RADIUS_Acct_Port=1813
RADIUS_Acct_Server=
RADIUS_Key1=
RADIUS_Key10=
RADIUS_Key11=
RADIUS_Key12=
RADIUS_Key13=
RADIUS_Key14=
RADIUS_Key15=
RADIUS_Key16=
RADIUS_Key2=
RADIUS_Key3=
RADIUS_Key4=
RADIUS_Key5=
RADIUS_Key6=
RADIUS_Key7=
RADIUS_Key8=
RADIUS_Key9=
RADIUS_Port=1812
RADIUS_Server=0
RDRegion=
RED_Enable=1
RekeyInterval=3600
RekeyMethod=DISABLE
RRMEnable=1
RTSThreshold=2347
session_timeout_interval=0
ShortSlot=1
SkuTableIdx=0
SKUenable=0
SREnable=1
SRMode=0
SRDPDEnable=0
SRSDEnable=1
PPEnable=0
SSID=
SSID1=MTK_MT7986_AP_AX4200_2.4G
SSID10=
SSID11=
SSID12=
SSID13=
SSID14=
SSID15=
SSID16=
SSID2=
SSID3=
SSID4=
SSID5=
SSID6=
SSID7=
SSID8=
SSID9=
StationKeepAlive=0
StreamMode=0
StreamModeMac0=
StreamModeMac1=
StreamModeMac2=
StreamModeMac3=
TGnWifiTest=0
ThermalRecal=0
CCKTxStream=4
TWTSupport=1
TxBurst=1
TxPower=100
TxPreamble=1
VHT_BW=0
VHT_BW_SIGNAL=0
VHT_LDPC=1
VHT_Sec80_Channel=0
VHT_SGI=1
VHT_STBC=1
Vht1024QamSupport=0
VLANID=0
VLANPriority=0
VLANTag=0
VOW_Airtime_Ctrl_En=
VOW_Airtime_Fairness_En=1
VOW_BW_Ctrl=0
VOW_Group_Backlog=
VOW_Group_DWRR_Max_Wait_Time=
VOW_Group_DWRR_Quantum=
VOW_Group_Max_Airtime_Bucket_Size=
VOW_Group_Max_Rate=
VOW_Group_Max_Rate_Bucket_Size=
VOW_Group_Max_Ratio=
VOW_Group_Max_Wait_Time=
VOW_Group_Min_Airtime_Bucket_Size=
VOW_Group_Min_Rate=
VOW_Group_Min_Rate_Bucket_Size=
VOW_Group_Min_Ratio=
VOW_Rate_Ctrl_En=
VOW_Refill_Period=
VOW_RX_En=1
VOW_Sta_BE_DWRR_Quantum=
VOW_Sta_BK_DWRR_Quantum=
VOW_Sta_DWRR_Max_Wait_Time=
VOW_Sta_VI_DWRR_Quantum=
VOW_Sta_VO_DWRR_Quantum=
VOW_WATF_Enable=
VOW_WATF_MAC_LV0=
VOW_WATF_MAC_LV1=
VOW_WATF_MAC_LV2=
VOW_WATF_MAC_LV3=
VOW_WATF_Q_LV0=
VOW_WATF_Q_LV1=
VOW_WATF_Q_LV2=
VOW_WATF_Q_LV3=
VOW_WMM_Search_Rule_Band0=
VOW_WMM_Search_Rule_Band1=
WapiAsCertPath=
WapiAsIpAddr=
WapiAsPort=
Wapiifname=
WapiPsk1=
WapiPsk10=
WapiPsk11=
WapiPsk12=
WapiPsk13=
WapiPsk14=
WapiPsk15=
WapiPsk16=
WapiPsk2=
WapiPsk3=
WapiPsk4=
WapiPsk5=
WapiPsk6=
WapiPsk7=
WapiPsk8=
WapiPsk9=
WapiPskType=
WapiUserCertPath=
WCNTest=0
Wds0Key=
Wds1Key=
Wds2Key=
Wds3Key=
WdsEnable=0
WdsEncrypType=NONE
WdsList=
WdsPhyMode=0
WHNAT=1
WiFiTest=0
WirelessMode=16
WmmCapable=1
WPAPSK=
WPAPSK1=12345678
WPAPSK10=
WPAPSK11=
WPAPSK12=
WPAPSK13=
WPAPSK14=
WPAPSK15=
WPAPSK16=
WPAPSK2=
WPAPSK3=
WPAPSK4=
WPAPSK5=
WPAPSK6=
WPAPSK7=
WPAPSK8=
WPAPSK9=
WscConfMode=0
WscConfStatus=2
TxCmdMode=1
MuOfdmaDlEnable=1
MuOfdmaUlEnable=1
MuMimoDlEnable=1
MuMimoUlEnable=1
MapMode=0
IsICAPFW=0
KernelRps=1
MboSupport=1
BSSColorValue=255
QoSR1Enable=1
DscpPriMapEnable=0
ScsEnable=0
SCSEnable=1
QoSMgmtCapa=0
SwStaEnable=0

439
package/mtk/drivers/wifi-profile/files/mt7986/mt7986-ax4200.dbdc.b1.dat Normal file
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@ -0,0 +1,439 @@
#The word of "Default" must not be removed
Default
AccessControlList0=
AccessControlList1=
AccessControlList10=
AccessControlList11=
AccessControlList12=
AccessControlList13=
AccessControlList14=
AccessControlList15=
AccessControlList2=
AccessControlList3=
AccessControlList4=
AccessControlList5=
AccessControlList6=
AccessControlList7=
AccessControlList8=
AccessControlList9=
AccessPolicy0=0
AccessPolicy1=0
AccessPolicy10=0
AccessPolicy11=0
AccessPolicy12=0
AccessPolicy13=0
AccessPolicy14=0
AccessPolicy15=0
AccessPolicy2=0
AccessPolicy3=0
AccessPolicy4=0
AccessPolicy5=0
AccessPolicy6=0
AccessPolicy7=0
AccessPolicy8=0
AccessPolicy9=0
AckPolicy=0;0;0;0
APACM=0;0;0;0
APAifsn=3;7;1;1
ApCliAuthMode=
ApCliBssid=
ApCliDefaultKeyID=
ApCliEnable=0
ApCliEncrypType=
ApCliKey1Str=
ApCliKey1Str1=
ApCliKey1Type=
ApCliKey2Str=
ApCliKey2Str1=
ApCliKey2Type=
ApCliKey3Str=
ApCliKey3Str1=
ApCliKey3Type=
ApCliKey4Str=
ApCliKey4Str1=
ApCliKey4Type=
ApCliSsid=
ApCliWirelessMode=
ApCliWPAPSK=
ApCliWPAPSK1=
ApCliMuOfdmaDlEnable=0
ApCliMuOfdmaUlEnable=0
ApCliMuMimoDlEnable=0
ApCliMuMimoUlEnable=0
APCwmax=6;10;4;3
APCwmin=4;4;3;2
APSDCapable=1
APTxop=0;0;94;47
AuthMode=OPEN
AutoChannelSelect=0
AutoChannelSkipList=
AutoProvisionEn=0
BandSteering=0
BasicRate=15
BeaconPeriod=100
BFBACKOFFenable=0
BgndScanSkipCh=
BGProtection=0
BndStrgBssIdx=
BSSACM=0;0;0;0
BSSAifsn=3;7;2;2
BSSCwmax=10;10;4;3
BSSCwmin=4;4;3;2
BssidNum=1
BSSTxop=0;0;94;47
BW_Enable=0
BW_Guarantee_Rate=
BW_Maximum_Rate=
BW_Priority=
BW_Root=0
CalCacheApply=0
CarrierDetect=0
Channel=36
ChannelGrp=
CountryCode=US
CountryRegion=0
CountryRegionABand=9
CP_SUPPORT=2
CSPeriod=6
DBDC_MODE=1
DebugFlags=0
DefaultKeyID=1
DfsCalibration=0
DfsEnable=1
DfsFalseAlarmPrevent=1
DfsZeroWait=0
DfsZeroWaitCacTime=255
DfsDedicatedZeroWait=0
DfsZeroWaitDefault=0
DisableOLBC=0
DtimPeriod=1
E2pAccessMode=2
EAPifname=br-lan
EDCCAEnable=1
CBP_COMPENSATION=-6:-6:-6:-6
EncrypType=NONE
EthConvertMode=dongle
EtherTrafficBand=0
Ethifname=
ETxBfEnCond=1
FineAGC=0
FixedTxMode=
ForceRoamSupport=
FragThreshold=2346
FreqDelta=0
FtSupport=0
GreenAP=0
G_BAND_256QAM=1
HideSSID=0
HT_AMSDU=1
AMSDU_NUM=8
HT_AutoBA=1
HT_BADecline=0
HT_BAWinSize=256
HT_BSSCoexistence=1
HT_BW=1
HT_DisallowTKIP=1
HT_EXTCHA=1
HT_GI=1
HT_HTC=1
HT_LDPC=1
HT_LinkAdapt=0
HT_MCS=33
HT_MpduDensity=4
HT_OpMode=0
HT_PROTECT=1
HT_RDG=0
HT_RxStream=3
HT_STBC=1
HT_TxStream=3
IcapMode=0
idle_timeout_interval=0
IEEE80211H=1
IEEE8021X=0
IgmpSnEnable=0
ITxBfEn=0
Key1Str=
Key1Str1=
Key1Str10=
Key1Str11=
Key1Str12=
Key1Str13=
Key1Str14=
Key1Str15=
Key1Str16=
Key1Str2=
Key1Str3=
Key1Str4=
Key1Str5=
Key1Str6=
Key1Str7=
Key1Str8=
Key1Str9=
Key1Type=0
Key2Str=
Key2Str1=
Key2Str10=
Key2Str11=
Key2Str12=
Key2Str13=
Key2Str14=
Key2Str15=
Key2Str16=
Key2Str2=
Key2Str3=
Key2Str4=
Key2Str5=
Key2Str6=
Key2Str7=
Key2Str8=
Key2Str9=
Key2Type=0
Key3Str=
Key3Str1=
Key3Str10=
Key3Str11=
Key3Str12=
Key3Str13=
Key3Str14=
Key3Str15=
Key3Str16=
Key3Str2=
Key3Str3=
Key3Str4=
Key3Str5=
Key3Str6=
Key3Str7=
Key3Str8=
Key3Str9=
Key3Type=0
Key4Str=
Key4Str1=
Key4Str10=
Key4Str11=
Key4Str12=
Key4Str13=
Key4Str14=
Key4Str15=
Key4Str16=
Key4Str2=
Key4Str3=
Key4Str4=
Key4Str5=
Key4Str6=
Key4Str7=
Key4Str8=
Key4Str9=
Key4Type=0
LinkTestSupport=0
MACRepeaterEn=
MACRepeaterOuiMode=2
MeshAuthMode=
MeshAutoLink=0
MeshDefaultkey=0
MeshEncrypType=
MeshId=
MeshWEPKEY=
MeshWPAKEY=
MUTxRxEnable=1
NoForwarding=0
NoForwardingBTNBSSID=0
own_ip_addr=192.168.1.1
PcieAspm=0
PERCENTAGEenable=0
PhyRateLimit=0
PMFMFPC=1
PMFMFPR=0
PMFSHA256=0
PMKCachePeriod=10
PowerUpCckOfdm=0:0:0:0:0:0:0
PowerUpHT20=0:0:0:0:0:0:0
PowerUpHT40=0:0:0:0:0:0:0
PowerUpVHT160=0:0:0:0:0:0:0
PowerUpVHT20=0:0:0:0:0:0:0
PowerUpVHT40=0:0:0:0:0:0:0
PowerUpVHT80=0:0:0:0:0:0:0
PreAntSwitch=
PreAuth=0
PreAuthifname=br-lan
RadioLinkSelection=0
RadioOn=1
RADIUS_Acct_Key=
RADIUS_Acct_Port=1813
RADIUS_Acct_Server=
RADIUS_Key1=
RADIUS_Key10=
RADIUS_Key11=
RADIUS_Key12=
RADIUS_Key13=
RADIUS_Key14=
RADIUS_Key15=
RADIUS_Key16=
RADIUS_Key2=
RADIUS_Key3=
RADIUS_Key4=
RADIUS_Key5=
RADIUS_Key6=
RADIUS_Key7=
RADIUS_Key8=
RADIUS_Key9=
RADIUS_Port=1812
RADIUS_Server=0
RDRegion=
RED_Enable=1
RekeyInterval=3600
RekeyMethod=DISABLE
RRMEnable=1
RTSThreshold=2347
session_timeout_interval=0
ShortSlot=1
SkuTableIdx=0
SKUenable=0
SREnable=1
SRMode=0
SRDPDEnable=0
SRSDEnable=1
PPEnable=1
SSID=
SSID1=MTK_MT7986_AP_AX4200_5G
SSID10=
SSID11=
SSID12=
SSID13=
SSID14=
SSID15=
SSID16=
SSID2=
SSID3=
SSID4=
SSID5=
SSID6=
SSID7=
SSID8=
SSID9=
StationKeepAlive=0
StreamMode=0
StreamModeMac0=
StreamModeMac1=
StreamModeMac2=
StreamModeMac3=
TGnWifiTest=0
ThermalRecal=0
CCKTxStream=4
TWTSupport=1
TxBurst=1
TxPower=100
TxPreamble=1
VHT_BW=2
VHT_BW_SIGNAL=0
VHT_LDPC=1
VHT_Sec80_Channel=0
VHT_SGI=1
VHT_STBC=1
Vht1024QamSupport=1
VLANID=0
VLANPriority=0
VLANTag=0
VOW_Airtime_Ctrl_En=
VOW_Airtime_Fairness_En=1
VOW_BW_Ctrl=0
VOW_Group_Backlog=
VOW_Group_DWRR_Max_Wait_Time=
VOW_Group_DWRR_Quantum=
VOW_Group_Max_Airtime_Bucket_Size=
VOW_Group_Max_Rate=
VOW_Group_Max_Rate_Bucket_Size=
VOW_Group_Max_Ratio=
VOW_Group_Max_Wait_Time=
VOW_Group_Min_Airtime_Bucket_Size=
VOW_Group_Min_Rate=
VOW_Group_Min_Rate_Bucket_Size=
VOW_Group_Min_Ratio=
VOW_Rate_Ctrl_En=
VOW_Refill_Period=
VOW_RX_En=1
VOW_Sta_BE_DWRR_Quantum=
VOW_Sta_BK_DWRR_Quantum=
VOW_Sta_DWRR_Max_Wait_Time=
VOW_Sta_VI_DWRR_Quantum=
VOW_Sta_VO_DWRR_Quantum=
VOW_WATF_Enable=
VOW_WATF_MAC_LV0=
VOW_WATF_MAC_LV1=
VOW_WATF_MAC_LV2=
VOW_WATF_MAC_LV3=
VOW_WATF_Q_LV0=
VOW_WATF_Q_LV1=
VOW_WATF_Q_LV2=
VOW_WATF_Q_LV3=
VOW_WMM_Search_Rule_Band0=
VOW_WMM_Search_Rule_Band1=
WapiAsCertPath=
WapiAsIpAddr=
WapiAsPort=
Wapiifname=
WapiPsk1=
WapiPsk10=
WapiPsk11=
WapiPsk12=
WapiPsk13=
WapiPsk14=
WapiPsk15=
WapiPsk16=
WapiPsk2=
WapiPsk3=
WapiPsk4=
WapiPsk5=
WapiPsk6=
WapiPsk7=
WapiPsk8=
WapiPsk9=
WapiPskType=
WapiUserCertPath=
WCNTest=0
Wds0Key=
Wds1Key=
Wds2Key=
Wds3Key=
WdsEnable=0
WdsEncrypType=NONE
WdsList=
WdsPhyMode=0
WHNAT=1
WiFiTest=0
WirelessMode=17
WmmCapable=1
WPAPSK=
WPAPSK1=12345678
WPAPSK10=
WPAPSK11=
WPAPSK12=
WPAPSK13=
WPAPSK14=
WPAPSK15=
WPAPSK16=
WPAPSK2=
WPAPSK3=
WPAPSK4=
WPAPSK5=
WPAPSK6=
WPAPSK7=
WPAPSK8=
WPAPSK9=
WscConfMode=0
WscConfStatus=2
TxCmdMode=1
MuOfdmaDlEnable=1
MuOfdmaUlEnable=1
MuMimoDlEnable=1
MuMimoUlEnable=1
MapMode=0
IsICAPFW=0
BSSColorValue=255
MboSupport=1
QoSR1Enable=1
DscpPriMapEnable=0
ScsEnable=0
SCSEnable=1
QoSMgmtCapa=0
SwStaEnable=0

1
target/linux/mediatek/base-files/sbin/smp.sh
View File

@ -710,6 +710,7 @@ setup_model()
case $board in
xiaomi,redmi-router-ax6000* |\
bananapi,bpi-r3mini |\
*7986*)
MT7986_whnat $num_of_wifi
;;

43
target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986-spim-nand-partition-bpir3_mini.dtsi Normal file
View File

@ -0,0 +1,43 @@
/ {
nmbm_spim_nand {
compatible = "generic,nmbm";
#address-cells = <1>;
#size-cells = <1>;
lower-mtd-device = <&spi_nand>;
forced-create;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x0100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
};
factory: partition@180000 {
label = "zerofact0ry";
reg = <0x180000 0x0200000>;
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x0200000>;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x4000000>;
};
};
};
};

338
target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3mini-nand.dts Normal file
View File

@ -0,0 +1,338 @@
/dts-v1/;
#include "mt7986a.dtsi"
#include "mt7986a-pinctrl.dtsi"
#include "mt7986-spim-nand-partition-bpir3_mini.dtsi"
/ {
model = "Bananapi BPI-R3MINI";
compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a";
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
earlycon=uart8250,mmio32,0x11002000";
};
memory {
reg = <0 0x40000000 0 0x10000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sound {
compatible = "mediatek,mt7986-wm8960-machine";
mediatek,platform = <&afe>;
audio-routing = "Headphone", "HP_L",
"Headphone", "HP_R",
"LINPUT1", "AMIC",
"RINPUT1", "AMIC";
mediatek,audio-codec = <&wm8960>;
status = "okay";
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "disabled";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins>;
status = "okay";
/* MAC Address EEPROM */
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
address-bits = <8>;
page-size = <8>;
size = <256>;
};
wm8960: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
};
};
&auxadc {
status = "okay";
};
&watchdog {
status = "okay";
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
phy14: phy@14 {
/* EN8811H PHY ID */
compatible = "ethernet-phy-id03a2.a411";
/* PHY Address */
reg = <14>;
reset-gpios = <&pio 49 1>; /* GPIO49 */
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
phy-mode = "2500base-x";
full-duplex;
pause;
};
phy15: phy@15 {
/* EN8811H PHY ID */
compatible = "ethernet-phy-id03a2.a411";
/* PHY Address */
reg = <15>;
reset-gpios = <&pio 47 1>; /* GPIO47 */
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
phy-mode = "2500base-x";
full-duplex;
pause;
};
};
};
&hnat {
mtketh-wan = "eth1";
mtketh-lan = "eth0";
mtketh-max-gmac = <2>;
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
cs-gpios = <0>, <0>;
status = "okay";
spi_nor@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
};
spi_nand: spi_nand@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <20000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins_g2>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "okay";
};
&wbsys {
mediatek,mtd-eeprom = <&factory 0x0000>;
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
&pio {
mmc0_pins_default: mmc0-pins-50-to-61-default {
mux {
function = "flash";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <MTK_DRIVE_6mA>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <MTK_DRIVE_4mA>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-pins-50-to-61-uhs {
mux {
function = "flash";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <MTK_DRIVE_6mA>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <MTK_DRIVE_4mA>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
spi_flash_pins: spi-flash-pins-33-to-38 {
mux {
function = "flash";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <MTK_DRIVE_8mA>;
mediatek,pull-up-adv = <0>; /* bias-disable */
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <MTK_DRIVE_8mA>;
mediatek,pull-down-adv = <0>; /* bias-disable */
};
};
wf_2g_5g_pins: wf_2g_5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <MTK_DRIVE_4mA>;
};
};
wf_dbdc_pins: wf_dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <MTK_DRIVE_4mA>;
};
};
};

19
target/linux/mediatek/image/mt7986.mk
View File

@ -385,3 +385,22 @@ define Device/xiaomi_redmi-router-ax6000-stock
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
TARGET_DEVICES += xiaomi_redmi-router-ax6000-stock
define Device/BPI-R3MINI-NAND
DEVICE_VENDOR := Banana Pi
DEVICE_MODEL := Banana Pi R3MINI
DEVICE_TITLE := MTK7986a BPI R3MINI NAND
DEVICE_DTS := mt7986a-bananapi-bpi-r3mini-nand
DEVICE_DTS_DIR := $(DTS_DIR)/mediatek
DEVICE_PACKAGES := kmod-phy-air-en8811h bpir3_mini-properties
SUPPORTED_DEVICES := bananapi,bpi-r3mini
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 65536k
KERNEL_IN_UBI := 1
IMAGES += factory.bin
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
TARGET_DEVICES += BPI-R3MINI-NAND

3
target/linux/mediatek/mt7986/base-files/etc/board.d/02_network
View File

@ -24,6 +24,9 @@ mediatek_setup_interfaces()
ucidef_add_switch "switch0" \
"1:lan:4" "2:lan:3" "3:lan:2" "4:wan" "6u@eth0" "5u@eth1"
;;
bananapi,bpi-r3mini)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
;;
*)
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 lan4 lan5" eth1
;;

2
target/linux/mediatek/mt7986/base-files/lib/upgrade/platform.sh
View File

@ -146,6 +146,7 @@ platform_do_upgrade() {
redmi_ax6000_nand_upgrade_tar "$1"
;;
xiaomi,redmi-router-ax6000 |\
bananapi,bpi-r3mini |\
*snand*)
nand_do_upgrade "$1"
;;
@ -168,6 +169,7 @@ platform_check_image() {
case "$board" in
xiaomi,redmi-router-ax6000* |\
bananapi,bpi-r3mini |\
*snand* |\
*emmc*)
# tar magic `ustar`

892
target/linux/mediatek/patches-5.4/9999-mt7986a-bananapi-bpi-r3-air_en8811-2.5G-phy.patch Normal file
View File

@ -0,0 +1,892 @@
diff -urN a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
--- a/drivers/net/phy/air_en8811h.c 1970-01-01 08:00:00.000000000 +0800
+++ b/drivers/net/phy/air_en8811h.c 2023-06-14 14:02:38.474875084 +0800
@@ -0,0 +1,706 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/* FILE NAME: air_en8811h.c
+ * PURPOSE:
+ * EN8811H phy driver for Linux
+ * NOTES:
+ *
+ */
+
+/* INCLUDE FILE DECLARATIONS
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mii.h>
+#include <linux/phy.h>
+#include <linux/delay.h>
+#include <linux/ethtool.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/firmware.h>
+#include <linux/crc32.h>
+
+#include "air_en8811h.h"
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+#define phydev_mdio_bus(_dev) (_dev->bus)
+#define phydev_addr(_dev) (_dev->addr)
+#define phydev_dev(_dev) (&_dev->dev)
+#else
+#define phydev_mdio_bus(_dev) (_dev->mdio.bus)
+#define phydev_addr(_dev) (_dev->mdio.addr)
+#define phydev_dev(_dev) (&_dev->mdio.dev)
+#endif
+
+MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
+MODULE_AUTHOR("Airoha");
+MODULE_LICENSE("GPL");
+
+/*
+GPIO5 <-> BASE_T_LED0,
+GPIO4 <-> BASE_T_LED1,
+GPIO3 <-> BASE_T_LED2,
+*/
+/* User-defined.B */
+#define AIR_LED_SUPPORT
+#ifdef AIR_LED_SUPPORT
+static const AIR_BASE_T_LED_CFG_T led_cfg[3] =
+{
+ /*
+ * LED Enable, GPIO, LED Polarity, LED ON, LED Blink
+ */
+ {LED_ENABLE, AIR_LED0_GPIO5, AIR_ACTIVE_HIGH, BASE_T_LED0_ON_CFG, BASE_T_LED0_BLK_CFG}, /* BASE-T LED0 */
+ {LED_ENABLE, AIR_LED1_GPIO4, AIR_ACTIVE_HIGH, BASE_T_LED1_ON_CFG, BASE_T_LED1_BLK_CFG}, /* BASE-T LED1 */
+ {LED_ENABLE, AIR_LED2_GPIO3, AIR_ACTIVE_HIGH, BASE_T_LED2_ON_CFG, BASE_T_LED2_BLK_CFG}, /* BASE-T LED2 */
+};
+static const u16 led_dur = UNIT_LED_BLINK_DURATION << AIR_LED_BLK_DUR_64M;
+#endif
+/* User-defined.E */
+
+/************************************************************************
+* F U N C T I O N S
+************************************************************************/
+#if 0
+/* Airoha MII read function */
+static int air_mii_cl22_read(struct mii_bus *ebus, unsigned int phy_addr,unsigned int phy_register)
+{
+ int read_data;
+ read_data = mdiobus_read(ebus, phy_addr, phy_register);
+ return read_data;
+}
+#endif
+/* Airoha MII write function */
+static int air_mii_cl22_write(struct mii_bus *ebus, unsigned int phy_addr, unsigned int phy_register,unsigned int write_data)
+{
+ int ret = 0;
+ ret = mdiobus_write(ebus, phy_addr, phy_register, write_data);
+ return ret;
+}
+
+static int air_mii_cl45_read(struct phy_device *phydev, int devad, u16 reg)
+{
+ int ret = 0;
+ int data;
+ struct device *dev = phydev_dev(phydev);
+ ret = phy_write(phydev, MII_MMD_ACC_CTL_REG, devad);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return INVALID_DATA;
+ }
+ ret = phy_write(phydev, MII_MMD_ADDR_DATA_REG, reg);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return INVALID_DATA;
+ }
+ ret = phy_write(phydev, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return INVALID_DATA;
+ }
+ data = phy_read(phydev, MII_MMD_ADDR_DATA_REG);
+ return data;
+}
+
+static int air_mii_cl45_write(struct phy_device *phydev, int devad, u16 reg, u16 write_data)
+{
+ int ret = 0;
+ struct device *dev = phydev_dev(phydev);
+ ret = phy_write(phydev, MII_MMD_ACC_CTL_REG, devad);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, MII_MMD_ADDR_DATA_REG, reg);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, MII_MMD_ADDR_DATA_REG, write_data);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+/* Use default PBUS_PHY_ID */
+/* EN8811H PBUS write function */
+static int air_pbus_reg_write(struct phy_device *phydev, unsigned long pbus_address, unsigned long pbus_data)
+{
+ struct mii_bus *mbus = phydev_mdio_bus(phydev);
+ int addr = phydev_addr(phydev);
+ int ret = 0;
+ ret = air_mii_cl22_write(mbus, (addr + 8), 0x1F, (unsigned int)(pbus_address >> 6));
+ AIR_RTN_ERR(ret);
+ ret = air_mii_cl22_write(mbus, (addr + 8), (unsigned int)((pbus_address >> 2) & 0xf), (unsigned int)(pbus_data & 0xFFFF));
+ AIR_RTN_ERR(ret);
+ ret = air_mii_cl22_write(mbus, (addr + 8), 0x10, (unsigned int)(pbus_data >> 16));
+ AIR_RTN_ERR(ret);
+ return 0;
+}
+
+/* EN8811H BUCK write function */
+static int air_buckpbus_reg_write(struct phy_device *phydev, unsigned long pbus_address, unsigned int pbus_data)
+{
+ int ret = 0;
+ struct device *dev = phydev_dev(phydev);
+ ret = phy_write(phydev, 0x1F, (unsigned int)4); /* page 4 */
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, 0x10, (unsigned int)0);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, 0x11, (unsigned int)((pbus_address >> 16) & 0xffff));
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, 0x12, (unsigned int)(pbus_address & 0xffff));
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, 0x13, (unsigned int)((pbus_data >> 16) & 0xffff));
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, 0x14, (unsigned int)(pbus_data & 0xffff));
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, 0x1F, 0);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+/* EN8811H BUCK read function */
+static unsigned int air_buckpbus_reg_read(struct phy_device *phydev, unsigned long pbus_address)
+{
+ unsigned int pbus_data = 0, pbus_data_low, pbus_data_high;
+ int ret = 0;
+ struct device *dev = phydev_dev(phydev);
+ ret = phy_write(phydev, 0x1F, (unsigned int)4); /* page 4 */
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return PBUS_INVALID_DATA;
+ }
+ ret = phy_write(phydev, 0x10, (unsigned int)0);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return PBUS_INVALID_DATA;
+ }
+ ret = phy_write(phydev, 0x15, (unsigned int)((pbus_address >> 16) & 0xffff));
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return PBUS_INVALID_DATA;
+ }
+ ret = phy_write(phydev, 0x16, (unsigned int)(pbus_address & 0xffff));
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return PBUS_INVALID_DATA;
+ }
+
+ pbus_data_high = phy_read(phydev, 0x17);
+ pbus_data_low = phy_read(phydev, 0x18);
+ pbus_data = (pbus_data_high << 16) + pbus_data_low;
+ ret = phy_write(phydev, 0x1F, 0);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ return pbus_data;
+}
+
+static int MDIOWriteBuf(struct phy_device *phydev, unsigned long address, const struct firmware *fw)
+{
+ unsigned int write_data, offset ;
+ int ret = 0;
+ struct device *dev = phydev_dev(phydev);
+ ret = phy_write(phydev, 0x1F, (unsigned int)4); /* page 4 */
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, 0x10, (unsigned int)0x8000); /* address increment*/
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, 0x11, (unsigned int)((address >> 16) & 0xffff));
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ ret = phy_write(phydev, 0x12, (unsigned int)(address & 0xffff));
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+
+ for (offset = 0; offset < fw->size; offset += 4)
+ {
+ write_data = (fw->data[offset + 3] << 8) | fw->data[offset + 2];
+ ret = phy_write(phydev, 0x13, write_data);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ write_data = (fw->data[offset + 1] << 8) | fw->data[offset];
+ ret = phy_write(phydev, 0x14, write_data);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ }
+ ret = phy_write(phydev, 0x1F, (unsigned int)0);
+ if (ret < 0) {
+ dev_err(dev, "phy_write, ret: %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int en8811h_load_firmware(struct phy_device *phydev)
+{
+ struct device *dev = phydev_dev(phydev);
+ const struct firmware *fw;
+ const char *firmware;
+ int ret = 0;
+ unsigned int crc32;
+ u32 pbus_value = 0;
+
+ ret = air_buckpbus_reg_write(phydev, 0x0f0018, 0x0);
+ AIR_RTN_ERR(ret);
+ pbus_value = air_buckpbus_reg_read(phydev, 0x800000);
+ pbus_value |= BIT(11);
+ ret = air_buckpbus_reg_write(phydev, 0x800000, pbus_value);
+ AIR_RTN_ERR(ret);
+ firmware = EN8811H_MD32_DM;
+ ret = request_firmware_direct(&fw, firmware, dev);
+ if (ret < 0) {
+ dev_err(dev, "failed to load firmware %s, ret: %d\n", firmware, ret);
+ return ret;
+ }
+ crc32 = ~crc32(~0, fw->data, fw->size);
+ dev_info(dev, "%s: crc32=0x%x\n", firmware, crc32);
+ /* Download DM */
+ ret = MDIOWriteBuf(phydev, 0x00000000, fw);
+ release_firmware(fw);
+ if (ret < 0) {
+ dev_err(dev, "MDIOWriteBuf 0x00000000 fail, ret: %d\n", ret);
+ return ret;
+ }
+
+ firmware = EN8811H_MD32_DSP;
+ ret = request_firmware_direct(&fw, firmware, dev);
+ if (ret < 0) {
+ dev_info(dev, "failed to load firmware %s, ret: %d\n", firmware, ret);
+ return ret;
+ }
+ crc32 = ~crc32(~0, fw->data, fw->size);
+ dev_info(dev, "%s: crc32=0x%x\n", firmware, crc32);
+ /* Download PM */
+ ret = MDIOWriteBuf(phydev, 0x00100000, fw);
+ release_firmware(fw);
+ if (ret < 0) {
+ dev_err(dev, "MDIOWriteBuf 0x00100000 fail , ret: %d\n", ret);
+ return ret;
+ }
+
+ pbus_value = air_buckpbus_reg_read(phydev, 0x800000);
+ pbus_value &= ~BIT(11);
+ ret = air_buckpbus_reg_write(phydev, 0x800000, pbus_value);
+ AIR_RTN_ERR(ret);
+ ret = air_buckpbus_reg_write(phydev, 0x0f0018, 0x01);
+ AIR_RTN_ERR(ret);
+ return 0;
+}
+
+#ifdef AIR_LED_SUPPORT
+static int airoha_led_set_usr_def(struct phy_device *phydev, u8 entity, int polar,
+ u16 on_evt, u16 blk_evt)
+{
+ int ret = 0;
+ if (AIR_ACTIVE_HIGH == polar) {
+ on_evt |= LED_ON_POL;
+ } else {
+ on_evt &= ~LED_ON_POL ;
+ }
+ ret = air_mii_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), on_evt | LED_ON_EN);
+ AIR_RTN_ERR(ret);
+ ret = air_mii_cl45_write(phydev, 0x1f, LED_BLK_CTRL(entity), blk_evt);
+ AIR_RTN_ERR(ret);
+ return 0;
+}
+
+static int airoha_led_set_mode(struct phy_device *phydev, u8 mode)
+{
+ u16 cl45_data;
+ int err = 0;
+ struct device *dev = phydev_dev(phydev);
+ cl45_data = air_mii_cl45_read(phydev, 0x1f, LED_BCR);
+ switch (mode) {
+ case AIR_LED_MODE_DISABLE:
+ cl45_data &= ~LED_BCR_EXT_CTRL;
+ cl45_data &= ~LED_BCR_MODE_MASK;
+ cl45_data |= LED_BCR_MODE_DISABLE;
+ break;
+ case AIR_LED_MODE_USER_DEFINE:
+ cl45_data |= LED_BCR_EXT_CTRL;
+ cl45_data |= LED_BCR_CLK_EN;
+ break;
+ default:
+ dev_err(dev, "LED mode%d is not supported!\n", mode);
+ return -EINVAL;
+ }
+ err = air_mii_cl45_write(phydev, 0x1f, LED_BCR, cl45_data);
+ AIR_RTN_ERR(err);
+ return 0;
+}
+
+static int airoha_led_set_state(struct phy_device *phydev, u8 entity, u8 state)
+{
+ u16 cl45_data = 0;
+ int err;
+
+ cl45_data = air_mii_cl45_read(phydev, 0x1f, LED_ON_CTRL(entity));
+ if (LED_ENABLE == state) {
+ cl45_data |= LED_ON_EN;
+ } else {
+ cl45_data &= ~LED_ON_EN;
+ }
+
+ err = air_mii_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), cl45_data);
+ AIR_RTN_ERR(err);
+ return 0;
+}
+
+static int en8811h_led_init(struct phy_device *phydev)
+{
+
+ unsigned long led_gpio = 0, reg_value = 0;
+ u16 cl45_data = led_dur;
+ int ret = 0, led_id;
+ struct device *dev = phydev_dev(phydev);
+ ret = air_mii_cl45_write(phydev, 0x1f, LED_BLK_DUR, cl45_data);
+ AIR_RTN_ERR(ret);
+ cl45_data >>= 1;
+ ret = air_mii_cl45_write(phydev, 0x1f, LED_ON_DUR, cl45_data);
+ AIR_RTN_ERR(ret);
+ ret = airoha_led_set_mode(phydev, AIR_LED_MODE_USER_DEFINE);
+ if (ret != 0) {
+ dev_err(dev, "LED fail to set mode, ret %d !\n", ret);
+ return ret;
+ }
+ for(led_id = 0; led_id < EN8811H_LED_COUNT; led_id++)
+ {
+ /* LED0 <-> GPIO5, LED1 <-> GPIO4, LED0 <-> GPIO3 */
+ if (led_cfg[led_id].gpio != (led_id + (AIR_LED0_GPIO5 - (2 * led_id))))
+ {
+ dev_err(dev, "LED%d uses incorrect GPIO%d !\n", led_id, led_cfg[led_id].gpio);
+ return -EINVAL;
+ }
+ ret = airoha_led_set_state(phydev, led_id, led_cfg[led_id].en);
+ if (ret != 0)
+ {
+ dev_err(dev, "LED fail to set state, ret %d !\n", ret);
+ return ret;
+ }
+ if (LED_ENABLE == led_cfg[led_id].en)
+ {
+ led_gpio |= BIT(led_cfg[led_id].gpio);
+ ret = airoha_led_set_usr_def(phydev, led_id, led_cfg[led_id].pol, led_cfg[led_id].on_cfg, led_cfg[led_id].blk_cfg);
+ if (ret != 0)
+ {
+ dev_err(dev, "LED fail to set default, ret %d !\n", ret);
+ return ret;
+ }
+ }
+ }
+ reg_value = air_buckpbus_reg_read(phydev, 0xcf8b8) | led_gpio;
+ ret = air_buckpbus_reg_write(phydev, 0xcf8b8, reg_value);
+ AIR_RTN_ERR(ret);
+
+ dev_info(dev, "LED initialize OK !\n");
+ return 0;
+}
+#endif /* AIR_LED_SUPPORT */
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 5, 0))
+static int en8811h_get_features(struct phy_device *phydev)
+{
+ int ret;
+ struct device *dev = phydev_dev(phydev);
+ dev_info(dev, "%s()\n", __func__);
+ ret = air_pbus_reg_write(phydev, 0xcf928 , 0x0);
+ AIR_RTN_ERR(ret);
+ ret = genphy_read_abilities(phydev);
+ if (ret)
+ return ret;
+
+ /* EN8811H supports 100M/1G/2.5G speed. */
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
+ phydev->supported);
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+ phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
+ phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
+ phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
+ phydev->supported);
+ return 0;
+}
+#endif
+static int en8811h_phy_probe(struct phy_device *phydev)
+{
+ int ret = 0;
+ int reg_value, pid1 = 0, pid2 = 0;
+ u32 pbus_value = 0, retry;
+ struct device *dev = phydev_dev(phydev);
+
+ ret = air_pbus_reg_write(phydev, 0xcf928 , 0x0);
+ AIR_RTN_ERR(ret);
+ pid1 = phy_read(phydev, MII_PHYSID1);
+ if (pid1 < 0)
+ return pid1;
+ pid2 = phy_read(phydev, MII_PHYSID2);
+ if (pid2 < 0)
+ return pid2;
+ dev_info(dev, "PHY = %x - %x\n", pid1, pid2);
+ if ((EN8811H_PHY_ID1 != pid1) || (EN8811H_PHY_ID2 != pid2))
+ {
+ dev_err(dev, "EN8811H dose not exist !\n");
+ return -ENODEV;
+ }
+ ret = en8811h_load_firmware(phydev);
+ if (ret)
+ {
+ dev_err(dev,"EN8811H load firmware fail.\n");
+ return ret;
+ }
+ retry = MAX_RETRY;
+ do {
+ mdelay(300);
+ reg_value = air_mii_cl45_read(phydev, 0x1e, 0x8009);
+ if (EN8811H_PHY_READY == reg_value)
+ {
+ dev_info(dev, "EN8811H PHY ready!\n");
+ break;
+ }
+ retry--;
+ } while (retry);
+ if (0 == retry)
+ {
+ dev_err(dev, "EN8811H PHY is not ready. (MD32 FW Status reg: 0x%x)\n", reg_value);
+ pbus_value = air_buckpbus_reg_read(phydev, 0x3b3c);
+ dev_err(dev, "Check MD32 FW Version(0x3b3c) : %08x\n", pbus_value);
+ dev_err(dev, "EN8811H initialize fail!\n");
+ return 0;
+ }
+ /* Mode selection*/
+ dev_info(dev, "EN8811H Mode 1 !\n");
+ ret = air_mii_cl45_write(phydev, 0x1e, 0x800c, 0x0);
+ AIR_RTN_ERR(ret);
+ ret = air_mii_cl45_write(phydev, 0x1e, 0x800d, 0x0);
+ AIR_RTN_ERR(ret);
+ ret = air_mii_cl45_write(phydev, 0x1e, 0x800e, 0x1101);
+ AIR_RTN_ERR(ret);
+ ret = air_mii_cl45_write(phydev, 0x1e, 0x800f, 0x0002);
+ AIR_RTN_ERR(ret);
+
+ /* Serdes polarity */
+ pbus_value = air_buckpbus_reg_read(phydev, 0xca0f8);
+ pbus_value = (pbus_value & 0xfffffffc) | EN8811H_RX_POLARITY_REVERSE | EN8811H_TX_POLARITY_NORMAL;
+ ret = air_buckpbus_reg_write(phydev, 0xca0f8, pbus_value);
+ AIR_RTN_ERR(ret);
+ pbus_value = air_buckpbus_reg_read(phydev, 0xca0f8);
+ dev_info(dev, "Tx, Rx Polarity(0xca0f8): %08x\n", pbus_value);
+ pbus_value = air_buckpbus_reg_read(phydev, 0x3b3c);
+ dev_info(dev, "MD32 FW Version(0x3b3c) : %08x\n", pbus_value);
+#if defined(AIR_LED_SUPPORT)
+ ret = en8811h_led_init(phydev);
+ if (ret < 0)
+ {
+ dev_err(dev, "en8811h_led_init fail. (ret=%d)\n", ret);
+ return ret;
+ }
+#endif
+ dev_info(dev, "EN8811H initialize OK! (%s)\n", EN8811H_DRIVER_VERSION);
+ return 0;
+}
+
+static int en8811h_get_autonego(struct phy_device *phydev, int *an)
+{
+ int reg;
+ reg = phy_read(phydev, MII_BMCR);
+ if (reg < 0)
+ return -EINVAL;
+ if (reg & BMCR_ANENABLE)
+ *an = AUTONEG_ENABLE;
+ else
+ *an = AUTONEG_DISABLE;
+ return 0;
+}
+
+static int en8811h_read_status(struct phy_device *phydev)
+{
+ int ret = 0, lpagb = 0, lpa = 0, common_adv_gb = 0, common_adv = 0, advgb = 0, adv = 0, reg = 0, an = AUTONEG_DISABLE, bmcr = 0;
+ int old_link = phydev->link;
+ u32 pbus_value = 0;
+ struct device *dev = phydev_dev(phydev);
+ ret = genphy_update_link(phydev);
+ if (ret)
+ {
+ dev_err(dev, "ret %d!\n", ret);
+ return ret;
+ }
+
+ if (old_link && phydev->link)
+ return 0;
+
+ phydev->speed = SPEED_UNKNOWN;
+ phydev->duplex = DUPLEX_UNKNOWN;
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ reg = phy_read(phydev, MII_BMSR);
+ if (reg < 0)
+ {
+ dev_err(dev, "MII_BMSR reg %d!\n", reg);
+ return reg;
+ }
+ reg = phy_read(phydev, MII_BMSR);
+ if (reg < 0)
+ {
+ dev_err(dev, "MII_BMSR reg %d!\n", reg);
+ return reg;
+ }
+ if(reg & BMSR_LSTATUS)
+ {
+ pbus_value = air_buckpbus_reg_read(phydev, 0x109D4);
+ if (0x10 & pbus_value) {
+ phydev->speed = SPEED_2500;
+ phydev->duplex = DUPLEX_FULL;
+ }
+ else
+ {
+ ret = en8811h_get_autonego(phydev, &an);
+ if ((AUTONEG_ENABLE == an) && (0 == ret))
+ {
+ dev_dbg(dev, "AN mode!\n");
+ dev_dbg(dev, "SPEED 1000/100!\n");
+ lpagb = phy_read(phydev, MII_STAT1000);
+ if (lpagb < 0 )
+ return lpagb;
+ advgb = phy_read(phydev, MII_CTRL1000);
+ if (adv < 0 )
+ return adv;
+ common_adv_gb = (lpagb & (advgb << 2));
+
+ lpa = phy_read(phydev, MII_LPA);
+ if (lpa < 0 )
+ return lpa;
+ adv = phy_read(phydev, MII_ADVERTISE);
+ if (adv < 0 )
+ return adv;
+ common_adv = (lpa & adv);
+
+ phydev->speed = SPEED_10;
+ phydev->duplex = DUPLEX_HALF;
+ if (common_adv_gb & (LPA_1000FULL | LPA_1000HALF))
+ {
+ phydev->speed = SPEED_1000;
+ if (common_adv_gb & LPA_1000FULL)
+
+ phydev->duplex = DUPLEX_FULL;
+ }
+ else if (common_adv & (LPA_100FULL | LPA_100HALF))
+ {
+ phydev->speed = SPEED_100;
+ if (common_adv & LPA_100FULL)
+ phydev->duplex = DUPLEX_FULL;
+ }
+ else
+ {
+ if (common_adv & LPA_10FULL)
+ phydev->duplex = DUPLEX_FULL;
+ }
+ }
+ else
+ {
+ dev_dbg(dev, "Force mode!\n");
+ bmcr = phy_read(phydev, MII_BMCR);
+
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ if (bmcr & BMCR_SPEED1000)
+ phydev->speed = SPEED_1000;
+ else if (bmcr & BMCR_SPEED100)
+ phydev->speed = SPEED_100;
+ else
+ phydev->speed = SPEED_UNKNOWN;
+ }
+ }
+ }
+
+ return ret;
+}
+static struct phy_driver en8811h_driver[] = {
+{
+ .phy_id = EN8811H_PHY_ID,
+ .name = "Airoha EN8811H",
+ .phy_id_mask = 0x0ffffff0,
+ .probe = en8811h_phy_probe,
+ .read_status = en8811h_read_status,
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 5, 0))
+ .get_features = en8811h_get_features,
+ .read_mmd = air_mii_cl45_read,
+ .write_mmd = air_mii_cl45_write,
+#endif
+} };
+
+int __init en8811h_phy_driver_register(void)
+{
+ int ret;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+ ret = phy_driver_register(en8811h_driver);
+#else
+ ret = phy_driver_register(en8811h_driver, THIS_MODULE);
+#endif
+ if (!ret)
+ return 0;
+
+ phy_driver_unregister(en8811h_driver);
+ return ret;
+}
+
+void __exit en8811h_phy_driver_unregister(void)
+{
+ phy_driver_unregister(en8811h_driver);
+}
+
+module_init(en8811h_phy_driver_register);
+module_exit(en8811h_phy_driver_unregister);
\ No newline at end of file
diff -urN a/drivers/net/phy/air_en8811h.h b/drivers/net/phy/air_en8811h.h
--- a/drivers/net/phy/air_en8811h.h 1970-01-01 08:00:00.000000000 +0800
+++ b/drivers/net/phy/air_en8811h.h 2023-06-14 14:02:38.474875084 +0800
@@ -0,0 +1,151 @@
+#ifndef __EN8811H_H
+#define __EN8811H_H
+
+#define EN8811H_MD32_DM "EthMD32.dm.bin"
+#define EN8811H_MD32_DSP "EthMD32.DSP.bin"
+
+#define EN8811H_PHY_ID1 0x03a2
+#define EN8811H_PHY_ID2 0xa411
+#define EN8811H_PHY_ID ((EN8811H_PHY_ID1 << 16) | EN8811H_PHY_ID2)
+#define EN8811H_PHY_READY 0x02
+#define MAX_RETRY 25
+
+#define EN8811H_TX_POLARITY_NORMAL 0x1
+#define EN8811H_TX_POLARITY_REVERSE 0x0
+
+#define EN8811H_RX_POLARITY_REVERSE (0x1 << 1)
+#define EN8811H_RX_POLARITY_NORMAL (0x0 << 1)
+
+
+/*
+The following led_cfg example is for reference only.
+LED0 Link 2500/Blink 2500 TxRx (GPIO5) <-> BASE_T_LED0,
+LED1 Link 1000/Blink 1000 TxRx (GPIO4) <-> BASE_T_LED1,
+LED2 Link 100 /Blink 100 TxRx (GPIO3) <-> BASE_T_LED2,
+*/
+/* User-defined.B */
+#define BASE_T_LED0_ON_CFG (LED_ON_EVT_LINK_2500M)
+#define BASE_T_LED0_BLK_CFG (LED_BLK_EVT_2500M_TX_ACT | LED_BLK_EVT_2500M_RX_ACT)
+#define BASE_T_LED1_ON_CFG (LED_ON_EVT_LINK_1000M)
+#define BASE_T_LED1_BLK_CFG (LED_BLK_EVT_1000M_TX_ACT | LED_BLK_EVT_1000M_RX_ACT)
+#define BASE_T_LED2_ON_CFG (LED_ON_EVT_LINK_100M)
+#define BASE_T_LED2_BLK_CFG (LED_BLK_EVT_100M_TX_ACT | LED_BLK_EVT_100M_RX_ACT)
+/* User-defined.E */
+
+/* CL45 MDIO control */
+#define MII_MMD_ACC_CTL_REG 0x0d
+#define MII_MMD_ADDR_DATA_REG 0x0e
+#define MMD_OP_MODE_DATA BIT(14)
+
+#define EN8811H_DRIVER_VERSION "v1.2.1"
+
+#define LED_ON_CTRL(i) (0x024 + ((i)*2))
+#define LED_ON_EN (1 << 15)
+#define LED_ON_POL (1 << 14)
+#define LED_ON_EVT_MASK (0x1ff)
+/* LED ON Event Option.B */
+#define LED_ON_EVT_LINK_2500M (1 << 8)
+#define LED_ON_EVT_FORCE (1 << 6)
+#define LED_ON_EVT_LINK_DOWN (1 << 3)
+#define LED_ON_EVT_LINK_100M (1 << 1)
+#define LED_ON_EVT_LINK_1000M (1 << 0)
+/* LED ON Event Option.E */
+
+#define LED_BLK_CTRL(i) (0x025 + ((i)*2))
+#define LED_BLK_EVT_MASK (0xfff)
+/* LED Blinking Event Option.B*/
+#define LED_BLK_EVT_2500M_RX_ACT (1 << 11)
+#define LED_BLK_EVT_2500M_TX_ACT (1 << 10)
+#define LED_BLK_EVT_FORCE (1 << 9)
+#define LED_BLK_EVT_100M_RX_ACT (1 << 3)
+#define LED_BLK_EVT_100M_TX_ACT (1 << 2)
+#define LED_BLK_EVT_1000M_RX_ACT (1 << 1)
+#define LED_BLK_EVT_1000M_TX_ACT (1 << 0)
+/* LED Blinking Event Option.E*/
+#define LED_ENABLE 1
+#define LED_DISABLE 0
+
+#define EN8811H_LED_COUNT 3
+
+#define LED_BCR (0x021)
+#define LED_BCR_EXT_CTRL (1 << 15)
+#define LED_BCR_CLK_EN (1 << 3)
+#define LED_BCR_TIME_TEST (1 << 2)
+#define LED_BCR_MODE_MASK (3)
+#define LED_BCR_MODE_DISABLE (0)
+
+#define LED_ON_DUR (0x022)
+#define LED_ON_DUR_MASK (0xffff)
+
+#define LED_BLK_DUR (0x023)
+#define LED_BLK_DUR_MASK (0xffff)
+
+#define UNIT_LED_BLINK_DURATION 1024
+
+#define AIR_RTN_ON_ERR(cond, err) \
+ do { if ((cond)) return (err); } while(0)
+
+#define AIR_RTN_ERR(err) AIR_RTN_ON_ERR(err < 0, err)
+
+#define LED_SET_EVT(reg, cod, result, bit) do \
+ { \
+ if(reg & cod) { \
+ result |= bit; \
+ } \
+ } while(0)
+
+#define LED_SET_GPIO_SEL(gpio, led, val) do \
+ { \
+ val |= (led << (8 * (gpio % 4))); \
+ } while(0)
+
+#define INVALID_DATA 0xffff
+#define PBUS_INVALID_DATA 0xffffffff
+
+typedef struct AIR_BASE_T_LED_CFG_S
+{
+ u16 en;
+ u16 gpio;
+ u16 pol;
+ u16 on_cfg;
+ u16 blk_cfg;
+}AIR_BASE_T_LED_CFG_T;
+typedef enum
+{
+ AIR_LED2_GPIO3 = 3,
+ AIR_LED1_GPIO4,
+ AIR_LED0_GPIO5,
+ AIR_LED_LAST
+} AIR_LED_GPIO;
+
+typedef enum {
+ AIR_BASE_T_LED0,
+ AIR_BASE_T_LED1,
+ AIR_BASE_T_LED2,
+ AIR_BASE_T_LED3
+}AIR_BASE_T_LED;
+
+typedef enum
+{
+ AIR_LED_BLK_DUR_32M,
+ AIR_LED_BLK_DUR_64M,
+ AIR_LED_BLK_DUR_128M,
+ AIR_LED_BLK_DUR_256M,
+ AIR_LED_BLK_DUR_512M,
+ AIR_LED_BLK_DUR_1024M,
+ AIR_LED_BLK_DUR_LAST
+} AIR_LED_BLK_DUT_T;
+
+typedef enum
+{
+ AIR_ACTIVE_LOW,
+ AIR_ACTIVE_HIGH,
+} AIR_LED_POLARITY;
+typedef enum
+{
+ AIR_LED_MODE_DISABLE,
+ AIR_LED_MODE_USER_DEFINE,
+ AIR_LED_MODE_LAST
+} AIR_LED_MODE_T;
+
+#endif /* End of __EN8811H_MD32_H */
diff -urN a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
--- a/drivers/net/phy/Kconfig 2022-03-26 16:28:40.211133235 +0800
+++ b/drivers/net/phy/Kconfig 2022-03-26 16:30:52.637025198 +0800
@@ -595,6 +595,11 @@
the Reduced Gigabit Media Independent Interface(RGMII) between
Ethernet physical media devices and the Gigabit Ethernet controller.
+config AIR_EN8811H_PHY
+ tristate "Drivers for Airoha EN8811H 2.5 Gigabit PHY"
+ ---help---
+ Currently supports the Airoha EN8811H PHY.
+
endif # PHYLIB
config MICREL_KS8995MA
diff -urN a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
--- a/drivers/net/phy/Makefile 2022-03-26 16:28:57.619384439 +0800
+++ b/drivers/net/phy/Makefile 2022-03-26 16:31:40.893705848 +0800
@@ -111,6 +111,7 @@
obj-$(CONFIG_TERANETICS_PHY) += teranetics.o
obj-$(CONFIG_VITESSE_PHY) += vitesse.o
obj-$(CONFIG_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
+obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
obj-$(CONFIG_MT753X_GSW) += mtk/mt753x/
obj-$(CONFIG_RTL8367S_GSW) += rtk/