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mediatek: remove unneeded patches
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hanwckf
parent
d56beafc56
commit
309e64b088
@ -1,31 +0,0 @@
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From b341f120cfc9ca1dfd48364b7f36ac2c1fbdea43 Mon Sep 17 00:00:00 2001
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From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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Date: Wed, 3 Apr 2019 16:30:01 +0800
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Subject: [PATCH 3/6] mtd: spinand: disable on-die ECC
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Change-Id: I9745adaed5295202fabbe8ab8947885c57a5b847
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Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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---
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drivers/mtd/nand/spi/core.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/mtd/nand/spi/core.c
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+++ b/drivers/mtd/nand/spi/core.c
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@@ -491,7 +491,7 @@ static int spinand_mtd_read(struct mtd_i
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int ret = 0;
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if (ops->mode != MTD_OPS_RAW && spinand->eccinfo.ooblayout)
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- enable_ecc = true;
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+ enable_ecc = false;
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mutex_lock(&spinand->lock);
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@@ -539,7 +539,7 @@ static int spinand_mtd_write(struct mtd_
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int ret = 0;
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if (ops->mode != MTD_OPS_RAW && mtd->ooblayout)
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- enable_ecc = true;
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+ enable_ecc = false;
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mutex_lock(&spinand->lock);
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@ -1,85 +0,0 @@
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From: Felix Fietkau <nbd@nbd.name>
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Date: Fri, 4 Sep 2020 18:36:06 +0200
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Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for coherent DMA
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It improves performance by eliminating the need for a cache flush on rx and tx
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -357,7 +357,7 @@
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};
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cci_control2: slave-if@5000 {
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- compatible = "arm,cci-400-ctrl-if";
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+ compatible = "arm,cci-400-ctrl-if", "syscon";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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@@ -969,6 +969,8 @@
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power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
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mediatek,ethsys = <ðsys>;
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mediatek,sgmiisys = <&sgmiisys>;
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+ mediatek,cci-control = <&cci_control2>;
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+ dma-coherent;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -9,6 +9,7 @@
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#include <linux/of_device.h>
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#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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+#include <linux/of_address.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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@@ -2526,6 +2527,13 @@ static int mtk_hw_init(struct mtk_eth *e
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if (ret)
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goto err_disable_pm;
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+ if (of_dma_is_coherent(eth->dev->of_node)) {
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+ u32 mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
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+ ETHSYS_DMA_AG_MAP_PPE;
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+
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+ regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, mask, mask);
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+ }
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+
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
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ret = device_reset(eth->dev);
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if (ret) {
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@@ -3124,6 +3132,16 @@ static int mtk_probe(struct platform_dev
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}
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}
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+ if (of_dma_is_coherent(pdev->dev.of_node)) {
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+ struct regmap *cci;
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+
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+ cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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+ "mediatek,cci-control");
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+ /* enable CPU/bus coherency */
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+ if (!IS_ERR(cci))
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+ regmap_write(cci, 0, 3);
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+ }
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+
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
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eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
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GFP_KERNEL);
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -448,6 +448,12 @@
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#define RSTCTRL_FE BIT(6)
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#define RSTCTRL_PPE BIT(31)
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+/* ethernet dma channel agent map */
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+#define ETHSYS_DMA_AG_MAP 0x408
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+#define ETHSYS_DMA_AG_MAP_PDMA BIT(0)
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+#define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
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+#define ETHSYS_DMA_AG_MAP_PPE BIT(2)
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+
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/* SGMII subsystem config registers */
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/* Register to auto-negotiation restart */
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#define SGMSYS_PCS_CONTROL_1 0x0
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@ -1,108 +0,0 @@
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From: Felix Fietkau <nbd@nbd.name>
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Date: Fri, 4 Sep 2020 18:42:42 +0200
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Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
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It improves performance by eliminating the need for a cache flush for DMA on
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attached devices
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -805,6 +805,8 @@
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reg = <0 0x1a143000 0 0x1000>;
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reg-names = "port0";
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mediatek,pcie-cfg = <&pciecfg>;
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+ mediatek,hifsys = <&hifsys>;
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+ mediatek,cci-control = <&cci_control2>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
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@@ -822,6 +824,7 @@
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
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status = "disabled";
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+ dma-coherent;
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slot0: pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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@@ -848,6 +851,8 @@
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reg = <0 0x1a145000 0 0x1000>;
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reg-names = "port1";
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mediatek,pcie-cfg = <&pciecfg>;
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+ mediatek,hifsys = <&hifsys>;
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+ mediatek,cci-control = <&cci_control2>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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@@ -866,6 +871,7 @@
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
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status = "disabled";
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+ dma-coherent;
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slot1: pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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@@ -925,6 +931,11 @@
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};
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};
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+ hifsys: syscon@1af00000 {
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+ compatible = "mediatek,mt7622-hifsys", "syscon";
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+ reg = <0 0x1af00000 0 0x70>;
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+ };
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+
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt7622-ethsys",
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"syscon";
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--- a/drivers/pci/controller/pcie-mediatek.c
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+++ b/drivers/pci/controller/pcie-mediatek.c
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@@ -20,6 +20,7 @@
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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+#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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@@ -139,6 +140,11 @@
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#define PCIE_LINK_STATUS_V2 0x804
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#define PCIE_PORT_LINKUP_V2 BIT(10)
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+/* DMA channel mapping */
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+#define HIFSYS_DMA_AG_MAP 0x008
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+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0)
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+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1)
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+
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struct mtk_pcie_port;
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/**
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@@ -1068,6 +1074,27 @@ static int mtk_pcie_setup(struct mtk_pci
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}
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}
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+ if (of_dma_is_coherent(node)) {
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+ struct regmap *con;
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+ u32 mask;
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+
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+ con = syscon_regmap_lookup_by_phandle(node,
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+ "mediatek,cci-control");
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+ /* enable CPU/bus coherency */
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+ if (!IS_ERR(con))
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+ regmap_write(con, 0, 3);
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+
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+ con = syscon_regmap_lookup_by_phandle(node,
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+ "mediatek,hifsys");
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+ if (IS_ERR(con)) {
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+ dev_err(dev, "missing hifsys node\n");
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+ return PTR_ERR(con);
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+ }
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+
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+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
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+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
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+ }
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+
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for_each_available_child_of_node(node, child) {
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int slot;
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