From 1b99cd51c501742be58d8dcfae64104829faf0ce Mon Sep 17 00:00:00 2001
From: lgs2007m <116912542@qq.com>
Date: Sat, 21 Sep 2024 18:28:29 +0800
Subject: [PATCH] mediatek: fix PCIe #PERST being de-asserted too early

The driver for MediaTek gen3 PCIe hosts de-asserts all reset
signals at the same time using a single register write operation.
Delay the de-assertion of the #PERST signal by 100ms as some PCIe
devices fail to come up otherwise.

Sync from https://github.com/immortalwrt/immortalwrt/commit/6a2e17d5c1
---
 ...611-pcie-mediatek-gen3-PERST-for-100ms.patch | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 target/linux/mediatek/patches-5.4/611-pcie-mediatek-gen3-PERST-for-100ms.patch

diff --git a/target/linux/mediatek/patches-5.4/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/target/linux/mediatek/patches-5.4/611-pcie-mediatek-gen3-PERST-for-100ms.patch
new file mode 100644
index 0000000000..b302e275f9
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/611-pcie-mediatek-gen3-PERST-for-100ms.patch
@@ -0,0 +1,17 @@
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -317,7 +317,13 @@ static int mtk_pcie_startup_port(struct
+ 	msleep(100);
+ 
+ 	/* De-assert reset signals */
+-	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
++	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
++	writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
++
++	msleep(100);
++
++	/* De-assert PERST# signals */
++	val &= ~(PCIE_PE_RSTB);
+ 	writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
+ 
+ 	/* Check if the link is up or not */