Merge Official Source

This commit is contained in:
AmadeusGhost 2020-10-31 12:00:38 +08:00
commit 04a1ceb936
576 changed files with 444 additions and 120246 deletions

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@ -44,15 +44,8 @@ config KERNEL_DEBUG_FS
write to these files. Many common debugging facilities, such as
ftrace, require the existence of debugfs.
# remove KERNEL_MIPS_FPU_EMULATOR after kernel 4.19 is gone
config KERNEL_MIPS_FPU_EMULATOR
bool "Compile the kernel with MIPS FPU Emulator"
default y
depends on (mips || mipsel || mips64 || mips64el)
config KERNEL_MIPS_FP_SUPPORT
bool
default y if KERNEL_MIPS_FPU_EMULATOR
config KERNEL_ARM_PMU
bool

View File

@ -36,6 +36,8 @@ define FeedSourcesAppend
echo 'src/gz %d_core %U/targets/%S/packages'; \
$(strip $(if $(CONFIG_PER_FEED_REPO), \
echo 'src/gz %d_base %U/packages/%A/base'; \
$(if $(filter %SNAPSHOT-y,$(VERSION_NUMBER)-$(CONFIG_BUILDBOT)), \
echo 'src/gz %d_kmods %U/targets/%S/kmods/$(LINUX_VERSION)-$(LINUX_RELEASE)-$(LINUX_VERMAGIC)';) \
$(foreach feed,$(FEEDS_AVAILABLE), \
$(if $(CONFIG_FEED_$(feed)), \
echo '$(if $(filter m,$(CONFIG_FEED_$(feed))),# )src/gz %d_$(feed) %U/packages/%A/$(feed)';)))) \

View File

@ -7,11 +7,114 @@ define rootfs_align
$(patsubst %-256k,0x40000,$(patsubst %-128k,0x20000,$(patsubst %-64k,0x10000,$(patsubst squashfs%,0x4,$(patsubst root.%,%,$(1))))))
endef
define Build/uImage
mkimage -A $(LINUX_KARCH) \
-O linux -T kernel \
-C $(1) -a $(KERNEL_LOADADDR) -e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \
-n '$(if $(UIMAGE_NAME),$(UIMAGE_NAME),$(call toupper,$(LINUX_KARCH)) $(VERSION_DIST) Linux-$(LINUX_VERSION))' -d $@ $@.new
define Build/append-dtb
cat $(KDIR)/image-$(firstword $(DEVICE_DTS)).dtb >> $@
endef
define Build/append-dtb-elf
$(TARGET_CROSS)objcopy \
--set-section-flags=.appended_dtb=alloc,contents \
--update-section \
.appended_dtb=$(KDIR)/image-$(firstword $(DEVICE_DTS)).dtb $@
endef
define Build/append-kernel
dd if=$(IMAGE_KERNEL) >> $@
endef
compat_version=$(if $(DEVICE_COMPAT_VERSION),$(DEVICE_COMPAT_VERSION),1.0)
json_quote=$(subst ','\'',$(subst ",\",$(1)))
#")')
legacy_supported_message=$(SUPPORTED_DEVICES) - Image version mismatch: image $(compat_version), \
device 1.0. Please wipe config during upgrade (force required) or reinstall. \
$(if $(DEVICE_COMPAT_MESSAGE),Reason: $(DEVICE_COMPAT_MESSAGE),Please check documentation ...)
metadata_devices=$(if $(1),$(subst "$(space)","$(comma)",$(strip $(foreach v,$(1),"$(call json_quote,$(v))"))))
metadata_json = \
'{ $(if $(IMAGE_METADATA),$(IMAGE_METADATA)$(comma)) \
"metadata_version": "1.1", \
"compat_version": "$(call json_quote,$(compat_version))", \
$(if $(DEVICE_COMPAT_MESSAGE),"compat_message": "$(call json_quote,$(DEVICE_COMPAT_MESSAGE))"$(comma)) \
$(if $(filter-out 1.0,$(compat_version)),"new_supported_devices": \
[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma) \
"supported_devices": ["$(call json_quote,$(legacy_supported_message))"]$(comma)) \
$(if $(filter 1.0,$(compat_version)),"supported_devices":[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma)) \
"version": { \
"dist": "$(call json_quote,$(VERSION_DIST))", \
"version": "$(call json_quote,$(VERSION_NUMBER))", \
"revision": "$(call json_quote,$(REVISION))", \
"target": "$(call json_quote,$(TARGETID))", \
"board": "$(call json_quote,$(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)))" \
} \
}'
define Build/append-metadata
$(if $(SUPPORTED_DEVICES),-echo $(call metadata_json) | fwtool -I - $@)
[ ! -s "$(BUILD_KEY)" -o ! -s "$(BUILD_KEY).ucert" -o ! -s "$@" ] || { \
cp "$(BUILD_KEY).ucert" "$@.ucert" ;\
usign -S -m "$@" -s "$(BUILD_KEY)" -x "$@.sig" ;\
ucert -A -c "$@.ucert" -x "$@.sig" ;\
fwtool -S "$@.ucert" "$@" ;\
}
endef
define Build/append-rootfs
dd if=$(IMAGE_ROOTFS) >> $@
endef
define Build/append-squashfs-fakeroot-be
rm -rf $@.fakefs $@.fakesquashfs
mkdir $@.fakefs
$(STAGING_DIR_HOST)/bin/mksquashfs-lzma \
$@.fakefs $@.fakesquashfs \
-noappend -root-owned -be -nopad -b 65536 \
$(if $(SOURCE_DATE_EPOCH),-fixed-time $(SOURCE_DATE_EPOCH))
cat $@.fakesquashfs >> $@
endef
define Build/append-string
echo -n $(1) >> $@
endef
define Build/append-ubi
sh $(TOPDIR)/scripts/ubinize-image.sh \
$(if $(UBOOTENV_IN_UBI),--uboot-env) \
$(if $(KERNEL_IN_UBI),--kernel $(IMAGE_KERNEL)) \
$(foreach part,$(UBINIZE_PARTS),--part $(part)) \
$(IMAGE_ROOTFS) \
$@.tmp \
-p $(BLOCKSIZE:%k=%KiB) -m $(PAGESIZE) \
$(if $(SUBPAGESIZE),-s $(SUBPAGESIZE)) \
$(if $(VID_HDR_OFFSET),-O $(VID_HDR_OFFSET)) \
$(UBINIZE_OPTS)
cat $@.tmp >> $@
rm $@.tmp
endef
define Build/append-uboot
dd if=$(UBOOT_PATH) >> $@
endef
# append a fake/empty uImage header, to fool bootloaders rootfs integrity check
# for example
define Build/append-uImage-fakehdr
$(eval type=$(word 1,$(1)))
$(eval magic=$(word 2,$(1)))
touch $@.fakehdr
$(STAGING_DIR_HOST)/bin/mkimage \
-A $(LINUX_KARCH) -O linux -T $(type) -C none \
-n '$(VERSION_DIST) fake $(type)' \
$(if $(magic),-M $(magic)) \
-d $@.fakehdr \
-s \
$@.fakehdr
cat $@.fakehdr >> $@
endef
define Build/buffalo-dhp-image
$(STAGING_DIR_HOST)/bin/mkdhpimg $@ $@.new
mv $@.new $@
endef
@ -43,9 +146,13 @@ define Build/buffalo-tag-dhp
mv $@.new $@
endef
define Build/buffalo-dhp-image
$(STAGING_DIR_HOST)/bin/mkdhpimg $@ $@.new
mv $@.new $@
define Build/check-size
@imagesize="$$(stat -c%s $@)"; \
limitsize="$$(($(subst k,* 1024,$(subst m, * 1024k,$(if $(1),$(1),$(IMAGE_SIZE))))))"; \
[ $$limitsize -ge $$imagesize ] || { \
echo "WARNING: Image file $@ is too big: $$imagesize > $$limitsize" >&2; \
rm -f $@; \
}
endef
define Build/eva-image
@ -53,29 +160,73 @@ define Build/eva-image
mv $@.new $@
endef
define Build/seama
$(STAGING_DIR_HOST)/bin/seama -i $@ \
-m "dev=/dev/mtdblock/$(SEAMA_MTDBLOCK)" -m "type=firmware"
mv $@.seama $@
define Build/fit
$(TOPDIR)/scripts/mkits.sh \
-D $(DEVICE_NAME) -o $@.its -k $@ \
$(if $(word 2,$(1)),-d $(word 2,$(1))) -C $(word 1,$(1)) \
-a $(KERNEL_LOADADDR) -e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \
$(if $(DEVICE_FDT_NUM),-n $(DEVICE_FDT_NUM)) \
-c $(if $(DEVICE_DTS_CONFIG),$(DEVICE_DTS_CONFIG),"config@1") \
-A $(LINUX_KARCH) -v $(LINUX_VERSION)
PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new
@mv $@.new $@
endef
define Build/seama-seal
$(STAGING_DIR_HOST)/bin/seama -i $@ -s $@.seama \
-m "signature=$(SEAMA_SIGNATURE)"
mv $@.seama $@
define Build/gzip
gzip -f -9n -c $@ $(1) > $@.new
@mv $@.new $@
endef
define Build/zyxel-ras-image
let \
newsize="$(subst k,* 1024,$(RAS_ROOTFS_SIZE))"; \
$(STAGING_DIR_HOST)/bin/mkrasimage \
-b $(RAS_BOARD) \
-v $(RAS_VERSION) \
-r $@ \
-s $$newsize \
define Build/install-dtb
$(call locked, \
$(foreach dts,$(DEVICE_DTS), \
$(CP) \
$(DTS_DIR)/$(dts).dtb \
$(BIN_DIR)/$(IMG_PREFIX)-$(dts).dtb; \
), \
install-dtb-$(IMG_PREFIX) \
)
endef
define Build/jffs2
rm -rf $(KDIR_TMP)/$(DEVICE_NAME)/jffs2 && \
mkdir -p $(KDIR_TMP)/$(DEVICE_NAME)/jffs2/$$(dirname $(1)) && \
cp $@ $(KDIR_TMP)/$(DEVICE_NAME)/jffs2/$(1) && \
$(STAGING_DIR_HOST)/bin/mkfs.jffs2 --pad \
$(if $(CONFIG_BIG_ENDIAN),--big-endian,--little-endian) \
--squash-uids -v -e $(patsubst %k,%KiB,$(BLOCKSIZE)) \
-o $@.new \
$(if $(findstring separate-kernel,$(word 1,$(1))),-k $(IMAGE_KERNEL)) \
&& mv $@.new $@
-d $(KDIR_TMP)/$(DEVICE_NAME)/jffs2 \
2>&1 1>/dev/null | awk '/^.+$$$$/' && \
$(STAGING_DIR_HOST)/bin/padjffs2 $@.new -J $(patsubst %k,,$(BLOCKSIZE))
-rm -rf $(KDIR_TMP)/$(DEVICE_NAME)/jffs2/
@mv $@.new $@
endef
define Build/kernel2minor
kernel2minor -k $@ -r $@.new $(1)
mv $@.new $@
endef
define Build/kernel-bin
rm -f $@
cp $< $@
endef
define Build/linksys-image
$(TOPDIR)/scripts/linksys-image.sh \
"$(call param_get_default,type,$(1),$(DEVICE_NAME))" \
$@ $@.new
mv $@.new $@
endef
define Build/lzma
$(call Build/lzma-no-dict,-lc1 -lp2 -pb2 $(1))
endef
define Build/lzma-no-dict
$(STAGING_DIR_HOST)/bin/lzma e $@ $(1) $@.new
@mv $@.new $@
endef
define Build/netgear-chk
@ -96,163 +247,23 @@ define Build/netgear-dni
mv $@.new $@
endef
define Build/append-squashfs-fakeroot-be
rm -rf $@.fakefs $@.fakesquashfs
mkdir $@.fakefs
$(STAGING_DIR_HOST)/bin/mksquashfs-lzma \
$@.fakefs $@.fakesquashfs \
-noappend -root-owned -be -nopad -b 65536 \
$(if $(SOURCE_DATE_EPOCH),-fixed-time $(SOURCE_DATE_EPOCH))
cat $@.fakesquashfs >> $@
endef
define Build/append-string
echo -n $(1) >> $@
endef
# append a fake/empty uImage header, to fool bootloaders rootfs integrity check
# for example
define Build/append-uImage-fakehdr
$(eval type=$(word 1,$(1)))
$(eval magic=$(word 2,$(1)))
touch $@.fakehdr
$(STAGING_DIR_HOST)/bin/mkimage \
-A $(LINUX_KARCH) -O linux -T $(type) -C none \
-n '$(VERSION_DIST) fake $(type)' \
$(if $(magic),-M $(magic)) \
-d $@.fakehdr \
-s \
$@.fakehdr
cat $@.fakehdr >> $@
endef
define Build/tplink-safeloader
-$(STAGING_DIR_HOST)/bin/tplink-safeloader \
-B $(TPLINK_BOARD_ID) \
-V $(REVISION) \
-k $(IMAGE_KERNEL) \
-r $@ \
-o $@.new \
-j \
$(wordlist 2,$(words $(1)),$(1)) \
$(if $(findstring sysupgrade,$(word 1,$(1))),-S) && mv $@.new $@ || rm -f $@
endef
define Build/append-dtb
cat $(KDIR)/image-$(firstword $(DEVICE_DTS)).dtb >> $@
endef
define Build/install-dtb
$(call locked, \
$(foreach dts,$(DEVICE_DTS), \
$(CP) \
$(DTS_DIR)/$(dts).dtb \
$(BIN_DIR)/$(IMG_PREFIX)-$(dts).dtb; \
), \
install-dtb-$(IMG_PREFIX) \
)
endef
define Build/fit
$(TOPDIR)/scripts/mkits.sh \
-D $(DEVICE_NAME) -o $@.its -k $@ \
$(if $(word 2,$(1)),-d $(word 2,$(1))) -C $(word 1,$(1)) \
-a $(KERNEL_LOADADDR) -e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \
$(if $(DEVICE_FDT_NUM),-n $(DEVICE_FDT_NUM)) \
-c $(if $(DEVICE_DTS_CONFIG),$(DEVICE_DTS_CONFIG),"config@1") \
-A $(LINUX_KARCH) -v $(LINUX_VERSION)
PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new
@mv $@.new $@
endef
define Build/lzma
$(call Build/lzma-no-dict,-lc1 -lp2 -pb2 $(1))
endef
define Build/lzma-no-dict
$(STAGING_DIR_HOST)/bin/lzma e $@ $(1) $@.new
@mv $@.new $@
endef
define Build/gzip
gzip -f -9n -c $@ $(1) > $@.new
@mv $@.new $@
endef
define Build/zip
mkdir $@.tmp
mv $@ $@.tmp/$(1)
zip -j -X \
$(if $(SOURCE_DATE_EPOCH),--mtime="$(SOURCE_DATE_EPOCH)") \
$@ $@.tmp/$(if $(1),$(1),$@)
rm -rf $@.tmp
endef
define Build/jffs2
rm -rf $(KDIR_TMP)/$(DEVICE_NAME)/jffs2 && \
mkdir -p $(KDIR_TMP)/$(DEVICE_NAME)/jffs2/$$(dirname $(1)) && \
cp $@ $(KDIR_TMP)/$(DEVICE_NAME)/jffs2/$(1) && \
$(STAGING_DIR_HOST)/bin/mkfs.jffs2 --pad \
$(if $(CONFIG_BIG_ENDIAN),--big-endian,--little-endian) \
--squash-uids -v -e $(patsubst %k,%KiB,$(BLOCKSIZE)) \
-o $@.new \
-d $(KDIR_TMP)/$(DEVICE_NAME)/jffs2 \
2>&1 1>/dev/null | awk '/^.+$$$$/' && \
$(STAGING_DIR_HOST)/bin/padjffs2 $@.new -J $(patsubst %k,,$(BLOCKSIZE))
-rm -rf $(KDIR_TMP)/$(DEVICE_NAME)/jffs2/
@mv $@.new $@
endef
define Build/kernel-bin
rm -f $@
cp $< $@
endef
define Build/patch-cmdline
$(STAGING_DIR_HOST)/bin/patch-cmdline $@ '$(CMDLINE)'
endef
define Build/append-kernel
dd if=$(IMAGE_KERNEL) >> $@
endef
define Build/append-rootfs
dd if=$(IMAGE_ROOTFS) >> $@
endef
define Build/append-ubi
sh $(TOPDIR)/scripts/ubinize-image.sh \
$(if $(UBOOTENV_IN_UBI),--uboot-env) \
$(if $(KERNEL_IN_UBI),--kernel $(IMAGE_KERNEL)) \
$(foreach part,$(UBINIZE_PARTS),--part $(part)) \
$(IMAGE_ROOTFS) \
$@.tmp \
-p $(BLOCKSIZE:%k=%KiB) -m $(PAGESIZE) \
$(if $(SUBPAGESIZE),-s $(SUBPAGESIZE)) \
$(if $(VID_HDR_OFFSET),-O $(VID_HDR_OFFSET)) \
$(UBINIZE_OPTS)
cat $@.tmp >> $@
rm $@.tmp
endef
define Build/append-uboot
dd if=$(UBOOT_PATH) >> $@
endef
define Build/pad-to
$(call Image/pad-to,$@,$(1))
define Build/openmesh-image
$(TOPDIR)/scripts/om-fwupgradecfg-gen.sh \
"$(call param_get_default,ce_type,$(1),$(DEVICE_NAME))" \
"$@-fwupgrade.cfg" \
"$(call param_get_default,kernel,$(1),$(IMAGE_KERNEL))" \
"$(call param_get_default,rootfs,$(1),$@)"
$(TOPDIR)/scripts/combined-ext-image.sh \
"$(call param_get_default,ce_type,$(1),$(DEVICE_NAME))" "$@" \
"$@-fwupgrade.cfg" "fwupgrade.cfg" \
"$(call param_get_default,kernel,$(1),$(IMAGE_KERNEL))" "kernel" \
"$(call param_get_default,rootfs,$(1),$@)" "rootfs"
endef
define Build/pad-extra
dd if=/dev/zero bs=$(1) count=1 >> $@
endef
define Build/pad-rootfs
$(STAGING_DIR_HOST)/bin/padjffs2 $@ $(1) \
$(if $(BLOCKSIZE),$(BLOCKSIZE:%k=%),4 8 16 64 128 256)
endef
define Build/pad-offset
let \
size="$$(stat -c%s $@)" \
@ -264,48 +275,26 @@ define Build/pad-offset
mv $@.new $@
endef
define Build/xor-image
$(STAGING_DIR_HOST)/bin/xorimage -i $@ -o $@.xor $(1)
mv $@.xor $@
define Build/pad-rootfs
$(STAGING_DIR_HOST)/bin/padjffs2 $@ $(1) \
$(if $(BLOCKSIZE),$(BLOCKSIZE:%k=%),4 8 16 64 128 256)
endef
define Build/check-size
@imagesize="$$(stat -c%s $@)"; \
limitsize="$$(($(subst k,* 1024,$(subst m, * 1024k,$(if $(1),$(1),$(IMAGE_SIZE))))))"; \
[ $$limitsize -ge $$imagesize ] || { \
echo "WARNING: Image file $@ is too big: $$imagesize > $$limitsize" >&2; \
rm -f $@; \
}
define Build/pad-to
$(call Image/pad-to,$@,$(1))
endef
define Build/combined-image
-sh $(TOPDIR)/scripts/combined-image.sh \
"$(IMAGE_KERNEL)" \
"$@" \
"$@.new"
define Build/patch-cmdline
$(STAGING_DIR_HOST)/bin/patch-cmdline $@ '$(CMDLINE)'
endef
# Convert a raw image into a $1 type image.
# E.g. | qemu-image vdi
define Build/qemu-image
qemu-img convert -f raw -O $1 $@ $@.new
@mv $@.new $@
endef
define Build/linksys-image
$(TOPDIR)/scripts/linksys-image.sh \
"$(call param_get_default,type,$(1),$(DEVICE_NAME))" \
$@ $@.new
mv $@.new $@
endef
define Build/openmesh-image
$(TOPDIR)/scripts/om-fwupgradecfg-gen.sh \
"$(call param_get_default,ce_type,$(1),$(DEVICE_NAME))" \
"$@-fwupgrade.cfg" \
"$(call param_get_default,kernel,$(1),$(IMAGE_KERNEL))" \
"$(call param_get_default,rootfs,$(1),$@)"
$(TOPDIR)/scripts/combined-ext-image.sh \
"$(call param_get_default,ce_type,$(1),$(DEVICE_NAME))" "$@" \
"$@-fwupgrade.cfg" "fwupgrade.cfg" \
"$(call param_get_default,kernel,$(1),$(IMAGE_KERNEL))" "kernel" \
"$(call param_get_default,rootfs,$(1),$@)" "rootfs"
endef
define Build/qsdk-ipq-factory-nand
$(TOPDIR)/scripts/mkits-qsdk-ipq-image.sh \
$@.its ubi $@
@ -320,6 +309,18 @@ define Build/qsdk-ipq-factory-nor
@mv $@.new $@
endef
define Build/seama
$(STAGING_DIR_HOST)/bin/seama -i $@ \
-m "dev=/dev/mtdblock/$(SEAMA_MTDBLOCK)" -m "type=firmware"
mv $@.seama $@
endef
define Build/seama-seal
$(STAGING_DIR_HOST)/bin/seama -i $@ -s $@.seama \
-m "signature=$(SEAMA_SIGNATURE)"
mv $@.seama $@
endef
define Build/senao-header
$(STAGING_DIR_HOST)/bin/mksenaofw $(1) -e $@ -o $@.new
mv $@.new $@
@ -333,6 +334,18 @@ define Build/sysupgrade-tar
$@
endef
define Build/tplink-safeloader
-$(STAGING_DIR_HOST)/bin/tplink-safeloader \
-B $(TPLINK_BOARD_ID) \
-V $(REVISION) \
-k $(IMAGE_KERNEL) \
-r $@ \
-o $@.new \
-j \
$(wordlist 2,$(words $(1)),$(1)) \
$(if $(findstring sysupgrade,$(word 1,$(1))),-S) && mv $@.new $@ || rm -f $@
endef
define Build/tplink-v1-header
$(STAGING_DIR_HOST)/bin/mktplinkfw \
-c -H $(TPLINK_HWID) -W $(TPLINK_HWREV) -L $(KERNEL_LOADADDR) \
@ -380,51 +393,38 @@ define Build/tplink-v2-image
rm -rf $@.new
endef
compat_version=$(if $(DEVICE_COMPAT_VERSION),$(DEVICE_COMPAT_VERSION),1.0)
json_quote=$(subst ','\'',$(subst ",\",$(1)))
#")')
legacy_supported_message=$(SUPPORTED_DEVICES) - Image version mismatch: image $(compat_version), \
device 1.0. Please wipe config during upgrade (force required) or reinstall. \
$(if $(DEVICE_COMPAT_MESSAGE),Reason: $(DEVICE_COMPAT_MESSAGE),Please check documentation ...)
metadata_devices=$(if $(1),$(subst "$(space)","$(comma)",$(strip $(foreach v,$(1),"$(call json_quote,$(v))"))))
metadata_json = \
'{ $(if $(IMAGE_METADATA),$(IMAGE_METADATA)$(comma)) \
"metadata_version": "1.1", \
"compat_version": "$(call json_quote,$(compat_version))", \
$(if $(DEVICE_COMPAT_MESSAGE),"compat_message": "$(call json_quote,$(DEVICE_COMPAT_MESSAGE))"$(comma)) \
$(if $(filter-out 1.0,$(compat_version)),"new_supported_devices": \
[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma) \
"supported_devices": ["$(call json_quote,$(legacy_supported_message))"]$(comma)) \
$(if $(filter 1.0,$(compat_version)),"supported_devices":[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma)) \
"version": { \
"dist": "$(call json_quote,$(VERSION_DIST))", \
"version": "$(call json_quote,$(VERSION_NUMBER))", \
"revision": "$(call json_quote,$(REVISION))", \
"target": "$(call json_quote,$(TARGETID))", \
"board": "$(call json_quote,$(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)))" \
} \
}'
define Build/append-metadata
$(if $(SUPPORTED_DEVICES),-echo $(call metadata_json) | fwtool -I - $@)
[ ! -s "$(BUILD_KEY)" -o ! -s "$(BUILD_KEY).ucert" -o ! -s "$@" ] || { \
cp "$(BUILD_KEY).ucert" "$@.ucert" ;\
usign -S -m "$@" -s "$(BUILD_KEY)" -x "$@.sig" ;\
ucert -A -c "$@.ucert" -x "$@.sig" ;\
fwtool -S "$@.ucert" "$@" ;\
}
endef
define Build/kernel2minor
kernel2minor -k $@ -r $@.new $(1)
define Build/uImage
mkimage -A $(LINUX_KARCH) \
-O linux -T kernel \
-C $(1) -a $(KERNEL_LOADADDR) -e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \
-n '$(if $(UIMAGE_NAME),$(UIMAGE_NAME),$(call toupper,$(LINUX_KARCH)) $(VERSION_DIST) Linux-$(LINUX_VERSION))' -d $@ $@.new
mv $@.new $@
endef
# Convert a raw image into a $1 type image.
# E.g. | qemu-image vdi
define Build/qemu-image
qemu-img convert -f raw -O $1 $@ $@.new
@mv $@.new $@
define Build/xor-image
$(STAGING_DIR_HOST)/bin/xorimage -i $@ -o $@.xor $(1)
mv $@.xor $@
endef
define Build/zip
mkdir $@.tmp
mv $@ $@.tmp/$(1)
zip -j -X \
$(if $(SOURCE_DATE_EPOCH),--mtime="$(SOURCE_DATE_EPOCH)") \
$@ $@.tmp/$(if $(1),$(1),$@)
rm -rf $@.tmp
endef
define Build/zyxel-ras-image
let \
newsize="$(subst k,* 1024,$(RAS_ROOTFS_SIZE))"; \
$(STAGING_DIR_HOST)/bin/mkrasimage \
-b $(RAS_BOARD) \
-v $(RAS_VERSION) \
-r $@ \
-s $$newsize \
-o $@.new \
$(if $(findstring separate-kernel,$(word 1,$(1))),-k $(IMAGE_KERNEL)) \
&& mv $@.new $@
endef

View File

@ -1,93 +0,0 @@
ifneq ($(CONFIG_TARGET_ROOTFS_UBIFS),)
define Image/mkfs/ubifs/generate
$(CP) ./ubinize$(1).cfg $(KDIR)
( cd $(KDIR); \
$(STAGING_DIR_HOST)/bin/ubinize \
$(if $($(PROFILE)_UBI_OPTS),$($(PROFILE)_UBI_OPTS),$(shell echo $(UBI_OPTS))) \
-o $(KDIR)/root$(1).ubi \
ubinize$(1).cfg \
)
endef
define Image/mkfs/ubifs/legacy
$(if $($(PROFILE)_UBIFS_OPTS)$(UBIFS_OPTS),
$(STAGING_DIR_HOST)/bin/mkfs.ubifs \
$(if $($(PROFILE)_UBIFS_OPTS),$($(PROFILE)_UBIFS_OPTS),$(UBIFS_OPTS)) \
$(if $(CONFIG_TARGET_UBIFS_FREE_SPACE_FIXUP),--space-fixup) \
$(if $(CONFIG_TARGET_UBIFS_COMPRESSION_NONE),--compr=none) \
$(if $(CONFIG_TARGET_UBIFS_COMPRESSION_LZO),--compr=lzo) \
$(if $(CONFIG_TARGET_UBIFS_COMPRESSION_ZLIB),--compr=zlib) \
$(if $(shell echo $(CONFIG_TARGET_UBIFS_JOURNAL_SIZE)),--jrn-size=$(CONFIG_TARGET_UBIFS_JOURNAL_SIZE)) \
--squash-uids \
-o $(KDIR)/root.ubifs \
-d $(TARGET_DIR)
)
$(call Image/Build,ubifs)
$(if $($(PROFILE)_UBI_OPTS)$(UBI_OPTS),
$(if $(wildcard ./ubinize.cfg),$(call Image/mkfs/ubifs/generate,))
$(if $(wildcard ./ubinize-overlay.cfg),$(call Image/mkfs/ubifs/generate,-overlay))
)
$(if $(wildcard ./ubinize.cfg),$(call Image/Build,ubi))
endef
endif
LegacyDevice/Dump = $(Device/Dump)
define LegacyDevice/Check
$(Device/Check/Common)
_TARGET_PREPARE := $$(if $$(_PROFILE_SET),legacy-images-prepare,prepare-disabled)
_TARGET := $$(if $$(_PROFILE_SET),legacy-images,install-disabled)
$$(if $$(_PROFILE_SET),install: legacy-images-make)
ifndef IB
$$(if $$(_PROFILE_SET),kernel_prepare: legacy-images-prepare-make)
endif
endef
ifdef TARGET_PER_DEVICE_ROOTFS
define Image/Build/Profile/Filesystem
cp $(KDIR)/root.$(2)+pkg=$(3) $(KDIR)/root.$(2)
$(call Image/Build/$(2),$(2))
$(call Image/Build/Profile,$(1),$(2))
endef
else
Image/Build/Profile/Filesystem = $(Image/Build/Profile)
endif
define LegacyDevice/Build
$$(_TARGET): legacy-image-$(1)
$$(_TARGET_PREPARE): legacy-image-prepare-$(1)
.PHONY: legacy-image-prepare-$(1) legacy-image-$(1)
legacy-image-prepare-$(1):
$$(call Image/Prepare/Profile,$(1))
ifndef IB
ifdef CONFIG_TARGET_PER_DEVICE_ROOTFS
ROOTFS/$(1) := $(foreach fs,$(TARGET_FILESYSTEMS), \
$(KDIR)/root.$(fs)$$(strip $(if $(CONFIG_TARGET_PER_DEVICE_ROOTFS),+pkg=$$(ROOTFS_ID/$(1)))) \
)
$$(ROOTFS/$(1)): target-dir-$$(ROOTFS_ID/$(1))
legacy-images-make: $$(if $$(_PROFILE_SET),$$(ROOTFS/$(1)))
endif
endif
legacy-image-$(1):
$$(call Image/BuildKernel/Profile,$(1))
$(foreach fs,$(TARGET_FILESYSTEMS),
$$(call Image/Build/Profile/Filesystem,$(1),$(fs),$$(ROOTFS_ID/$(1)))
)
endef
define LegacyDevice
$(call Device/InitProfile,$(1))
$(call Device/Default,$(1))
$(call LegacyDevice/Default,$(1))
$(call LegacyDevice/$(1),$(1))
$(call LegacyDevice/Check,$(1))
$(call LegacyDevice/$(if $(DUMP),Dump,Build),$(1))
endef

View File

@ -17,7 +17,6 @@ ifndef IB
endif
endif
include $(INCLUDE_DIR)/image-legacy.mk
include $(INCLUDE_DIR)/feeds.mk
include $(INCLUDE_DIR)/rootfs.mk
@ -163,18 +162,12 @@ DTC_FLAGS += \
-Wno-unit_address_format \
-Wno-pci_bridge \
-Wno-pci_device_bus_num \
-Wno-pci_device_reg
ifeq ($(strip $(call kernel_patchver_ge,4.17.0)),1)
DTC_FLAGS += \
-Wno-avoid_unnecessary_addr_size \
-Wno-alias_paths
endif
ifeq ($(strip $(call kernel_patchver_ge,4.18.0)),1)
DTC_FLAGS += \
-Wno-graph_child_address \
-Wno-graph_port \
-Wno-unique_unit_address
endif
-Wno-pci_device_reg \
-Wno-avoid_unnecessary_addr_size \
-Wno-alias_paths \
-Wno-graph_child_address \
-Wno-graph_port \
-Wno-unique_unit_address
define Image/pad-to
dd if=$(1) of=$(1).new bs=$(2) conv=sync
@ -258,35 +251,6 @@ define Image/mkfs/squashfs
endef
endif
# $(1): board name
# $(2): rootfs type
# $(3): kernel image
# $(4): compat string
ifneq ($(CONFIG_NAND_SUPPORT),)
define Image/Build/SysupgradeNAND
mkdir -p "$(KDIR_TMP)/sysupgrade-$(if $(4),$(4),$(1))/"
echo "BOARD=$(if $(4),$(4),$(1))" > "$(KDIR_TMP)/sysupgrade-$(if $(4),$(4),$(1))/CONTROL"
[ -z "$(2)" ] || $(CP) "$(KDIR)/root.$(2)" "$(KDIR_TMP)/sysupgrade-$(if $(4),$(4),$(1))/root"
[ -z "$(3)" ] || $(CP) "$(3)" "$(KDIR_TMP)/sysupgrade-$(if $(4),$(4),$(1))/kernel"
(cd "$(KDIR_TMP)"; $(TAR) cvf \
"$(BIN_DIR)/$(IMG_PREFIX)-$(1)-$(2)-sysupgrade.tar" sysupgrade-$(if $(4),$(4),$(1)) \
$(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") \
)
endef
# $(1) board name
# $(2) ubinize-image options (e.g. --uboot-env and/or --kernel kernelimage)
# $(3) rootfstype (e.g. squashfs or ubifs)
# $(4) options to pass-through to ubinize (i.e. $($(PROFILE)_UBI_OPTS)))
define Image/Build/UbinizeImage
sh $(TOPDIR)/scripts/ubinize-image.sh $(2) \
"$(KDIR)/root.$(3)" \
"$(KDIR)/$(IMG_PREFIX)-$(1)-$(3)-ubinized.bin" \
$(4)
endef
endif
define Image/mkfs/ubifs
$(STAGING_DIR_HOST)/bin/mkfs.ubifs \
$(UBIFS_OPTS) $(call param_unmangle,$(call param_get,fs,$(1))) \
@ -712,8 +676,6 @@ define BuildImage
prepare:
compile:
clean:
legacy-images-prepare:
legacy-images:
image_prepare:
ifeq ($(IB),)
@ -729,9 +691,6 @@ define BuildImage
rm -rf $(BUILD_DIR)/json_info_files
$(call Image/Prepare)
legacy-images-prepare-make: image_prepare
$(MAKE) legacy-images-prepare BIN_DIR="$(BIN_DIR)"
else
image_prepare:
mkdir -p $(BIN_DIR) $(KDIR)/tmp
@ -745,17 +704,12 @@ define BuildImage
$(call Image/InstallKernel)
$(foreach device,$(TARGET_DEVICES),$(call Device,$(device)))
$(foreach device,$(LEGACY_DEVICES),$(call LegacyDevice,$(device)))
install-images: kernel_prepare $(foreach fs,$(filter-out $(if $(UBIFS_OPTS),,ubifs),$(TARGET_FILESYSTEMS) $(fs-subtypes-y)),$(KDIR)/root.$(fs))
$(foreach fs,$(TARGET_FILESYSTEMS),
$(call Image/Build,$(fs))
)
legacy-images-make: install-images
$(call Image/mkfs/ubifs/legacy)
$(MAKE) legacy-images BIN_DIR="$(BIN_DIR)"
install: install-images
$(call Image/Manifest)

View File

@ -6,10 +6,8 @@ ifdef CONFIG_TESTING_KERNEL
KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER)
endif
LINUX_VERSION-4.19 = .138
LINUX_VERSION-5.4 = .72
LINUX_KERNEL_HASH-4.19.138 = d15c27d05f6c527269b75b30cc72972748e55720e7e00ad8abbaa4fe3b1d5e02
LINUX_KERNEL_HASH-5.4.72 = 0e24645bd56fe5b55a7a662895f5562c103d71b54d097281f0c9c71ff22c1172
remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))

View File

@ -198,21 +198,17 @@ $(eval $(call nf_add,IPT_IPV6_EXTRA,CONFIG_IP6_NF_MATCH_RT, $(P_V6)ip6t_rt))
# kernel only
$(eval $(if $(NF_KMOD),$(call nf_add,NF_NAT,CONFIG_NF_NAT, $(P_XT)nf_nat),))
$(eval $(if $(NF_KMOD),$(call nf_add,NF_NAT,CONFIG_NF_NAT_IPV4, $(P_V4)nf_nat_ipv4, lt 5.1)))
$(eval $(if $(NF_KMOD),$(call nf_add,NF_NAT6,CONFIG_NF_NAT_IPV6, $(P_V6)nf_nat_ipv6, lt 5.1)))
$(eval $(if $(NF_KMOD),$(call nf_add,IPT_NAT,CONFIG_NETFILTER_XT_NAT, $(P_XT)xt_nat),))
$(eval $(if $(NF_KMOD),$(call nf_add,IPT_NAT,CONFIG_IP_NF_NAT, $(P_V4)iptable_nat),))
$(eval $(if $(NF_KMOD),$(call nf_add,IPT_NAT6,CONFIG_IP6_NF_NAT, $(P_V6)ip6table_nat),))
$(eval $(if $(NF_KMOD),$(call nf_add,IPT_NAT6,CONFIG_IP6_NF_TARGET_MASQUERADE, $(P_V6)ip6t_MASQUERADE, lt 5.2),))
$(eval $(if $(NF_KMOD),$(call nf_add,IPT_NAT6,CONFIG_IP6_NF_TARGET_NPT, $(P_V6)ip6t_NPT),))
# userland only
$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_NAT,CONFIG_NF_NAT, ipt_SNAT ipt_DNAT)))
$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_NAT6,CONFIG_IP6_NF_TARGET_NPT, ip6t_DNPT ip6t_SNPT)))
$(eval $(call nf_add,IPT_NAT,CONFIG_IP_NF_TARGET_MASQUERADE, $(P_V4)ipt_MASQUERADE, lt 5.2))
$(eval $(call nf_add,IPT_NAT,CONFIG_NETFILTER_XT_TARGET_MASQUERADE, $(P_XT)xt_MASQUERADE, ge 5.2))
$(eval $(call nf_add,IPT_NAT,CONFIG_NETFILTER_XT_TARGET_MASQUERADE, $(P_XT)xt_MASQUERADE))
$(eval $(call nf_add,IPT_NAT,CONFIG_NETFILTER_XT_TARGET_REDIRECT, $(P_XT)xt_REDIRECT))
@ -232,8 +228,6 @@ $(eval $(call nf_add,NF_NATHELPER,CONFIG_NF_NAT_FTP, $(P_XT)nf_nat_ftp))
$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_BROADCAST, $(P_XT)nf_conntrack_broadcast))
$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_AMANDA, $(P_XT)nf_conntrack_amanda))
$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_NAT_AMANDA, $(P_XT)nf_nat_amanda))
$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CT_PROTO_GRE, $(P_XT)nf_conntrack_proto_gre, lt 5.1))
$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_NAT_PROTO_GRE, $(P_V4)nf_nat_proto_gre, lt 5.0))
$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_H323, $(P_XT)nf_conntrack_h323))
$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_NAT_H323, $(P_V4)nf_nat_h323))
$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_PPTP, $(P_XT)nf_conntrack_pptp))
@ -345,11 +339,8 @@ $(eval $(call nf_add,EBTABLES_WATCHERS,CONFIG_BRIDGE_EBT_NFQUEUE, $(P_EBT)ebt_nf
# nftables
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NF_TABLES, $(P_XT)nf_tables),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NF_TABLES_SET, $(P_XT)nf_tables_set),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_CHAIN_ROUTE_IPV4, $(P_V4)nft_chain_route_ipv4, lt 5.2),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_CHAIN_ROUTE_IPV6, $(P_V6)nft_chain_route_ipv6, lt 5.2),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_COUNTER, $(P_XT)nft_counter),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_CT, $(P_XT)nft_ct),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_EXTHDR, $(P_XT)nft_exthdr, lt 4.18),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_HASH, $(P_XT)nft_hash),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_LIMIT, $(P_XT)nft_limit),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_LOG, $(P_XT)nft_log),))
@ -365,14 +356,12 @@ $(eval $(if $(NF_KMOD),$(call nf_add,NFT_BRIDGE,CONFIG_NFT_BRIDGE_META, $(P_EBT)
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_BRIDGE,CONFIG_NFT_BRIDGE_REJECT, $(P_EBT)nft_reject_bridge),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_NAT, $(P_XT)nft_nat),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_NAT, $(P_XT)nft_chain_nat, ge 5.1),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_CHAIN_NAT_IPV4, $(P_V4)nft_chain_nat_ipv4, lt 5.1),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_NAT, $(P_XT)nft_chain_nat),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_REDIR_IPV4, $(P_V4)nft_redir_ipv4),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_MASQ, $(P_XT)nft_masq),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_MASQ_IPV4, $(P_V4)nft_masq_ipv4),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT6,CONFIG_NFT_REDIR_IPV6, $(P_V6)nft_redir_ipv6),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT6,CONFIG_NFT_CHAIN_NAT_IPV6, $(P_V6)nft_chain_nat_ipv6, lt 5.1),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT6,CONFIG_NFT_MASQ_IPV6, $(P_V6)nft_masq_ipv6),))
$(eval $(if $(NF_KMOD),$(call nf_add,NFT_FIB,CONFIG_NFT_FIB, $(P_XT)nft_fib),))

View File

@ -7,7 +7,7 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=ltq-atm
PKG_RELEASE:=2
PKG_RELEASE:=3
PKG_MAINTAINER:=John Crispin <john@phrozen.org>
PKG_LICENSE:=GPL-2.0+

View File

@ -289,17 +289,9 @@ static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
return -ENOTTY;
if ( _IOC_DIR(cmd) & _IOC_READ )
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0)
ret = !access_ok(arg, _IOC_SIZE(cmd));
#else
ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
#endif
else if ( _IOC_DIR(cmd) & _IOC_WRITE )
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0)
ret = !access_ok(arg, _IOC_SIZE(cmd));
#else
ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
#endif
if ( ret )
return -EFAULT;

View File

@ -171,7 +171,7 @@ define KernelPackage/crypto-des
KCONFIG:=CONFIG_CRYPTO_DES
FILES:= \
$(LINUX_DIR)/crypto/des_generic.ko \
$(LINUX_DIR)/lib/crypto/libdes.ko@ge5.4
$(LINUX_DIR)/lib/crypto/libdes.ko
AUTOLOAD:=$(call AutoLoad,09,des_generic)
$(call AddDepends/crypto)
endef
@ -197,7 +197,7 @@ define KernelPackage/crypto-ecdh
KCONFIG:= CONFIG_CRYPTO_ECDH
FILES:= \
$(LINUX_DIR)/crypto/ecdh_generic.ko \
$(LINUX_DIR)/crypto/ecc.ko@ge5.2
$(LINUX_DIR)/crypto/ecc.ko
AUTOLOAD:=$(call AutoLoad,10,ecdh_generic)
$(call AddDepends/crypto)
endef
@ -729,7 +729,7 @@ define KernelPackage/crypto-sha256
CONFIG_CRYPTO_SHA256_SSSE3
FILES:= \
$(LINUX_DIR)/crypto/sha256_generic.ko \
$(LINUX_DIR)/lib/crypto/libsha256.ko@ge5.4
$(LINUX_DIR)/lib/crypto/libsha256.ko
AUTOLOAD:=$(call AutoLoad,09,sha256_generic)
$(call AddDepends/crypto)
endef

View File

@ -204,7 +204,7 @@ $(eval $(call KernelPackage,fs-ext4))
define KernelPackage/fs-f2fs
SUBMENU:=$(FS_MENU)
TITLE:=F2FS filesystem support
DEPENDS:= +kmod-crypto-hash +kmod-crypto-crc32 +!LINUX_4_19:kmod-nls-base
DEPENDS:= +kmod-crypto-hash +kmod-crypto-crc32 +kmod-nls-base
KCONFIG:=CONFIG_F2FS_FS
FILES:=$(LINUX_DIR)/fs/f2fs/f2fs.ko
AUTOLOAD:=$(call AutoLoad,30,f2fs,1)

View File

@ -182,7 +182,7 @@ define KernelPackage/input-touchscreen-ads7846
CONFIG_TOUCHSCREEN_PROPERTIES=y \
CONFIG_TOUCHSCREEN_ADS7846
FILES:=$(LINUX_DIR)/drivers/input/touchscreen/ads7846.ko \
$(LINUX_DIR)/drivers/input/touchscreen/of_touchscreen.ko@ge5.4
$(LINUX_DIR)/drivers/input/touchscreen/of_touchscreen.ko
AUTOLOAD:=$(call AutoProbe,ads7846)
endef

View File

@ -250,8 +250,7 @@ define KernelPackage/lib-cordic
SUBMENU:=$(LIB_MENU)
TITLE:=Cordic function support
KCONFIG:=CONFIG_CORDIC
FILES:=$(LINUX_DIR)/lib/cordic.ko@lt5.2 \
$(LINUX_DIR)/lib/math/cordic.ko@ge5.2
FILES:=$(LINUX_DIR)/lib/math/cordic.ko
AUTOLOAD:=$(call AutoProbe,cordic)
endef

View File

@ -682,7 +682,7 @@ $(eval $(call KernelPackage,igbvf))
define KernelPackage/ixgbe
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Intel(R) 82598/82599 PCI-Express 10 Gigabit Ethernet support
DEPENDS:=@PCI_SUPPORT +kmod-mdio +kmod-ptp +kmod-hwmon-core +!LINUX_4_19:kmod-libphy
DEPENDS:=@PCI_SUPPORT +kmod-mdio +kmod-ptp +kmod-hwmon-core +kmod-libphy
KCONFIG:=CONFIG_IXGBE \
CONFIG_IXGBE_VXLAN=n \
CONFIG_IXGBE_HWMON=y \
@ -720,7 +720,7 @@ $(eval $(call KernelPackage,ixgbevf))
define KernelPackage/i40e
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Intel(R) Ethernet Controller XL710 Family support
DEPENDS:=@PCI_SUPPORT +kmod-mdio +kmod-ptp +kmod-hwmon-core +!LINUX_4_19:kmod-libphy
DEPENDS:=@PCI_SUPPORT +kmod-mdio +kmod-ptp +kmod-hwmon-core +kmod-libphy
KCONFIG:=CONFIG_I40E \
CONFIG_I40E_VXLAN=n \
CONFIG_I40E_HWMON=y \
@ -744,8 +744,7 @@ define KernelPackage/iavf
CONFIG_I40EVF \
CONFIG_IAVF
FILES:= \
$(LINUX_DIR)/drivers/net/ethernet/intel/i40evf/i40evf.ko@lt4.20 \
$(LINUX_DIR)/drivers/net/ethernet/intel/iavf/iavf.ko@ge4.20
$(LINUX_DIR)/drivers/net/ethernet/intel/iavf/iavf.ko
AUTOLOAD:=$(call AutoProbe,i40evf iavf)
AUTOLOAD:=$(call AutoProbe,iavf)
endef
@ -864,36 +863,6 @@ endef
$(eval $(call KernelPackage,hfcmulti))
define KernelPackage/gigaset
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Siemens Gigaset support for isdn4linux
DEPENDS:=@USB_SUPPORT +kmod-isdn4linux +kmod-lib-crc-ccitt +kmod-usb-core @LINUX_4_19
URL:=http://gigaset307x.sourceforge.net/
KCONFIG:= \
CONFIG_ISDN_DRV_GIGASET \
CONFIG_GIGASET_BASE \
CONFIG_GIGASET_M101 \
CONFIG_GIGASET_M105 \
CONFIG_GIGASET_UNDOCREQ=y \
CONFIG_GIGASET_I4L=y
FILES:= \
$(LINUX_DIR)/drivers/isdn/gigaset/gigaset.ko \
$(LINUX_DIR)/drivers/isdn/gigaset/bas_gigaset.ko \
$(LINUX_DIR)/drivers/isdn/gigaset/ser_gigaset.ko \
$(LINUX_DIR)/drivers/isdn/gigaset/usb_gigaset.ko
AUTOLOAD:=$(call AutoProbe,gigaset bas_gigaset ser_gigaset usb_gigaset)
endef
define KernelPackage/gigaset/description
This driver supports the Siemens Gigaset SX205/255 family of
ISDN DECT bases, including the predecessors Gigaset 3070/3075
and 4170/4175 and their T-Com versions Sinus 45isdn and Sinus
721X.
endef
$(eval $(call KernelPackage,gigaset))
define KernelPackage/macvlan
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=MAC-VLAN support
@ -1245,7 +1214,7 @@ $(eval $(call KernelPackage,sfp))
define KernelPackage/igc
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Intel(R) Ethernet Controller I225 Series support
DEPENDS:=@PCI_SUPPORT @!LINUX_4_19
DEPENDS:=@PCI_SUPPORT
KCONFIG:=CONFIG_IGC
FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/igc/igc.ko
AUTOLOAD:=$(call AutoProbe,igc)

View File

@ -1137,7 +1137,7 @@ $(eval $(call KernelPackage,ipt-rpfilter))
define KernelPackage/nft-core
SUBMENU:=$(NF_MENU)
TITLE:=Netfilter nf_tables support
DEPENDS:=+kmod-nfnetlink +kmod-nf-reject +IPV6:kmod-nf-reject6 +IPV6:kmod-nf-conntrack6 +!LINUX_4_19:kmod-nf-nat
DEPENDS:=+kmod-nfnetlink +kmod-nf-reject +IPV6:kmod-nf-reject6 +IPV6:kmod-nf-conntrack6 +kmod-nf-nat
FILES:=$(foreach mod,$(NFT_CORE-m),$(LINUX_DIR)/net/$(mod).ko)
AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_CORE-m)))
KCONFIG:= \

View File

@ -136,21 +136,6 @@ endef
$(eval $(call KernelPackage,dma-buf))
define KernelPackage/nvmem
SUBMENU:=$(OTHER_MENU)
TITLE:=Non Volatile Memory support
DEPENDS:=@LINUX_4_19
KCONFIG:=CONFIG_NVMEM
HIDDEN:=1
FILES:=$(LINUX_DIR)/drivers/nvmem/nvmem_core.ko
endef
define KernelPackage/nvmem/description
Support for NVMEM(Non Volatile Memory) devices like EEPROM, EFUSES, etc.
endef
$(eval $(call KernelPackage,nvmem))
define KernelPackage/eeprom-93cx6
SUBMENU:=$(OTHER_MENU)
TITLE:=EEPROM 93CX6 support
@ -170,7 +155,7 @@ define KernelPackage/eeprom-at24
SUBMENU:=$(OTHER_MENU)
TITLE:=EEPROM AT24 support
KCONFIG:=CONFIG_EEPROM_AT24
DEPENDS:=+kmod-i2c-core +LINUX_4_19:kmod-nvmem +kmod-regmap-i2c
DEPENDS:=+kmod-i2c-core +kmod-regmap-i2c
FILES:=$(LINUX_DIR)/drivers/misc/eeprom/at24.ko
AUTOLOAD:=$(call AutoProbe,at24)
endef
@ -186,7 +171,6 @@ define KernelPackage/eeprom-at25
SUBMENU:=$(OTHER_MENU)
TITLE:=EEPROM AT25 support
KCONFIG:=CONFIG_EEPROM_AT25
DEPENDS:=+LINUX_4_19:kmod-nvmem
FILES:=$(LINUX_DIR)/drivers/misc/eeprom/at25.ko
AUTOLOAD:=$(call AutoProbe,at25)
endef
@ -265,7 +249,7 @@ $(eval $(call KernelPackage,gpio-nxp-74hc164))
define KernelPackage/gpio-pca953x
SUBMENU:=$(OTHER_MENU)
DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core +!LINUX_4_19:kmod-regmap-i2c
DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core +kmod-regmap-i2c
TITLE:=PCA95xx, TCA64xx, and MAX7310 I/O ports
KCONFIG:=CONFIG_GPIO_PCA953X
FILES:=$(LINUX_DIR)/drivers/gpio/gpio-pca953x.ko
@ -651,7 +635,7 @@ define KernelPackage/rtc-pcf2123
SUBMENU:=$(OTHER_MENU)
TITLE:=Philips PCF2123 RTC support
DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
DEPENDS:=+!LINUX_4_19:kmod-regmap-spi
DEPENDS:=+kmod-regmap-spi
KCONFIG:=CONFIG_RTC_DRV_PCF2123 \
CONFIG_RTC_CLASS=y
FILES:=$(LINUX_DIR)/drivers/rtc/rtc-pcf2123.ko
@ -818,7 +802,7 @@ define KernelPackage/serial-8250
$(LINUX_DIR)/drivers/tty/serial/8250/8250.ko \
$(LINUX_DIR)/drivers/tty/serial/8250/8250_base.ko \
$(if $(CONFIG_PCI),$(LINUX_DIR)/drivers/tty/serial/8250/8250_pci.ko) \
$(if $(CONFIG_GPIOLIB),$(LINUX_DIR)/drivers/tty/serial/serial_mctrl_gpio.ko@ge5.3)
$(if $(CONFIG_GPIOLIB),$(LINUX_DIR)/drivers/tty/serial/serial_mctrl_gpio.ko)
AUTOLOAD:=$(call AutoProbe,8250 8250_base 8250_pci)
endef

View File

@ -522,7 +522,7 @@ define KernelPackage/sound-hda-intel
CONFIG_SND_HDA_INTEL
FILES:= \
$(LINUX_DIR)/sound/pci/hda/snd-hda-intel.ko \
$(LINUX_DIR)/sound/hda/snd-intel-nhlt.ko@ge5.4
$(LINUX_DIR)/sound/hda/snd-intel-nhlt.ko
AUTOLOAD:=$(call AutoProbe,snd-hda-intel)
$(call AddDepends/sound,kmod-sound-hda-core)
endef

View File

@ -1586,7 +1586,7 @@ define KernelPackage/usb-chipidea
$(LINUX_DIR)/drivers/extcon/extcon-core.ko \
$(LINUX_DIR)/drivers/usb/chipidea/ci_hdrc.ko \
$(LINUX_DIR)/drivers/usb/common/ulpi.ko \
$(LINUX_DIR)/drivers/usb/roles/roles.ko@ge5.0
$(LINUX_DIR)/drivers/usb/roles/roles.ko
AUTOLOAD:=$(call AutoLoad,39,ci_hdrc,1)
$(call AddDepends/usb)
endef

View File

@ -284,8 +284,7 @@ define KernelPackage/drm-amdgpu
CONFIG_DRM_AMD_DC=y \
CONFIG_DEBUG_KERNEL_DC=n
FILES:=$(LINUX_DIR)/drivers/gpu/drm/amd/amdgpu/amdgpu.ko \
$(LINUX_DIR)/drivers/gpu/drm/scheduler/gpu-sched.ko \
$(LINUX_DIR)/drivers/gpu/drm/amd/lib/chash.ko@lt5.3
$(LINUX_DIR)/drivers/gpu/drm/scheduler/gpu-sched.ko
AUTOLOAD:=$(call AutoProbe,amdgpu)
endef
@ -407,7 +406,6 @@ define KernelPackage/video-core
CONFIG_V4L_PLATFORM_DRIVERS=y \
CONFIG_V4L_ISA_PARPORT_DRIVERS=y
FILES:= \
$(LINUX_DIR)/drivers/media/$(V4L2_DIR)/v4l2-common.ko@lt5.4 \
$(LINUX_DIR)/drivers/media/$(V4L2_DIR)/videodev.ko
AUTOLOAD:=$(call AutoLoad,60, videodev v4l2-common)
endef

View File

@ -7,7 +7,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=libselinux
PKG_VERSION:=3.1
PKG_RELEASE:=2
PKG_RELEASE:=3
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/SELinuxProject/selinux/releases/download/20200710
@ -69,7 +69,7 @@ define Package/libselinux
$(call Package/libselinux/Default)
SECTION:=libs
CATEGORY:=Libraries
DEPENDS:=+libsepol +libpcre +musl-fts
DEPENDS:=+libsepol +libpcre +USE_MUSL:musl-fts
endef
define Package/libselinux/description
@ -109,8 +109,11 @@ HOST_MAKE_FLAGS += \
PREFIX=$(STAGING_DIR_HOSTPKG) \
SHLIBDIR=$(STAGING_DIR_HOSTPKG)/lib
ifeq ($(CONFIG_USE_MUSL),y)
MAKE_FLAGS += FTS_LDLIBS=-lfts
endif
MAKE_FLAGS += \
FTS_LDLIBS=-lfts \
SHLIBDIR=/usr/lib \
OS=Linux

View File

@ -13,6 +13,7 @@ config WPA_RFKILL_SUPPORT
PACKAGE_wpad-openssl || \
PACKAGE_wpad-wolfssl || \
PACKAGE_wpad-basic || \
PACKAGE_wpad-basic-openssl || \
PACKAGE_wpad-basic-wolfssl || \
PACKAGE_wpad-mini || \
PACKAGE_wpad-mesh-openssl || \
@ -33,6 +34,7 @@ config WPA_MSG_MIN_PRIORITY
PACKAGE_wpad-openssl || \
PACKAGE_wpad-wolfssl || \
PACKAGE_wpad-basic || \
PACKAGE_wpad-basic-openssl || \
PACKAGE_wpad-basic-wolfssl || \
PACKAGE_wpad-mini || \
PACKAGE_wpad-mesh-openssl || \

View File

@ -68,9 +68,6 @@ CONFIG_VARIANT:=$(LOCAL_VARIANT)
ifeq ($(LOCAL_VARIANT),mesh)
CONFIG_VARIANT:=full
endif
ifeq ($(LOCAL_VARIANT),hs20)
CONFIG_VARIANT:=full
endif
include $(INCLUDE_DIR)/package.mk
@ -111,10 +108,6 @@ ifeq ($(SSL_VARIANT),openssl)
ifeq ($(LOCAL_VARIANT),full)
DRIVER_MAKEOPTS += CONFIG_OWE=y CONFIG_SUITEB192=y CONFIG_AP=y CONFIG_MESH=y
endif
ifeq ($(LOCAL_VARIANT),hs20)
DRIVER_MAKEOPTS += CONFIG_OWE=y CONFIG_SUITEB192=y CONFIG_AP=y CONFIG_MESH=y CONFIG_DPP=y CONFIG_HS20=y CONFIG_INTERWORKING=y
endif
endif
ifeq ($(SSL_VARIANT),wolfssl)
@ -175,15 +168,6 @@ endef
Package/hostapd-openssl/description = $(Package/hostapd/description)
define Package/hostapd-hs20
$(call Package/hostapd/Default,$(1))
TITLE+= (OpenSSL with Hotspot 2.0)
VARIANT:=hs20-openssl
DEPENDS+=+libopenssl
endef
Package/hostapd-hs20/description = $(Package/hostapd/description)
define Package/hostapd-wolfssl
$(call Package/hostapd/Default,$(1))
TITLE+= (wolfSSL full)
@ -203,6 +187,17 @@ define Package/hostapd-basic/description
This package contains a basic IEEE 802.1x/WPA Authenticator with WPA-PSK, 802.11r and 802.11w support.
endef
define Package/hostapd-basic-openssl
$(call Package/hostapd/Default,$(1))
TITLE+= (WPA-PSK, 11r and 11w)
VARIANT:=basic-openssl
DEPENDS+=+libopenssl
endef
define Package/hostapd-basic-openssl/description
This package contains a basic IEEE 802.1x/WPA Authenticator with WPA-PSK, 802.11r and 802.11w support.
endef
define Package/hostapd-mini
$(call Package/hostapd/Default,$(1))
TITLE+= (WPA-PSK only)
@ -266,6 +261,17 @@ define Package/wpad-basic/description
This package contains a basic IEEE 802.1x/WPA Authenticator and Supplicant with WPA-PSK, 802.11r and 802.11w support.
endef
define Package/wpad-basic-openssl
$(call Package/wpad/Default,$(1))
TITLE+= (OpenSSL, 11r, 11w)
VARIANT:=wpad-basic-openssl
DEPENDS+=+libopenssl
endef
define Package/wpad-basic-openssl/description
This package contains a basic IEEE 802.1x/WPA Authenticator and Supplicant with WPA-PSK, SAE (WPA3-Personal), 802.11r and 802.11w support.
endef
define Package/wpad-basic-wolfssl
$(call Package/wpad/Default,$(1))
TITLE+= (wolfSSL, 11r, 11w)
@ -585,7 +591,7 @@ define Package/hostapd/install
$(INSTALL_BIN) $(PKG_BUILD_DIR)/hostapd/hostapd $(1)/usr/sbin/
endef
Package/hostapd-basic/install = $(Package/hostapd/install)
Package/hostapd-hs20/install = $(Package/hostapd/install)
Package/hostapd-basic-openssl/install = $(Package/hostapd/install)
Package/hostapd-mini/install = $(Package/hostapd/install)
Package/hostapd-openssl/install = $(Package/hostapd/install)
Package/hostapd-wolfssl/install = $(Package/hostapd/install)
@ -605,6 +611,7 @@ define Package/wpad/install
$(LN) wpad $(1)/usr/sbin/wpa_supplicant
endef
Package/wpad-basic/install = $(Package/wpad/install)
Package/wpad-basic-openssl/install = $(Package/wpad/install)
Package/wpad-basic-wolfssl/install = $(Package/wpad/install)
Package/wpad-mini/install = $(Package/wpad/install)
Package/wpad-openssl/install = $(Package/wpad/install)
@ -654,7 +661,7 @@ endif
$(eval $(call BuildPackage,hostapd))
$(eval $(call BuildPackage,hostapd-basic))
$(eval $(call BuildPackage,hostapd-hs20))
$(eval $(call BuildPackage,hostapd-basic-openssl))
$(eval $(call BuildPackage,hostapd-mini))
$(eval $(call BuildPackage,hostapd-openssl))
$(eval $(call BuildPackage,hostapd-wolfssl))
@ -662,6 +669,7 @@ $(eval $(call BuildPackage,wpad))
$(eval $(call BuildPackage,wpad-mesh-openssl))
$(eval $(call BuildPackage,wpad-mesh-wolfssl))
$(eval $(call BuildPackage,wpad-basic))
$(eval $(call BuildPackage,wpad-basic-openssl))
$(eval $(call BuildPackage,wpad-basic-wolfssl))
$(eval $(call BuildPackage,wpad-mini))
$(eval $(call BuildPackage,wpad-openssl))

View File

@ -14,9 +14,9 @@ PKG_FLAGS:=essential
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://git.openwrt.org/project/opkg-lede.git
PKG_SOURCE_DATE:=2020-08-31
PKG_SOURCE_VERSION:=cf44c2feb606b60ba3f35392e102c281ef6ea0da
PKG_MIRROR_HASH:=0d7be9f8f86864e2a9999145210ecaa286fb85cfae131ec502609a6d1e435871
PKG_SOURCE_DATE:=2020-10-30
PKG_SOURCE_VERSION:=8769c75199b4668878176bde0e5faebf3bc61663
PKG_MIRROR_HASH:=601af77e6855e30fd9b82184bf3cdbc9395fe46ad971a65c8ad5e1329e94c545
PKG_LICENSE:=GPL-2.0
PKG_LICENSE_FILES:=COPYING

View File

@ -264,12 +264,7 @@ endif
BUILD_KEY=$(TOPDIR)/key-build
ifeq ($(HOST_OS),Darwin)
FAKEROOT_SO:=$(STAGING_DIR_HOST)/lib/libfakeroot.dylib
else
FAKEROOT_SO:=$(STAGING_DIR_HOST)/lib/libfakeroot.so
endif
FAKEROOT:=$(STAGING_DIR_HOST)/bin/fakeroot -l $(FAKEROOT_SO) -f $(STAGING_DIR_HOST)/bin/faked
FAKEROOT:=$(STAGING_DIR_HOST)/bin/fakeroot
TARGET_CC:=$(TARGET_CROSS)gcc
TARGET_CXX:=$(TARGET_CROSS)g++

View File

@ -38,23 +38,27 @@ $(BIN_DIR)/$(IB_NAME).tar.xz: clean
ifeq ($(CONFIG_IB_STANDALONE),)
echo '## Remote package repositories' >> $(PKG_BUILD_DIR)/repositories.conf
$(call FeedSourcesAppend,$(PKG_BUILD_DIR)/repositories.conf)
$(VERSION_SED_SCRIPT) $(PKG_BUILD_DIR)/repositories.conf
endif
ifeq ($(CONFIG_BUILDBOT),)
$(INSTALL_DIR) $(PKG_BUILD_DIR)/packages
echo '' >> $(PKG_BUILD_DIR)/repositories.conf
echo '## This is the local package repository, do not remove!' >> $(PKG_BUILD_DIR)/repositories.conf
echo 'src imagebuilder file:packages' >> $(PKG_BUILD_DIR)/repositories.conf
$(VERSION_SED_SCRIPT) $(PKG_BUILD_DIR)/repositories.conf
ifeq ($(CONFIG_IB_STANDALONE),)
(cd $(call FeedPackageDir,libc); $(FIND) -type f -name 'libc_*.ipk' -or -name 'kernel_*.ipk' -or -name 'kmod-*.ipk') | \
while read path; do \
mkdir -p "$(PKG_BUILD_DIR)/packages/$${path%/*}"; \
cp "$(call FeedPackageDir,libc)/$$path" "$(PKG_BUILD_DIR)/packages/$$path"; \
done
ifeq ($(CONFIG_IB_STANDALONE),)
$(FIND) $(call FeedPackageDir,libc) -type f \
\( -name 'libc_*.ipk' -or -name 'kernel_*.ipk' -or -name 'kmod-*.ipk' \) \
-exec $(CP) -t $(PKG_BUILD_DIR)/packages {} +
else
$(FIND) $(wildcard $(PACKAGE_SUBDIRS)) -type f -name '*.ipk' \
-exec $(CP) -t $(PKG_BUILD_DIR)/packages/ {} +
endif
else
$(INSTALL_DIR) $(PKG_BUILD_DIR)/packages
find $(wildcard $(PACKAGE_SUBDIRS)) -type f -name '*.ipk' -exec $(CP) {} $(PKG_BUILD_DIR)/packages/ \;
$(FIND) $(call FeedPackageDir,libc) -type f \
\( -name 'libc_*.ipk' -or -name 'kernel_*.ipk' \) \
-exec $(CP) -t $(IB_LDIR)/ {} +
endif
$(CP) $(TOPDIR)/target/linux $(PKG_BUILD_DIR)/target/

View File

@ -138,7 +138,10 @@ package_index: FORCE
$(OPKG) update >&2 || true
package_reload:
if [ ! -f "$(PACKAGE_DIR)/Packages" ] || [ ! -f "$(PACKAGE_DIR)/Packages.gz" ] || [ "`find $(PACKAGE_DIR) -cnewer $(PACKAGE_DIR)/Packages.gz`" ]; then \
if [ -d "$(PACKAGE_DIR)" ] && ( \
[ ! -f "$(PACKAGE_DIR)/Packages" ] || \
[ ! -f "$(PACKAGE_DIR)/Packages.gz" ] || \
[ "`find $(PACKAGE_DIR) -cnewer $(PACKAGE_DIR)/Packages.gz`" ] ); then \
echo "Package list missing or not up-to-date, generating it." >&2 ;\
$(MAKE) package_index; \
else \
@ -153,8 +156,8 @@ package_list: FORCE
package_install: FORCE
@echo
@echo Installing packages...
$(OPKG) install $(firstword $(wildcard $(PACKAGE_DIR)/libc_*.ipk $(PACKAGE_DIR)/base/libc_*.ipk))
$(OPKG) install $(firstword $(wildcard $(PACKAGE_DIR)/kernel_*.ipk $(PACKAGE_DIR)/base/kernel_*.ipk))
$(OPKG) install $(firstword $(wildcard $(LINUX_DIR)/libc_*.ipk $(PACKAGE_DIR)/libc_*.ipk))
$(OPKG) install $(firstword $(wildcard $(LINUX_DIR)/kernel_*.ipk $(PACKAGE_DIR)/kernel_*.ipk))
$(OPKG) install $(BUILD_PACKAGES)
prepare_rootfs: FORCE

View File

@ -1,335 +0,0 @@
# CONFIG_40x is not set
CONFIG_44x=y
CONFIG_460EX=y
CONFIG_4xx=y
CONFIG_4xx_SOC=y
# CONFIG_ADVANCED_OPTIONS is not set
CONFIG_APM821xx=y
CONFIG_APOLLO3G=y
# CONFIG_ARCHES is not set
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
CONFIG_ARCH_HAS_MEMBARRIER_CALLBACKS=y
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_WALK_MEMORY=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_ARCH_MMAP_RND_BITS=11
CONFIG_ARCH_MMAP_RND_BITS_MAX=17
CONFIG_ARCH_MMAP_RND_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y
CONFIG_AUDIT_ARCH=y
# CONFIG_BAMBOO is not set
CONFIG_BCH=y
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_BLK_MQ_PCI=y
CONFIG_BLUESTONE=y
CONFIG_BOOKE=y
CONFIG_BOOKE_WDT=y
# CONFIG_BOUNCE is not set
CONFIG_BUILD_SALT=""
# CONFIG_CANYONLANDS is not set
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
CONFIG_CLANG_VERSION=0
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
CONFIG_CMDLINE_BOOL=y
CONFIG_CONSISTENT_SIZE=0x00200000
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DEV_PPC4XX=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MD5_PPC=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1_PPC=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DTC=y
# CONFIG_E200 is not set
CONFIG_EARLY_PRINTK=y
# CONFIG_EBONY is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
# CONFIG_EIGER is not set
CONFIG_EXTRA_TARGETS="uImage"
CONFIG_FIXED_PHY=y
CONFIG_FREEZER=y
# CONFIG_FSL_LBC is not set
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_NVRAM=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
# CONFIG_GEN_RTC is not set
# CONFIG_GLACIER is not set
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_CBPF_JIT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_GENERIC_GUP=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_KPROBES_ON_FTRACE=y
CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_PPC4XX=y
CONFIG_HZ=1000
CONFIG_HZ_1000=y
CONFIG_HZ_PERIODIC=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IBM_IIC=y
CONFIG_IBM_EMAC=y
CONFIG_IBM_EMAC_EMAC4=y
CONFIG_IBM_EMAC_POLL_WEIGHT=32
CONFIG_IBM_EMAC_RGMII=y
CONFIG_IBM_EMAC_RXB=128
CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256
CONFIG_IBM_EMAC_RX_SKB_HEADROOM=0
CONFIG_IBM_EMAC_TAH=y
CONFIG_IBM_EMAC_TXB=128
# CONFIG_ICE is not set
# CONFIG_ICON is not set
CONFIG_ILLEGAL_POINTER_VALUE=0
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_ISA_DMA_API=y
# CONFIG_JFFS2_FS is not set
# CONFIG_KATMAI is not set
CONFIG_KERNEL_GZIP=y
CONFIG_KERNEL_START=0xc0000000
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOWMEM_SIZE=0x30000000
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MATH_EMULATION is not set
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MEMFD_CREATE=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
# CONFIG_MTD_CFI_GEOMETRY is not set
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_BCH=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_BCH=y
CONFIG_MTD_NAND_ECC_SMC=y
CONFIG_MTD_NAND_NDFC=y
# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NEED_SG_DMA_LENGTH=y
# CONFIG_NF_LOG_BRIDGE is not set
CONFIG_NOT_COHERENT_CACHE=y
CONFIG_NO_BOOTMEM=y
CONFIG_NR_IRQS=512
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND=y
# CONFIG_OVERLAY_FS_METACOPY is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
CONFIG_PAGE_OFFSET=0xc0000000
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_MSI=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYSICAL_START=0x00000000
CONFIG_PHYS_64BIT=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PM=y
CONFIG_PM_AUTOSLEEP=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_GC=y
CONFIG_PM_WAKELOCKS_LIMIT=100
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_PPC44x_SIMPLE=y
CONFIG_PPC4xx_CPM=y
CONFIG_PPC4xx_GPIO=y
CONFIG_PPC4xx_MSI=y
CONFIG_PPC4xx_OCM=y
CONFIG_PPC4xx_PCI_EXPRESS=y
# CONFIG_PPC64 is not set
# CONFIG_PPC_47x is not set
# CONFIG_PPC_85xx is not set
# CONFIG_PPC_8xx is not set
CONFIG_PPC_ADV_DEBUG_DACS=2
CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y
CONFIG_PPC_ADV_DEBUG_DVCS=2
CONFIG_PPC_ADV_DEBUG_IACS=4
CONFIG_PPC_ADV_DEBUG_REGS=y
# CONFIG_PPC_BOOK3S_32 is not set
CONFIG_PPC_DCR=y
CONFIG_PPC_DCR_NATIVE=y
# CONFIG_PPC_EARLY_DEBUG is not set
CONFIG_PPC_FPU=y
CONFIG_PPC_INDIRECT_PCI=y
# CONFIG_PPC_IRQ_SOFT_MASK_DEBUG is not set
CONFIG_PPC_LIB_RHEAP=y
CONFIG_PPC_MMU_NOHASH=y
CONFIG_PPC_MSI_BITMAP=y
CONFIG_PPC_PCI_CHOICE=y
# CONFIG_PPC_PTDUMP is not set
CONFIG_PPC_UDBG_16550=y
CONFIG_PPC_WERROR=y
CONFIG_PTE_64BIT=y
# CONFIG_RAINIER is not set
# CONFIG_RANDOM_TRUST_CPU is not set
CONFIG_RAS=y
CONFIG_RD_GZIP=y
# CONFIG_RENESAS_PHY is not set
# CONFIG_RPMSG_VIRTIO is not set
CONFIG_RSEQ=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
# CONFIG_SAM440EP is not set
# CONFIG_SEQUOIA is not set
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SGL_ALLOC=y
CONFIG_SIMPLE_GPIO=y
CONFIG_SPARSE_IRQ=y
CONFIG_SRCU=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
# CONFIG_TAISHAN is not set
CONFIG_TASK_SIZE=0xc0000000
CONFIG_THREAD_SHIFT=13
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TINY_SRCU=y
CONFIG_USB_SUPPORT=y
CONFIG_VDSO32=y
# CONFIG_VIRTIO_MENU is not set
# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
# CONFIG_WARP is not set
CONFIG_WATCHDOG_CORE=y
# CONFIG_WNDR4700 is not set
# CONFIG_XILINX_SYSACE is not set
# CONFIG_XILINX_VCU is not set
# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set
# CONFIG_XIL_AXIS_FIFO is not set
CONFIG_XZ_DEC_BCJ=y
CONFIG_XZ_DEC_POWERPC=y
# CONFIG_YOSEMITE is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

View File

@ -1,74 +0,0 @@
From 538098281ce884a51d2aa4ab445056a41741c6ad Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sat, 17 Nov 2018 17:17:20 +0100
Subject: [PATCH] dt-bindings: dmaengine: dw-dmac: add protection control
property
This patch for the DesignWare AHB Central
Direct Memory Access Controller adds the dma
protection control property:
"snps,dma-protection-control"
as well as the properties specific values defines into
a new include file: include/dt-bindings/dma/dw-dmac.h
Note: The protection control signals are one-to-one
mapped to the AHB HPROT[1:3] signals for this controller.
The HPROT0 (Data Access) is always hardwired to 1.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
Documentation/devicetree/bindings/dma/snps-dma.txt | 4 ++++
MAINTAINERS | 4 +++-
include/dt-bindings/dma/dw-dmac.h | 14 ++++++++++++++
3 files changed, 21 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/dma/dw-dmac.h
--- a/Documentation/devicetree/bindings/dma/snps-dma.txt
+++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
@@ -27,6 +27,10 @@ Optional properties:
general purpose DMA channel allocator. False if not passed.
- multi-block: Multi block transfers supported by hardware. Array property with
one cell per channel. 0: not supported, 1 (default): supported.
+- snps,dma-protection-control: AHB HPROT[3:1] protection setting.
+ The default value is 0 (for non-cacheable, non-buffered,
+ unprivileged data access).
+ Refer to include/dt-bindings/dma/dw-dmac.h for possible values.
Example:
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14075,9 +14075,11 @@ SYNOPSYS DESIGNWARE DMAC DRIVER
M: Viresh Kumar <vireshk@kernel.org>
R: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
S: Maintained
+F: Documentation/devicetree/bindings/dma/snps-dma.txt
+F: drivers/dma/dw/
+F: include/dt-bindings/dma/dw-dmac.h
F: include/linux/dma/dw.h
F: include/linux/platform_data/dma-dw.h
-F: drivers/dma/dw/
SYNOPSYS DESIGNWARE ENTERPRISE ETHERNET DRIVER
M: Jose Abreu <Jose.Abreu@synopsys.com>
--- /dev/null
+++ b/include/dt-bindings/dma/dw-dmac.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+#ifndef __DT_BINDINGS_DMA_DW_DMAC_H__
+#define __DT_BINDINGS_DMA_DW_DMAC_H__
+
+/*
+ * Protection Control bits provide protection against illegal transactions.
+ * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals.
+ */
+#define DW_DMAC_HPROT1_PRIVILEGED_MODE (1 << 0) /* Privileged Mode */
+#define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */
+#define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */
+
+#endif /* __DT_BINDINGS_DMA_DW_DMAC_H__ */

View File

@ -1,34 +0,0 @@
From 1ad0f1603a6b2afb62a1c065409aaa4e43ca7627 Mon Sep 17 00:00:00 2001
From: Eric Biggers <ebiggers@google.com>
Date: Wed, 14 Nov 2018 12:19:39 -0800
Subject: [PATCH 03/15] crypto: drop mask=CRYPTO_ALG_ASYNC from 'cipher' tfm
allocations
'cipher' algorithms (single block ciphers) are always synchronous, so
passing CRYPTO_ALG_ASYNC in the mask to crypto_alloc_cipher() has no
effect. Many users therefore already don't pass it, but some still do.
This inconsistency can cause confusion, especially since the way the
'mask' argument works is somewhat counterintuitive.
Thus, just remove the unneeded CRYPTO_ALG_ASYNC flags.
This patch shouldn't change any actual behavior.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
---
drivers/crypto/amcc/crypto4xx_alg.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/drivers/crypto/amcc/crypto4xx_alg.c
+++ b/drivers/crypto/amcc/crypto4xx_alg.c
@@ -540,8 +540,7 @@ static int crypto4xx_compute_gcm_hash_ke
uint8_t src[16] = { 0 };
int rc = 0;
- aes_tfm = crypto_alloc_cipher("aes", 0, CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_NEED_FALLBACK);
+ aes_tfm = crypto_alloc_cipher("aes", 0, CRYPTO_ALG_NEED_FALLBACK);
if (IS_ERR(aes_tfm)) {
rc = PTR_ERR(aes_tfm);
pr_warn("could not load aes cipher driver: %d\n", rc);

View File

@ -1,30 +0,0 @@
From 67d8208fba1324fa0198f9fc58a9edbe09596947 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Sun, 16 Dec 2018 18:19:46 +0100
Subject: [PATCH 04/15] crypto4xx_core: don't abuse __dma_sync_page
This function is internal to the DMA API implementation. Instead use
the DMA API to properly unmap. Note that the DMA API usage in this
driver is a disaster and urgently needs some work - it is missing all
the unmaps, seems to do a secondary map where it looks like it should
to a unmap in one place to work around cache coherency and the
directions passed in seem to be partially wrong.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Tested-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
drivers/crypto/amcc/crypto4xx_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/crypto/amcc/crypto4xx_core.c
+++ b/drivers/crypto/amcc/crypto4xx_core.c
@@ -592,7 +592,7 @@ static void crypto4xx_aead_done(struct c
pd->pd_ctl_len.bf.pkt_len,
dst);
} else {
- __dma_sync_page(sg_page(dst), dst->offset, dst->length,
+ dma_unmap_page(dev->core_dev->device, pd->dest, dst->length,
DMA_FROM_DEVICE);
}

View File

@ -1,40 +0,0 @@
From 750afb08ca71310fcf0c4e2cb1565c63b8235b60 Mon Sep 17 00:00:00 2001
From: Luis Chamberlain <mcgrof@kernel.org>
Date: Fri, 4 Jan 2019 09:23:09 +0100
Subject: [PATCH 05/15] cross-tree: phase out dma_zalloc_coherent()
We already need to zero out memory for dma_alloc_coherent(), as such
using dma_zalloc_coherent() is superflous. Phase it out.
This change was generated with the following Coccinelle SmPL patch:
@ replace_dma_zalloc_coherent @
expression dev, size, data, handle, flags;
@@
-dma_zalloc_coherent(dev, size, handle, flags)
+dma_alloc_coherent(dev, size, handle, flags)
Suggested-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Luis Chamberlain <mcgrof@kernel.org>
[hch: re-ran the script on the latest tree]
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
drivers/crypto/amcc/crypto4xx_core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/drivers/crypto/amcc/crypto4xx_core.c
+++ b/drivers/crypto/amcc/crypto4xx_core.c
@@ -283,9 +283,9 @@ static u32 crypto4xx_put_pd_to_pdr(struc
*/
static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev)
{
- dev->gdr = dma_zalloc_coherent(dev->core_dev->device,
- sizeof(struct ce_gd) * PPC4XX_NUM_GD,
- &dev->gdr_pa, GFP_ATOMIC);
+ dev->gdr = dma_alloc_coherent(dev->core_dev->device,
+ sizeof(struct ce_gd) * PPC4XX_NUM_GD,
+ &dev->gdr_pa, GFP_ATOMIC);
if (!dev->gdr)
return -ENOMEM;

View File

@ -1,199 +0,0 @@
From d072bfa4885354fff86aa1fb1dbc4f1533c9e0bf Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 23 Dec 2018 02:16:13 +0100
Subject: [PATCH 06/15] crypto: crypto4xx - add prng crypto support
This patch adds support for crypto4xx's ANSI X9.17 Annex C compliant
pseudo random number generator which provides a pseudo random source
for the purpose of generating Initialization Vectors (IV's) for AES
algorithms to the Packet Engine and other pseudo random number
requirements.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
---
drivers/crypto/amcc/crypto4xx_core.c | 87 +++++++++++++++++++++++++
drivers/crypto/amcc/crypto4xx_core.h | 4 ++
drivers/crypto/amcc/crypto4xx_reg_def.h | 1 +
3 files changed, 92 insertions(+)
--- a/drivers/crypto/amcc/crypto4xx_core.c
+++ b/drivers/crypto/amcc/crypto4xx_core.c
@@ -40,9 +40,11 @@
#include <crypto/ctr.h>
#include <crypto/gcm.h>
#include <crypto/sha.h>
+#include <crypto/rng.h>
#include <crypto/scatterwalk.h>
#include <crypto/skcipher.h>
#include <crypto/internal/aead.h>
+#include <crypto/internal/rng.h>
#include <crypto/internal/skcipher.h>
#include "crypto4xx_reg_def.h"
#include "crypto4xx_core.h"
@@ -1042,6 +1044,10 @@ static int crypto4xx_register_alg(struct
rc = crypto_register_ahash(&alg->alg.u.hash);
break;
+ case CRYPTO_ALG_TYPE_RNG:
+ rc = crypto_register_rng(&alg->alg.u.rng);
+ break;
+
default:
rc = crypto_register_skcipher(&alg->alg.u.cipher);
break;
@@ -1071,6 +1077,10 @@ static void crypto4xx_unregister_alg(str
crypto_unregister_aead(&alg->alg.u.aead);
break;
+ case CRYPTO_ALG_TYPE_RNG:
+ crypto_unregister_rng(&alg->alg.u.rng);
+ break;
+
default:
crypto_unregister_skcipher(&alg->alg.u.cipher);
}
@@ -1129,6 +1139,69 @@ static irqreturn_t crypto4xx_ce_interrup
PPC4XX_TMO_ERR_INT);
}
+static int ppc4xx_prng_data_read(struct crypto4xx_device *dev,
+ u8 *data, unsigned int max)
+{
+ unsigned int i, curr = 0;
+ u32 val[2];
+
+ do {
+ /* trigger PRN generation */
+ writel(PPC4XX_PRNG_CTRL_AUTO_EN,
+ dev->ce_base + CRYPTO4XX_PRNG_CTRL);
+
+ for (i = 0; i < 1024; i++) {
+ /* usually 19 iterations are enough */
+ if ((readl(dev->ce_base + CRYPTO4XX_PRNG_STAT) &
+ CRYPTO4XX_PRNG_STAT_BUSY))
+ continue;
+
+ val[0] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_0);
+ val[1] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_1);
+ break;
+ }
+ if (i == 1024)
+ return -ETIMEDOUT;
+
+ if ((max - curr) >= 8) {
+ memcpy(data, &val, 8);
+ data += 8;
+ curr += 8;
+ } else {
+ /* copy only remaining bytes */
+ memcpy(data, &val, max - curr);
+ break;
+ }
+ } while (curr < max);
+
+ return curr;
+}
+
+static int crypto4xx_prng_generate(struct crypto_rng *tfm,
+ const u8 *src, unsigned int slen,
+ u8 *dstn, unsigned int dlen)
+{
+ struct rng_alg *alg = crypto_rng_alg(tfm);
+ struct crypto4xx_alg *amcc_alg;
+ struct crypto4xx_device *dev;
+ int ret;
+
+ amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.rng);
+ dev = amcc_alg->dev;
+
+ mutex_lock(&dev->core_dev->rng_lock);
+ ret = ppc4xx_prng_data_read(dev, dstn, dlen);
+ mutex_unlock(&dev->core_dev->rng_lock);
+ return ret;
+}
+
+
+static int crypto4xx_prng_seed(struct crypto_rng *tfm, const u8 *seed,
+ unsigned int slen)
+{
+ return 0;
+}
+
/**
* Supported Crypto Algorithms
*/
@@ -1298,6 +1371,18 @@ static struct crypto4xx_alg_common crypt
.cra_module = THIS_MODULE,
},
} },
+ { .type = CRYPTO_ALG_TYPE_RNG, .u.rng = {
+ .base = {
+ .cra_name = "stdrng",
+ .cra_driver_name = "crypto4xx_rng",
+ .cra_priority = 300,
+ .cra_ctxsize = 0,
+ .cra_module = THIS_MODULE,
+ },
+ .generate = crypto4xx_prng_generate,
+ .seed = crypto4xx_prng_seed,
+ .seedsize = 0,
+ } },
};
/**
@@ -1367,6 +1452,7 @@ static int crypto4xx_probe(struct platfo
core_dev->dev->core_dev = core_dev;
core_dev->dev->is_revb = is_revb;
core_dev->device = dev;
+ mutex_init(&core_dev->rng_lock);
spin_lock_init(&core_dev->lock);
INIT_LIST_HEAD(&core_dev->dev->alg_list);
ratelimit_default_init(&core_dev->dev->aead_ratelimit);
@@ -1446,6 +1532,7 @@ static int crypto4xx_remove(struct platf
tasklet_kill(&core_dev->tasklet);
/* Un-register with Linux CryptoAPI */
crypto4xx_unregister_alg(core_dev->dev);
+ mutex_destroy(&core_dev->rng_lock);
/* Free all allocated memory */
crypto4xx_stop_all(core_dev);
--- a/drivers/crypto/amcc/crypto4xx_core.h
+++ b/drivers/crypto/amcc/crypto4xx_core.h
@@ -23,8 +23,10 @@
#define __CRYPTO4XX_CORE_H__
#include <linux/ratelimit.h>
+#include <linux/mutex.h>
#include <crypto/internal/hash.h>
#include <crypto/internal/aead.h>
+#include <crypto/internal/rng.h>
#include <crypto/internal/skcipher.h>
#include "crypto4xx_reg_def.h"
#include "crypto4xx_sa.h"
@@ -119,6 +121,7 @@ struct crypto4xx_core_device {
u32 irq;
struct tasklet_struct tasklet;
spinlock_t lock;
+ struct mutex rng_lock;
};
struct crypto4xx_ctx {
@@ -143,6 +146,7 @@ struct crypto4xx_alg_common {
struct skcipher_alg cipher;
struct ahash_alg hash;
struct aead_alg aead;
+ struct rng_alg rng;
} u;
};
--- a/drivers/crypto/amcc/crypto4xx_reg_def.h
+++ b/drivers/crypto/amcc/crypto4xx_reg_def.h
@@ -100,6 +100,7 @@
#define CRYPTO4XX_ENDIAN_CFG 0x000600d8
#define CRYPTO4XX_PRNG_STAT 0x00070000
+#define CRYPTO4XX_PRNG_STAT_BUSY 0x1
#define CRYPTO4XX_PRNG_CTRL 0x00070004
#define CRYPTO4XX_PRNG_SEED_L 0x00070008
#define CRYPTO4XX_PRNG_SEED_H 0x0007000c

View File

@ -1,63 +0,0 @@
From 38cf5533d7a876f75088bacc1277046f30005f28 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Mon, 22 Apr 2019 13:26:01 +0200
Subject: [PATCH 12/15] crypto: crypto4xx - get rid of redundant using_sd
variable
using_sd is used as a stand-in for sa_command_0.bf.scatter
that we need to set anyway, so we might as well just prevent
double-accounting.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
---
drivers/crypto/amcc/crypto4xx_core.c | 6 ++----
drivers/crypto/amcc/crypto4xx_core.h | 1 -
2 files changed, 2 insertions(+), 5 deletions(-)
--- a/drivers/crypto/amcc/crypto4xx_core.c
+++ b/drivers/crypto/amcc/crypto4xx_core.c
@@ -535,7 +535,7 @@ static void crypto4xx_cipher_done(struct
req = skcipher_request_cast(pd_uinfo->async_req);
- if (pd_uinfo->using_sd) {
+ if (pd_uinfo->sa_va->sa_command_0.bf.scatter) {
crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
req->cryptlen, req->dst);
} else {
@@ -589,7 +589,7 @@ static void crypto4xx_aead_done(struct c
u32 icv[AES_BLOCK_SIZE];
int err = 0;
- if (pd_uinfo->using_sd) {
+ if (pd_uinfo->sa_va->sa_command_0.bf.scatter) {
crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
pd->pd_ctl_len.bf.pkt_len,
dst);
@@ -883,7 +883,6 @@ int crypto4xx_build_pd(struct crypto_asy
* we know application give us dst a whole piece of memory
* no need to use scatter ring.
*/
- pd_uinfo->using_sd = 0;
pd_uinfo->first_sd = 0xffffffff;
sa->sa_command_0.bf.scatter = 0;
pd->dest = (u32)dma_map_page(dev->core_dev->device,
@@ -897,7 +896,6 @@ int crypto4xx_build_pd(struct crypto_asy
u32 sd_idx = fst_sd;
nbytes = datalen;
sa->sa_command_0.bf.scatter = 1;
- pd_uinfo->using_sd = 1;
pd_uinfo->first_sd = fst_sd;
sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
pd->dest = sd_dma;
--- a/drivers/crypto/amcc/crypto4xx_core.h
+++ b/drivers/crypto/amcc/crypto4xx_core.h
@@ -64,7 +64,6 @@ union shadow_sa_buf {
struct pd_uinfo {
struct crypto4xx_device *dev;
u32 state;
- u32 using_sd;
u32 first_gd; /* first gather discriptor
used by this packet */
u32 num_gd; /* number of gather discriptor

View File

@ -1,169 +0,0 @@
From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 12 Aug 2014 20:49:27 +0200
Subject: [PATCH 30/36] GPIO: add named gpio exports
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++
drivers/gpio/gpiolib.c | 11 +++++--
include/asm-generic/gpio.h | 5 +++
include/linux/gpio/consumer.h | 8 +++++
4 files changed, 90 insertions(+), 2 deletions(-)
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -23,6 +23,8 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/slab.h>
#include <linux/gpio/machine.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
#include "gpiolib.h"
@@ -660,3 +662,72 @@ void of_gpiochip_remove(struct gpio_chip
gpiochip_remove_pin_ranges(chip);
of_node_put(chip->of_node);
}
+
+#ifdef CONFIG_GPIO_SYSFS
+
+static struct of_device_id gpio_export_ids[] = {
+ { .compatible = "gpio-export" },
+ { /* sentinel */ }
+};
+
+static int of_gpio_export_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *cnp;
+ u32 val;
+ int nb = 0;
+
+ for_each_child_of_node(np, cnp) {
+ const char *name = NULL;
+ int gpio;
+ bool dmc;
+ int max_gpio = 1;
+ int i;
+
+ of_property_read_string(cnp, "gpio-export,name", &name);
+
+ if (!name)
+ max_gpio = of_gpio_count(cnp);
+
+ for (i = 0; i < max_gpio; i++) {
+ unsigned flags = 0;
+ enum of_gpio_flags of_flags;
+
+ gpio = of_get_gpio_flags(cnp, i, &of_flags);
+ if (!gpio_is_valid(gpio))
+ return gpio;
+
+ if (of_flags == OF_GPIO_ACTIVE_LOW)
+ flags |= GPIOF_ACTIVE_LOW;
+
+ if (!of_property_read_u32(cnp, "gpio-export,output", &val))
+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
+ else
+ flags |= GPIOF_IN;
+
+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
+ continue;
+
+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
+ gpio_export_with_name(gpio, dmc, name);
+ nb++;
+ }
+ }
+
+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
+
+ return 0;
+}
+
+static struct platform_driver gpio_export_driver = {
+ .driver = {
+ .name = "gpio-export",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(gpio_export_ids),
+ },
+ .probe = of_gpio_export_probe,
+};
+
+module_platform_driver(gpio_export_driver);
+
+#endif
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g
return gpiod_export(gpio_to_desc(gpio), direction_may_change);
}
+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
+{
+ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
+}
+
static inline int gpio_export_link(struct device *dev, const char *name,
unsigned gpio)
{
--- a/include/linux/gpio/consumer.h
+++ b/include/linux/gpio/consumer.h
@@ -533,6 +533,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_
#if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
int gpiod_export_link(struct device *dev, const char *name,
struct gpio_desc *desc);
@@ -540,6 +541,13 @@ void gpiod_unexport(struct gpio_desc *de
#else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
+static inline int _gpiod_export(struct gpio_desc *desc,
+ bool direction_may_change,
+ const char *name)
+{
+ return -ENOSYS;
+}
+
static inline int gpiod_export(struct gpio_desc *desc,
bool direction_may_change)
{
--- a/drivers/gpio/gpiolib-sysfs.c
+++ b/drivers/gpio/gpiolib-sysfs.c
@@ -568,7 +568,7 @@ static struct class gpio_class = {
*
* Returns zero on success, else an error.
*/
-int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
{
struct gpio_chip *chip;
struct gpio_device *gdev;
@@ -630,6 +630,8 @@ int gpiod_export(struct gpio_desc *desc,
offset = gpio_chip_hwgpio(desc);
if (chip->names && chip->names[offset])
ioname = chip->names[offset];
+ if (name)
+ ioname = name;
dev = device_create_with_groups(&gpio_class, &gdev->dev,
MKDEV(0, 0), data, gpio_groups,
@@ -651,6 +653,12 @@ err_unlock:
gpiod_dbg(desc, "%s: status %d\n", __func__, status);
return status;
}
+EXPORT_SYMBOL_GPL(__gpiod_export);
+
+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
+{
+ return __gpiod_export(desc, direction_may_change, NULL);
+}
EXPORT_SYMBOL_GPL(gpiod_export);
static int match_export(struct device *dev, const void *desc)

View File

@ -1,30 +0,0 @@
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -131,6 +131,17 @@ config CANYONLANDS
help
This option enables support for the AMCC PPC460EX evaluation board.
+config APOLLO3G
+ bool "Apollo3G"
+ depends on 44x
+ default n
+ select PPC44x_SIMPLE
+ select APM821xx
+ select IBM_EMAC_RGMII
+ select 460EX
+ help
+ This option enables support for the AMCC Apollo 3G board.
+
config GLACIER
bool "Glacier"
depends on 44x
--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
@@ -50,6 +50,7 @@ machine_device_initcall(ppc44x_simple, p
* board.c file for it rather than adding it to this list.
*/
static char *board[] __initdata = {
+ "amcc,apollo3g",
"amcc,arches",
"amcc,bamboo",
"apm,bluestone",

View File

@ -1,32 +0,0 @@
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -4,6 +4,7 @@ ifneq ($(CONFIG_PPC4xx_CPM),y)
obj-y += idle.o
endif
obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o
+obj-$(CONFIG_WNDR4700) += wndr4700.o
obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_SAM440EP) += sam440ep.o
obj-$(CONFIG_WARP) += warp.o
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -260,6 +260,19 @@ config ICON
help
This option enables support for the AMCC PPC440SPe evaluation board.
+config WNDR4700
+ bool "WNDR4700"
+ depends on 44x
+ default n
+ select APM821xx
+ select PCI_MSI
+ select PPC4xx_MSI
+ select PPC4xx_PCI_EXPRESS
+ select IBM_EMAC_RGMII
+ select 460EX
+ help
+ This option enables support for the Netgear WNDR4700/WNDR4720 board.
+
config XILINX_VIRTEX440_GENERIC_BOARD
bool "Generic Xilinx Virtex 5 FXT board support"
depends on 44x

View File

@ -1,51 +0,0 @@
--- a/arch/powerpc/platforms/4xx/pci.c
+++ b/arch/powerpc/platforms/4xx/pci.c
@@ -1060,15 +1060,24 @@ static int __init apm821xx_pciex_init_po
u32 val;
/*
- * Do a software reset on PCIe ports.
- * This code is to fix the issue that pci drivers doesn't re-assign
- * bus number for PCIE devices after Uboot
- * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
- * PT quad port, SAS LSI 1064E)
+ * Only reset the PHY when no link is currently established.
+ * This is for the Atheros PCIe board which has problems to establish
+ * the link (again) after this PHY reset. All other currently tested
+ * PCIe boards don't show this problem.
*/
-
- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
- mdelay(10);
+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
+ if (!(val & 0x00001000)) {
+ /*
+ * Do a software reset on PCIe ports.
+ * This code is to fix the issue that pci drivers doesn't re-assign
+ * bus number for PCIE devices after Uboot
+ * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
+ * PT quad port, SAS LSI 1064E)
+ */
+
+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
+ mdelay(10);
+ }
if (port->endpoint)
val = PTYPE_LEGACY_ENDPOINT << 20;
@@ -1085,9 +1094,12 @@ static int __init apm821xx_pciex_init_po
mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
- mdelay(50);
- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
+ if (!(val & 0x00001000)) {
+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
+ mdelay(50);
+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
+ }
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |

View File

@ -1,14 +0,0 @@
--- a/arch/powerpc/platforms/4xx/pci.c
+++ b/arch/powerpc/platforms/4xx/pci.c
@@ -1903,9 +1903,9 @@ static void __init ppc4xx_configure_pcie
* if it works
*/
out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
- out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
+ out_le32(mbase + PECFG_PIM0LAH, 0x00000008);
out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
- out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
+ out_le32(mbase + PECFG_PIM1LAH, 0x0000000c);
out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
out_le32(mbase + PECFG_PIM01SAL, 0x00000000);

View File

@ -1,545 +0,0 @@
From 419992bae5aaa4e06402e0b7c79fcf7bcb6b4764 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Thu, 2 Jun 2016 00:48:46 +0200
Subject: [PATCH] usb: xhci: add firmware loader for uPD720201 and uPD720202
w/o ROM
This patch adds a firmware loader for the uPD720201K8-711-BAC-A
and uPD720202K8-711-BAA-A variant. Both of these chips are listed
in Renesas' R19UH0078EJ0500 Rev.5.00 "User's Manual: Hardware" as
devices which need the firmware loader on page 2 in order to
work as they "do not support the External ROM".
The "Firmware Download Sequence" is describe in chapter
"7.1 FW Download Interface" R19UH0078EJ0500 Rev.5.00 page 131.
The firmware "K2013080.mem" is available from a USB3.0 Host to
PCIe Adapter (PP2U-E card) "Firmware download" archive. An
alternative version can be sourced from Netgear's WNDR4700 GPL
archives.
The release notes of the PP2U-E's "Firmware Download" ver 2.0.1.3
(2012-06-15) state that the firmware is for the following devices:
- uPD720201 ES 2.0 sample whose revision ID is 2.
- uPD720201 ES 2.1 sample & CS sample & Mass product, ID is 3.
- uPD720202 ES 2.0 sample & CS sample & Mass product, ID is 2.
If someone from Renesas is listening: It would be great, if these
firmwares could be added to linux-firmware.git.
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
---
drivers/usb/host/xhci-pci.c | 492 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 492 insertions(+)
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -12,6 +12,8 @@
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/acpi.h>
+#include <linux/firmware.h>
+#include <asm/unaligned.h>
#include "xhci.h"
#include "xhci-trace.h"
@@ -268,6 +270,458 @@ static void xhci_pme_acpi_rtd3_enable(st
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
#endif /* CONFIG_ACPI */
+static const struct renesas_fw_entry {
+ const char *firmware_name;
+ u16 device;
+ u8 revision;
+ u16 expected_version;
+} renesas_fw_table[] = {
+ /*
+ * Only the uPD720201K8-711-BAC-A or uPD720202K8-711-BAA-A
+ * are listed in R19UH0078EJ0500 Rev.5.00 as devices which
+ * need the software loader.
+ *
+ * PP2U/ReleaseNote_USB3-201-202-FW.txt:
+ *
+ * Note: This firmware is for the following devices.
+ * - uPD720201 ES 2.0 sample whose revision ID is 2.
+ * - uPD720201 ES 2.1 sample & CS sample & Mass product, ID is 3.
+ * - uPD720202 ES 2.0 sample & CS sample & Mass product, ID is 2.
+ */
+ { "K2013080.mem", 0x0014, 0x02, 0x2013 },
+ { "K2013080.mem", 0x0014, 0x03, 0x2013 },
+ { "K2013080.mem", 0x0015, 0x02, 0x2013 },
+};
+
+static const struct renesas_fw_entry *renesas_needs_fw_dl(struct pci_dev *dev)
+{
+ const struct renesas_fw_entry *entry;
+ size_t i;
+
+ /* This loader will only work with a RENESAS device. */
+ if (!(dev->vendor == PCI_VENDOR_ID_RENESAS))
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE(renesas_fw_table); i++) {
+ entry = &renesas_fw_table[i];
+ if (entry->device == dev->device &&
+ entry->revision == dev->revision)
+ return entry;
+ }
+
+ return NULL;
+}
+
+static int renesas_fw_download_image(struct pci_dev *dev,
+ const u32 *fw,
+ size_t step)
+{
+ size_t i;
+ int err;
+ u8 fw_status;
+ bool data0_or_data1;
+
+ /*
+ * The hardware does alternate between two 32-bit pages.
+ * (This is because each row of the firmware is 8 bytes).
+ *
+ * for even steps we use DATA0, for odd steps DATA1.
+ */
+ data0_or_data1 = (step & 1) == 1;
+
+ /* step+1. Read "Set DATAX" and confirm it is cleared. */
+ for (i = 0; i < 10000; i++) {
+ err = pci_read_config_byte(dev, 0xF5, &fw_status);
+ if (err)
+ return pcibios_err_to_errno(err);
+ if (!(fw_status & BIT(data0_or_data1)))
+ break;
+
+ udelay(1);
+ }
+ if (i == 10000)
+ return -ETIMEDOUT;
+
+ /*
+ * step+2. Write FW data to "DATAX".
+ * "LSB is left" => force little endian
+ */
+ err = pci_write_config_dword(dev, data0_or_data1 ? 0xFC : 0xF8,
+ (__force u32) cpu_to_le32(fw[step]));
+ if (err)
+ return pcibios_err_to_errno(err);
+
+ udelay(100);
+
+ /* step+3. Set "Set DATAX". */
+ err = pci_write_config_byte(dev, 0xF5, BIT(data0_or_data1));
+ if (err)
+ return pcibios_err_to_errno(err);
+
+ return 0;
+}
+
+static int renesas_fw_verify(struct pci_dev *dev,
+ const void *fw_data,
+ size_t length)
+{
+ const struct renesas_fw_entry *entry = renesas_needs_fw_dl(dev);
+ u16 fw_version_pointer;
+ u16 fw_version;
+
+ if (!entry)
+ return -EINVAL;
+
+ /*
+ * The Firmware's Data Format is describe in
+ * "6.3 Data Format" R19UH0078EJ0500 Rev.5.00 page 124
+ */
+
+ /* "Each row is 8 bytes". => firmware size must be a multiple of 8. */
+ if (length % 8 != 0) {
+ dev_err(&dev->dev, "firmware size is not a multipe of 8.");
+ return -EINVAL;
+ }
+
+ /*
+ * The bootrom chips of the big brother have sizes up to 64k, let's
+ * assume that's the biggest the firmware can get.
+ */
+ if (length < 0x1000 || length >= 0x10000) {
+ dev_err(&dev->dev, "firmware is size %zd is not (4k - 64k).",
+ length);
+ return -EINVAL;
+ }
+
+ /* The First 2 bytes are fixed value (55aa). "LSB on Left" */
+ if (get_unaligned_le16(fw_data) != 0x55aa) {
+ dev_err(&dev->dev, "no valid firmware header found.");
+ return -EINVAL;
+ }
+
+ /* verify the firmware version position and print it. */
+ fw_version_pointer = get_unaligned_le16(fw_data + 4);
+ if (fw_version_pointer + 2 >= length) {
+ dev_err(&dev->dev, "firmware version pointer is outside of the firmware image.");
+ return -EINVAL;
+ }
+
+ fw_version = get_unaligned_le16(fw_data + fw_version_pointer);
+ dev_dbg(&dev->dev, "got firmware version: %02x.", fw_version);
+
+ if (fw_version != entry->expected_version) {
+ dev_err(&dev->dev, "firmware version mismatch, expected version: %02x.",
+ entry->expected_version);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int renesas_fw_check_running(struct pci_dev *pdev)
+{
+ int err;
+ u8 fw_state;
+
+ /*
+ * Test if the device is actually needing the firmware. As most
+ * BIOSes will initialize the device for us. If the device is
+ * initialized.
+ */
+ err = pci_read_config_byte(pdev, 0xF4, &fw_state);
+ if (err)
+ return pcibios_err_to_errno(err);
+
+ /*
+ * Check if "FW Download Lock" is locked. If it is and the FW is
+ * ready we can simply continue. If the FW is not ready, we have
+ * to give up.
+ */
+ if (fw_state & BIT(1)) {
+ dev_dbg(&pdev->dev, "FW Download Lock is engaged.");
+
+ if (fw_state & BIT(4))
+ return 0;
+
+ dev_err(&pdev->dev, "FW Download Lock is set and FW is not ready. Giving Up.");
+ return -EIO;
+ }
+
+ /*
+ * Check if "FW Download Enable" is set. If someone (us?) tampered
+ * with it and it can't be resetted, we have to give up too... and
+ * ask for a forgiveness and a reboot.
+ */
+ if (fw_state & BIT(0)) {
+ dev_err(&pdev->dev, "FW Download Enable is stale. Giving Up (poweroff/reboot needed).");
+ return -EIO;
+ }
+
+ /* Otherwise, Check the "Result Code" Bits (6:4) and act accordingly */
+ switch ((fw_state & 0x70)) {
+ case 0: /* No result yet */
+ dev_dbg(&pdev->dev, "FW is not ready/loaded yet.");
+
+ /* tell the caller, that this device needs the firmware. */
+ return 1;
+
+ case BIT(4): /* Success, device should be working. */
+ dev_dbg(&pdev->dev, "FW is ready.");
+ return 0;
+
+ case BIT(5): /* Error State */
+ dev_err(&pdev->dev, "hardware is in an error state. Giving up (poweroff/reboot needed).");
+ return -ENODEV;
+
+ default: /* All other states are marked as "Reserved states" */
+ dev_err(&pdev->dev, "hardware is in an invalid state %x. Giving up (poweroff/reboot needed).",
+ (fw_state & 0x70) >> 4);
+ return -EINVAL;
+ }
+}
+
+static int renesas_hw_check_run_stop_busy(struct pci_dev *pdev)
+{
+#if 0
+ u32 val;
+
+ /*
+ * 7.1.3 Note 3: "... must not set 'FW Download Enable' when
+ * 'RUN/STOP' of USBCMD Register is set"
+ */
+ val = readl(hcd->regs + 0x20);
+ if (val & BIT(0)) {
+ dev_err(&pdev->dev, "hardware is busy and can't receive a FW.");
+ return -EBUSY;
+ }
+#endif
+ return 0;
+}
+
+static int renesas_fw_download(struct pci_dev *pdev,
+ const struct firmware *fw, unsigned int retry_counter)
+{
+ const u32 *fw_data = (const u32 *) fw->data;
+ size_t i;
+ int err;
+ u8 fw_status;
+
+ /*
+ * For more information and the big picture: please look at the
+ * "Firmware Download Sequence" in "7.1 FW Download Interface"
+ * of R19UH0078EJ0500 Rev.5.00 page 131
+ */
+ err = renesas_hw_check_run_stop_busy(pdev);
+ if (err)
+ return err;
+
+ /*
+ * 0. Set "FW Download Enable" bit in the
+ * "FW Download Control & Status Register" at 0xF4
+ */
+ err = pci_write_config_byte(pdev, 0xF4, BIT(0));
+ if (err)
+ return pcibios_err_to_errno(err);
+
+ /* 1 - 10 follow one step after the other. */
+ for (i = 0; i < fw->size / 4; i++) {
+ err = renesas_fw_download_image(pdev, fw_data, i);
+ if (err) {
+ dev_err(&pdev->dev, "Firmware Download Step %zd failed at position %zd bytes with (%d).",
+ i, i * 4, err);
+ return err;
+ }
+ }
+
+ /*
+ * This sequence continues until the last data is written to
+ * "DATA0" or "DATA1". Naturally, we wait until "SET DATA0/1"
+ * is cleared by the hardware beforehand.
+ */
+ for (i = 0; i < 10000; i++) {
+ err = pci_read_config_byte(pdev, 0xF5, &fw_status);
+ if (err)
+ return pcibios_err_to_errno(err);
+ if (!(fw_status & (BIT(0) | BIT(1))))
+ break;
+
+ udelay(1);
+ }
+ if (i == 10000)
+ dev_warn(&pdev->dev, "Final Firmware Download step timed out.");
+
+ /*
+ * 11. After finishing writing the last data of FW, the
+ * System Software must clear "FW Download Enable"
+ */
+ err = pci_write_config_byte(pdev, 0xF4, 0);
+ if (err)
+ return pcibios_err_to_errno(err);
+
+ /* 12. Read "Result Code" and confirm it is good. */
+ for (i = 0; i < 10000; i++) {
+ err = pci_read_config_byte(pdev, 0xF4, &fw_status);
+ if (err)
+ return pcibios_err_to_errno(err);
+ if (fw_status & BIT(4))
+ break;
+
+ udelay(1);
+ }
+ if (i == 10000) {
+ /* Timed out / Error - let's see if we can fix this */
+ err = renesas_fw_check_running(pdev);
+ switch (err) {
+ case 0: /*
+ * we shouldn't end up here.
+ * maybe it took a little bit longer.
+ * But all should be well?
+ */
+ break;
+
+ case 1: /* (No result yet? - we can try to retry) */
+ if (retry_counter < 10) {
+ retry_counter++;
+ dev_warn(&pdev->dev, "Retry Firmware download: %d try.",
+ retry_counter);
+ return renesas_fw_download(pdev, fw,
+ retry_counter);
+ }
+ return -ETIMEDOUT;
+
+ default:
+ return err;
+ }
+ }
+ /*
+ * Optional last step: Engage Firmware Lock
+ *
+ * err = pci_write_config_byte(pdev, 0xF4, BIT(2));
+ * if (err)
+ * return pcibios_err_to_errno(err);
+ */
+
+ return 0;
+}
+
+struct renesas_fw_ctx {
+ struct pci_dev *pdev;
+ const struct pci_device_id *id;
+ bool resume;
+};
+
+static int xhci_pci_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id);
+
+static void renesas_fw_callback(const struct firmware *fw,
+ void *context)
+{
+ struct renesas_fw_ctx *ctx = context;
+ struct pci_dev *pdev = ctx->pdev;
+ struct device *parent = pdev->dev.parent;
+ int err = -ENOENT;
+
+ if (fw) {
+ err = renesas_fw_verify(pdev, fw->data, fw->size);
+ if (!err) {
+ err = renesas_fw_download(pdev, fw, 0);
+ release_firmware(fw);
+ if (!err) {
+ if (ctx->resume)
+ return;
+
+ err = xhci_pci_probe(pdev, ctx->id);
+ if (!err) {
+ /* everything worked */
+ devm_kfree(&pdev->dev, ctx);
+ return;
+ }
+
+ /* in case of an error - fall through */
+ } else {
+ dev_err(&pdev->dev, "firmware failed to download (%d).",
+ err);
+ }
+ }
+ } else {
+ dev_err(&pdev->dev, "firmware failed to load (%d).", err);
+ }
+
+ dev_info(&pdev->dev, "Unloading driver");
+
+ if (parent)
+ device_lock(parent);
+
+ device_release_driver(&pdev->dev);
+
+ if (parent)
+ device_unlock(parent);
+
+ pci_dev_put(pdev);
+}
+
+static int renesas_fw_alive_check(struct pci_dev *pdev)
+{
+ const struct renesas_fw_entry *entry;
+ int err;
+
+ /* check if we have a eligible RENESAS' uPD720201/2 w/o FW. */
+ entry = renesas_needs_fw_dl(pdev);
+ if (!entry)
+ return 0;
+
+ err = renesas_fw_check_running(pdev);
+ /* Also go ahead, if the firmware is running */
+ if (err == 0)
+ return 0;
+
+ /* At this point, we can be sure that the FW isn't ready. */
+ return err;
+}
+
+static int renesas_fw_download_to_hw(struct pci_dev *pdev,
+ const struct pci_device_id *id,
+ bool do_resume)
+{
+ const struct renesas_fw_entry *entry;
+ struct renesas_fw_ctx *ctx;
+ int err;
+
+ /* check if we have a eligible RENESAS' uPD720201/2 w/o FW. */
+ entry = renesas_needs_fw_dl(pdev);
+ if (!entry)
+ return 0;
+
+ err = renesas_fw_check_running(pdev);
+ /* Continue ahead, if the firmware is already running. */
+ if (err == 0)
+ return 0;
+
+ if (err != 1)
+ return err;
+
+ ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+ ctx->pdev = pdev;
+ ctx->resume = do_resume;
+ ctx->id = id;
+
+ pci_dev_get(pdev);
+ err = request_firmware_nowait(THIS_MODULE, 1, entry->firmware_name,
+ &pdev->dev, GFP_KERNEL, ctx, renesas_fw_callback);
+ if (err) {
+ pci_dev_put(pdev);
+ return err;
+ }
+
+ /*
+ * The renesas_fw_callback() callback will continue the probe
+ * process, once it aquires the firmware.
+ */
+ return 1;
+}
+
/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
@@ -309,6 +763,22 @@ static int xhci_pci_probe(struct pci_dev
struct hc_driver *driver;
struct usb_hcd *hcd;
+ /*
+ * Check if this device is a RENESAS uPD720201/2 device.
+ * Otherwise, we can continue with xhci_pci_probe as usual.
+ */
+ retval = renesas_fw_download_to_hw(dev, id, false);
+ switch (retval) {
+ case 0:
+ break;
+
+ case 1: /* let it load the firmware and recontinue the probe. */
+ return 0;
+
+ default:
+ return retval;
+ }
+
driver = (struct hc_driver *)id->driver_data;
/* Prevent runtime suspending between USB-2 and USB-3 initialization */
@@ -367,6 +837,16 @@ static void xhci_pci_remove(struct pci_d
{
struct xhci_hcd *xhci;
+ if (renesas_fw_alive_check(dev)) {
+ /*
+ * bail out early, if this was a renesas device w/o FW.
+ * Else we might hit the NMI watchdog in xhci_handsake
+ * during xhci_reset as part of the driver's unloading.
+ * which we forced in the renesas_fw_callback().
+ */
+ return;
+ }
+
xhci = hcd_to_xhci(pci_get_drvdata(dev));
xhci->xhc_state |= XHCI_STATE_REMOVING;
if (xhci->shared_hcd) {

View File

@ -1,53 +0,0 @@
From a0dc613140bab907a3d5787a7ae7b0638bf674d0 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Thu, 23 Jun 2016 20:28:20 +0200
Subject: [PATCH] usb: xhci: force MSI for uPD720201 and
uPD720202
The APM82181 does not support MSI-X. When probed, it will
produce a noisy warning.
---
drivers/usb/host/pci-quirks.c | 362 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 362 insertions(+)
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -218,6 +218,7 @@ static void xhci_pci_quirks(struct devic
pdev->device == 0x0015) {
xhci->quirks |= XHCI_RESET_ON_RESUME;
xhci->quirks |= XHCI_ZERO_64B_REGS;
+ xhci->quirks |= XHCI_FORCE_MSI;
}
if (pdev->vendor == PCI_VENDOR_ID_VIA)
xhci->quirks |= XHCI_RESET_ON_RESUME;
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -422,10 +422,14 @@ static int xhci_try_enable_msi(struct us
free_irq(hcd->irq, hcd);
hcd->irq = 0;
- ret = xhci_setup_msix(xhci);
- if (ret)
- /* fall back to msi*/
+ if (xhci->quirks & XHCI_FORCE_MSI) {
ret = xhci_setup_msi(xhci);
+ } else {
+ ret = xhci_setup_msix(xhci);
+ if (ret)
+ /* fall back to msi*/
+ ret = xhci_setup_msi(xhci);
+ }
if (!ret) {
hcd->msi_enabled = 1;
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1883,6 +1883,7 @@ struct xhci_hcd {
/* support xHCI 0.96 spec USB2 software LPM */
unsigned sw_lpm_support:1;
/* support xHCI 1.0 spec USB2 hardware LPM */
+#define XHCI_FORCE_MSI (1 << 24)
unsigned hw_lpm_support:1;
/* Broken Suspend flag for SNPS Suspend resume issue */
unsigned broken_suspend:1;

View File

@ -1,65 +0,0 @@
From 694f9bfb8efaef8a33e8992015ff9d0866faf4a2 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 17 Dec 2017 17:27:15 +0100
Subject: [PATCH 1/2] hwmon: tc654 add detection routine
This patch adds a detection routine for the TC654/TC655
chips. Both IDs are listed in the Datasheet.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
drivers/hwmon/tc654.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
--- a/drivers/hwmon/tc654.c
+++ b/drivers/hwmon/tc654.c
@@ -64,6 +64,11 @@ enum tc654_regs {
/* Register data is read (and cached) at most once per second. */
#define TC654_UPDATE_INTERVAL HZ
+/* Manufacturer and Version Identification Register Values */
+#define TC654_MFR_ID_MICROCHIP 0x84
+#define TC654_VER_ID 0x00
+#define TC655_VER_ID 0x01
+
struct tc654_data {
struct i2c_client *client;
@@ -497,6 +502,29 @@ static const struct i2c_device_id tc654_
{}
};
+static int
+tc654_detect(struct i2c_client *new_client, struct i2c_board_info *info)
+{
+ struct i2c_adapter *adapter = new_client->adapter;
+ int manufacturer, product;
+
+ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+ return -ENODEV;
+
+ manufacturer = i2c_smbus_read_byte_data(new_client, TC654_REG_MFR_ID);
+ if (manufacturer != TC654_MFR_ID_MICROCHIP)
+ return -ENODEV;
+
+ product = i2c_smbus_read_byte_data(new_client, TC654_REG_VER_ID);
+ if (!((product == TC654_VER_ID) || (product == TC655_VER_ID)))
+ return -ENODEV;
+
+ strlcpy(info->type, product == TC654_VER_ID ? "tc654" : "tc655",
+ I2C_NAME_SIZE);
+ return 0;
+}
+
+
MODULE_DEVICE_TABLE(i2c, tc654_id);
static struct i2c_driver tc654_driver = {
@@ -505,6 +533,7 @@ static struct i2c_driver tc654_driver =
},
.probe = tc654_probe,
.id_table = tc654_id,
+ .detect = tc654_detect,
};
module_i2c_driver(tc654_driver);

View File

@ -1,174 +0,0 @@
From 15ae701189744d321d3a1264ff46f8871e8765ee Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 17 Dec 2017 17:29:13 +0100
Subject: [PATCH] hwmon: tc654: add thermal_cooling device
This patch adds a thermaL_cooling device to the tc654 driver.
This allows the chip to be used for DT-based cooling.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
drivers/hwmon/tc654.c | 103 +++++++++++++++++++++++++++++++++++++++++---------
1 file changed, 86 insertions(+), 17 deletions(-)
--- a/drivers/hwmon/tc654.c
+++ b/drivers/hwmon/tc654.c
@@ -24,6 +24,7 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/slab.h>
+#include <linux/thermal.h>
#include <linux/util_macros.h>
enum tc654_regs {
@@ -141,6 +142,9 @@ struct tc654_data {
* writable register used to control the duty
* cycle of the V OUT output.
*/
+
+ /* optional cooling device */
+ struct thermal_cooling_device *cdev;
};
/* helper to grab and cache data, at most one time per second */
@@ -376,36 +380,30 @@ static ssize_t set_pwm_mode(struct devic
static const int tc654_pwm_map[16] = { 77, 88, 102, 112, 124, 136, 148, 160,
172, 184, 196, 207, 219, 231, 243, 255};
+static int get_pwm(struct tc654_data *data)
+{
+ if (data->config & TC654_REG_CONFIG_SDM)
+ return 0;
+ else
+ return tc654_pwm_map[data->duty_cycle];
+}
+
static ssize_t show_pwm(struct device *dev, struct device_attribute *da,
char *buf)
{
struct tc654_data *data = tc654_update_client(dev);
- int pwm;
if (IS_ERR(data))
return PTR_ERR(data);
- if (data->config & TC654_REG_CONFIG_SDM)
- pwm = 0;
- else
- pwm = tc654_pwm_map[data->duty_cycle];
-
- return sprintf(buf, "%d\n", pwm);
+ return sprintf(buf, "%d\n", get_pwm(data));
}
-static ssize_t set_pwm(struct device *dev, struct device_attribute *da,
- const char *buf, size_t count)
+static int _set_pwm(struct tc654_data *data, unsigned long val)
{
- struct tc654_data *data = dev_get_drvdata(dev);
struct i2c_client *client = data->client;
- unsigned long val;
int ret;
- if (kstrtoul(buf, 10, &val))
- return -EINVAL;
- if (val > 255)
- return -EINVAL;
-
mutex_lock(&data->update_lock);
if (val == 0)
@@ -425,6 +423,22 @@ static ssize_t set_pwm(struct device *de
out:
mutex_unlock(&data->update_lock);
+ return ret;
+}
+
+static ssize_t set_pwm(struct device *dev, struct device_attribute *da,
+ const char *buf, size_t count)
+{
+ struct tc654_data *data = dev_get_drvdata(dev);
+ unsigned long val;
+ int ret;
+
+ if (kstrtoul(buf, 10, &val))
+ return -EINVAL;
+ if (val > 255)
+ return -EINVAL;
+
+ ret = _set_pwm(data, val);
return ret < 0 ? ret : count;
}
@@ -462,6 +476,47 @@ static struct attribute *tc654_attrs[] =
ATTRIBUTE_GROUPS(tc654);
+/* cooling device */
+
+static int tc654_get_max_state(struct thermal_cooling_device *cdev,
+ unsigned long *state)
+{
+ *state = 255;
+ return 0;
+}
+
+static int tc654_get_cur_state(struct thermal_cooling_device *cdev,
+ unsigned long *state)
+{
+ struct tc654_data *data = tc654_update_client(cdev->devdata);
+
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
+ *state = get_pwm(data);
+ return 0;
+}
+
+static int tc654_set_cur_state(struct thermal_cooling_device *cdev,
+ unsigned long state)
+{
+ struct tc654_data *data = tc654_update_client(cdev->devdata);
+
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
+ if (state > 255)
+ return -EINVAL;
+
+ return _set_pwm(data, state);
+}
+
+static const struct thermal_cooling_device_ops tc654_fan_cool_ops = {
+ .get_max_state = tc654_get_max_state,
+ .get_cur_state = tc654_get_cur_state,
+ .set_cur_state = tc654_set_cur_state,
+};
+
/*
* device probe and removal
*/
@@ -493,7 +548,21 @@ static int tc654_probe(struct i2c_client
hwmon_dev =
devm_hwmon_device_register_with_groups(dev, client->name, data,
tc654_groups);
- return PTR_ERR_OR_ZERO(hwmon_dev);
+ if (IS_ERR(hwmon_dev))
+ return PTR_ERR(hwmon_dev);
+
+#if IS_ENABLED(CONFIG_OF)
+ /* Optional cooling device register for Device tree platforms */
+ data->cdev = thermal_of_cooling_device_register(client->dev.of_node,
+ "tc654", hwmon_dev,
+ &tc654_fan_cool_ops);
+#else /* CONFIG_OF */
+ /* Optional cooling device register for non Device tree platforms */
+ data->cdev = thermal_cooling_device_register("tc654", hwmon_dev,
+ &tc654_fan_cool_ops);
+#endif /* CONFIG_OF */
+
+ return PTR_ERR_OR_ZERO(data->cdev);
}
static const struct i2c_device_id tc654_id[] = {

View File

@ -1,91 +0,0 @@
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_ARCH_AXXIA is not set
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_VIRT=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_ARM=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_LPAE=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_ARM_PSCI=y
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
CONFIG_ARM_VIRT_EXT=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_CACHE_L2X0=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_HAS_ASID=y
# CONFIG_CPU_ICACHE_DISABLE is not set
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
# CONFIG_DEBUG_USER is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_HAVE_SMP=y
# CONFIG_HUGETLBFS is not set
CONFIG_HZ_FIXED=0
CONFIG_HZ_PERIODIC=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGHT_HAVE_PCI=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_NEON=y
CONFIG_NR_CPUS=4
CONFIG_OLD_SIGACTION=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PAGE_OFFSET=0xC0000000
# CONFIG_PCI_V3_SEMI is not set
CONFIG_PERF_USE_VMALLOC=y
# CONFIG_PL310_ERRATA_588369 is not set
# CONFIG_PL310_ERRATA_727915 is not set
# CONFIG_PL310_ERRATA_753970 is not set
# CONFIG_PL310_ERRATA_769419 is not set
CONFIG_RTC_MC146818_LIB=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SMP_ON_UP=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
# CONFIG_THUMB2_KERNEL is not set
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0

View File

@ -1,230 +0,0 @@
CONFIG_64BIT=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_INLINE_READ_LOCK=y
CONFIG_ARCH_INLINE_READ_LOCK_BH=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_READ_UNLOCK=y
CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_SPIN_LOCK=y
CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_WRITE_LOCK=y
CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARM64=y
# CONFIG_ARM64_16K_PAGES is not set
CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_64K_PAGES is not set
CONFIG_ARM64_CONT_SHIFT=4
CONFIG_ARM64_CRYPTO=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_HW_AFDBM=y
# CONFIG_ARM64_LSE_ATOMICS is not set
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PAN=y
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
# CONFIG_ARM64_PMEM is not set
# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
CONFIG_ARM64_SSBD=y
CONFIG_ARM64_SVE=y
CONFIG_ARM64_UAO=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_48 is not set
CONFIG_ARM64_VHE=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
CONFIG_ATOMIC64_SELFTEST=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLKSRC_VERSATILE=y
CONFIG_CLK_SP810=y
CONFIG_CLK_VEXPRESS_OSC=y
CONFIG_COMMON_CLK_VERSATILE=y
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_IDLE=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_PM=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CHACHA20_NEON=y
CONFIG_CRYPTO_CRC32_ARM64_CE=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
# CONFIG_CRYPTO_SHA3_ARM64 is not set
CONFIG_CRYPTO_SHA512_ARM64=y
# CONFIG_CRYPTO_SHA512_ARM64_CE is not set
CONFIG_CRYPTO_SIMD=y
# CONFIG_CRYPTO_SM3_ARM64_CE is not set
# CONFIG_CRYPTO_SM4_ARM64_CE is not set
CONFIG_DMA_DIRECT_OPS=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DRM=y
CONFIG_DRM_BOCHS=y
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_PANEL=y
CONFIG_DRM_PANEL_BRIDGE=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
# CONFIG_DRM_PANEL_SIMPLE is not set
CONFIG_DRM_QXL=y
CONFIG_DRM_TTM=y
CONFIG_DRM_VIRTIO_GPU=y
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_DEBUG_BUGVERBOSE=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_HAVE_PATA_PLATFORM=y
CONFIG_HDMI=y
CONFIG_HOLES_IN_ZONE=y
# CONFIG_HUGETLBFS is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INLINE_READ_LOCK=y
CONFIG_INLINE_READ_LOCK_BH=y
CONFIG_INLINE_READ_LOCK_IRQ=y
CONFIG_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_INLINE_READ_UNLOCK_BH=y
CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_SPIN_LOCK=y
CONFIG_INLINE_SPIN_LOCK_BH=y
CONFIG_INLINE_SPIN_LOCK_IRQ=y
CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_INLINE_SPIN_TRYLOCK=y
CONFIG_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_INLINE_SPIN_UNLOCK_BH=y
CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_WRITE_LOCK=y
CONFIG_INLINE_WRITE_LOCK_BH=y
CONFIG_INLINE_WRITE_LOCK_IRQ=y
CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_INLINE_WRITE_UNLOCK_BH=y
CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_PLATFORM is not set
CONFIG_MFD_CORE=y
CONFIG_MFD_SYSCON=y
CONFIG_MFD_VEXPRESS_SYSREG=y
CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
# CONFIG_MMC_TIFM_SD is not set
CONFIG_MODULES_USE_ELF_RELA=y
# CONFIG_MTD_PHYSMAP_OF is not set
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=64
# CONFIG_NUMA is not set
CONFIG_PM=y
CONFIG_PM_CLK=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_VEXPRESS=y
CONFIG_POWER_SUPPLY=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_SMC91X=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SYNC_FILE=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_VEXPRESS_SYSCFG=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_VMAP_STACK=y
CONFIG_ZONE_DMA32=y

View File

@ -1,218 +0,0 @@
CONFIG_9P_FS=y
# CONFIG_9P_FS_POSIX_ACL is not set
# CONFIG_9P_FS_SECURITY is not set
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
CONFIG_ARCH_HAS_KCOV=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_SP805_WATCHDOG is not set
CONFIG_BALLOON_COMPACTION=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
CONFIG_CPU_RMAP=y
CONFIG_CRC16=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DTC=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EXT4_FS=y
CONFIG_F2FS_FS=y
CONFIG_FAILOVER=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_PL061=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARM_SMCCC=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_GENERIC_GUP=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_RCU_TABLE_FREE=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_UID16=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HVC_DRIVER=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IOMMU_HELPER=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_MEMORY_BALLOON=y
CONFIG_MEMFD_CREATE=y
CONFIG_MIGRATION=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NET_9P=y
# CONFIG_NET_9P_DEBUG is not set
CONFIG_NET_9P_VIRTIO=y
CONFIG_NET_FAILOVER=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NO_BOOTMEM=y
CONFIG_NVMEM=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_NET=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_PADATA=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_RATIONAL=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_REFCOUNT_FULL=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PL031=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
# CONFIG_SCHED_INFO is not set
CONFIG_SCSI=y
CONFIG_SCSI_VIRTIO=y
CONFIG_SERIAL_8250_FSL=y
# CONFIG_SERIAL_AMBA_PL010 is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SPARSE_IRQ=y
CONFIG_SRCU=y
CONFIG_SWIOTLB=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_USB_SUPPORT=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_BLK=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_VIRTIO_MMIO=y
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_XPS=y

View File

@ -1,239 +0,0 @@
CONFIG_AG71XX=y
# CONFIG_AG71XX_DEBUG is not set
CONFIG_AG71XX_DEBUG_FS=y
CONFIG_AR8216_PHY=y
CONFIG_AR8216_PHY_LEDS=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_AT803X_PHY=y
CONFIG_ATH79=y
CONFIG_ATH79_WDT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_CEVT_R4K=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_BOSTON is not set
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_RIXI=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_CPU_MIPSR2=y
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
CONFIG_CPU_R4K_CACHE_TLB=y
CONFIG_CPU_R4K_FPU=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_CPU_SUPPORTS_MSA=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CSRC_R4K=y
CONFIG_DMA_DIRECT_OPS=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_NONCOHERENT_OPS=y
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
CONFIG_ETHERNET_PACKET_MANGLE=y
CONFIG_FIXED_PHY=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_LIB_ASHLDI3=y
CONFIG_GENERIC_LIB_ASHRDI3=y
CONFIG_GENERIC_LIB_CMPDI2=y
CONFIG_GENERIC_LIB_LSHRDI3=y
CONFIG_GENERIC_LIB_UCMPDI2=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_74X164=y
CONFIG_GPIO_ATH79=y
CONFIG_GPIO_GENERIC=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_CBPF_JIT=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_COPY_THREAD_TLS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HW_HAS_PCI=y
CONFIG_HZ_PERIODIC=y
CONFIG_IMAGE_CMDLINE_HACK=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MIPS_CPU=y
CONFIG_IRQ_WORK=y
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_RESET is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_GPIO=y
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_RB4XX_CPLD is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MIPS=y
CONFIG_MIPS_ASID_BITS=8
CONFIG_MIPS_ASID_SHIFT=0
CONFIG_MIPS_CBPF_JIT=y
CONFIG_MIPS_CLOCK_VSYSCALL=y
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_MIPS_CMDLINE_FROM_DTB=y
# CONFIG_MIPS_ELF_APPENDED_DTB is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_NO_APPENDED_DTB is not set
CONFIG_MIPS_RAW_APPENDED_DTB=y
CONFIG_MIPS_SPRAM=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_CFI_I2 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_M25P80=y
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
CONFIG_MTD_PARSER_CYBERTAN=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_ELF_FW=y
CONFIG_MTD_SPLIT_LZMA_FW=y
CONFIG_MTD_SPLIT_SEAMA_FW=y
CONFIG_MTD_SPLIT_TPLINK_FW=y
CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_MTD_SPLIT_WRGG_FW=y
CONFIG_MTD_VIRT_CONCAT=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_NVMEM=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_PCI=y
CONFIG_PCI_AR71XX=y
CONFIG_PCI_AR724X=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
# CONFIG_PHY_AR7100_USB is not set
# CONFIG_PHY_AR7200_USB is not set
# CONFIG_PHY_ATH79_USB is not set
CONFIG_PINCTRL=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_RESET_ATH79=y
CONFIG_RESET_CONTROLLER=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_AR933X=y
CONFIG_SERIAL_AR933X_CONSOLE=y
CONFIG_SERIAL_AR933X_NR_UARTS=2
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_AR934X=y
CONFIG_SPI_ATH79=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_RB4XX is not set
CONFIG_SRCU=y
CONFIG_SWCONFIG=y
CONFIG_SWCONFIG_LEDS=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_SYS_SUPPORTS_ZBOOT=y
CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TINY_SRCU=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y

View File

@ -631,19 +631,11 @@ static void ar934x_nfc_read_status(struct ar934x_nfc *nfc)
nfc->buf[0] = status;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static void ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command,
int column, int page_addr)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
struct nand_chip *nand = &nfc->nand_chip;
#else
static void ar934x_nfc_cmdfunc(struct nand_chip *nand, unsigned int command,
int column, int page_addr)
{
struct mtd_info *mtd = nand_to_mtd(nand);
struct ar934x_nfc *nfc = nand->priv;
#endif
nfc->read_id = false;
if (command != NAND_CMD_PAGEPROG)
@ -748,28 +740,16 @@ static void ar934x_nfc_cmdfunc(struct nand_chip *nand, unsigned int command,
}
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_dev_ready(struct mtd_info *mtd)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_dev_ready(struct nand_chip *chip)
{
struct ar934x_nfc *nfc = chip->priv;
#endif
return __ar934x_nfc_dev_ready(nfc);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static u8 ar934x_nfc_read_byte(struct mtd_info *mtd)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static u8 ar934x_nfc_read_byte(struct nand_chip *chip)
{
struct ar934x_nfc *nfc = chip->priv;
#endif
u8 data;
WARN_ON(nfc->buf_index >= nfc->buf_size);
@ -784,15 +764,9 @@ static u8 ar934x_nfc_read_byte(struct nand_chip *chip)
return data;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static void ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static void ar934x_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
{
struct ar934x_nfc *nfc = chip->priv;
#endif
int i;
WARN_ON(nfc->buf_index + len > nfc->buf_size);
@ -810,15 +784,9 @@ static void ar934x_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
}
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static void ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static void ar934x_nfc_read_buf(struct nand_chip *chip, u8 *buf, int len)
{
struct ar934x_nfc *nfc = chip->priv;
#endif
int buf_index;
int i;
@ -853,18 +821,11 @@ static inline void ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc)
nfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_read_oob(struct nand_chip *chip,
int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
int err;
nfc_dbg(nfc, "read_oob: page:%d\n", page);
@ -879,18 +840,11 @@ static int ar934x_nfc_read_oob(struct nand_chip *chip,
return 0;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_write_oob(struct nand_chip *chip,
int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
nfc_dbg(nfc, "write_oob: page:%d\n", page);
memcpy(nfc->buf, chip->oob_poi, mtd->oobsize);
@ -899,20 +853,12 @@ static int ar934x_nfc_write_oob(struct nand_chip *chip,
page, mtd->oobsize);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_read_page_raw(struct mtd_info *mtd,
struct nand_chip *chip, u8 *buf,
int oob_required, int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_read_page_raw(
struct nand_chip *chip, u8 *buf,
int oob_required, int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
int len;
int err;
@ -934,18 +880,11 @@ static int ar934x_nfc_read_page_raw(
return 0;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
u8 *buf, int oob_required, int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_read_page(struct nand_chip *chip,
u8 *buf, int oob_required, int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
u32 ecc_ctrl;
int max_bitflips = 0;
bool ecc_failed;
@ -1014,20 +953,12 @@ static int ar934x_nfc_read_page(struct nand_chip *chip,
return max_bitflips;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_write_page_raw(struct mtd_info *mtd,
struct nand_chip *chip, const u8 *buf,
int oob_required, int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_write_page_raw(
struct nand_chip *chip, const u8 *buf,
int oob_required, int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
int len;
nfc_dbg(nfc, "write_page_raw: page:%d oob:%d\n", page, oob_required);
@ -1043,18 +974,11 @@ static int ar934x_nfc_write_page_raw(
return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
const u8 *buf, int oob_required, int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_write_page(struct nand_chip *chip,
const u8 *buf, int oob_required, int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
int err;
nfc_dbg(nfc, "write_page: page:%d oob:%d\n", page, oob_required);
@ -1062,11 +986,7 @@ static int ar934x_nfc_write_page(struct nand_chip *chip,
/* write OOB first */
if (oob_required &&
!is_all_ff(chip->oob_poi, mtd->oobsize)) {
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
err = ar934x_nfc_write_oob(mtd, chip, page);
#else
err = ar934x_nfc_write_oob(chip, page);
#endif
if (err)
return err;
}
@ -1176,11 +1096,7 @@ static int ar934x_nfc_init_tail(struct mtd_info *mtd)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
struct nand_chip *chip = &nfc->nand_chip;
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)
u64 chipsize = chip->chipsize;
#else
u64 chipsize = nanddev_target_size(&chip->base);
#endif
u32 ctrl;
u32 t;
int err;
@ -1427,13 +1343,8 @@ static int ar934x_nfc_attach_chip(struct nand_chip *nand)
static u64 ar934x_nfc_dma_mask = DMA_BIT_MASK(32);
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static void ar934x_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
unsigned int ctrl)
#else
static void ar934x_nfc_cmd_ctrl(struct nand_chip *chip, int dat,
unsigned int ctrl)
#endif
{
WARN_ON(dat != NAND_CMD_NONE);
}
@ -1504,15 +1415,6 @@ static int ar934x_nfc_probe(struct platform_device *pdev)
nand_set_controller_data(nand, nfc);
nand_set_flash_node(nand, pdev->dev.of_node);
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
nand->chip_delay = 25;
nand->dev_ready = ar934x_nfc_dev_ready;
nand->cmdfunc = ar934x_nfc_cmdfunc;
nand->cmd_ctrl = ar934x_nfc_cmd_ctrl; /* dummy */
nand->read_byte = ar934x_nfc_read_byte;
nand->write_buf = ar934x_nfc_write_buf;
nand->read_buf = ar934x_nfc_read_buf;
#else
nand->legacy.chip_delay = 25;
nand->legacy.dev_ready = ar934x_nfc_dev_ready;
nand->legacy.cmdfunc = ar934x_nfc_cmdfunc;
@ -1520,7 +1422,6 @@ static int ar934x_nfc_probe(struct platform_device *pdev)
nand->legacy.read_byte = ar934x_nfc_read_byte;
nand->legacy.write_buf = ar934x_nfc_write_buf;
nand->legacy.read_buf = ar934x_nfc_read_buf;
#endif
nand->ecc.mode = NAND_ECC_HW; /* default */
nand->priv = nfc;
platform_set_drvdata(pdev, nfc);
@ -1535,16 +1436,8 @@ static int ar934x_nfc_probe(struct platform_device *pdev)
goto err_free_buf;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 130)
nand->dummy_controller.ops = &ar934x_nfc_controller_ops;
ret = nand_scan(mtd, 1);
#elif LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
nand->dummy_controller.ops = &ar934x_nfc_controller_ops;
ret = nand_scan(nand, 1);
#else
nand->legacy.dummy_controller.ops = &ar934x_nfc_controller_ops;
ret = nand_scan(nand, 1);
#endif
if (ret) {
dev_err(&pdev->dev, "nand_scan failed, err:%d\n", ret);
goto err_free_buf;
@ -1566,9 +1459,6 @@ err_free_buf:
static int ar934x_nfc_remove(struct platform_device *pdev)
{
struct ar934x_nfc *nfc;
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
struct mtd_info *mtd;
#endif
nfc = platform_get_drvdata(pdev);
if (nfc) {

View File

@ -81,15 +81,9 @@ static const struct mtd_ooblayout_ops rb4xx_nand_ecclayout_ops = {
.free = rb4xx_ooblayout_free,
};
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,20,0)
static uint8_t rb4xx_nand_read_byte(struct mtd_info *mtd)
{
struct rb4xx_nand *nand = mtd->priv;
#else
static u8 rb4xx_nand_read_byte(struct nand_chip *chip)
{
struct rb4xx_nand *nand = chip->priv;
#endif
struct rb4xx_cpld *cpld = nand->cpld;
u8 data;
int ret;
@ -101,45 +95,26 @@ static u8 rb4xx_nand_read_byte(struct nand_chip *chip)
return data;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,20,0)
static void rb4xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
int len)
{
struct rb4xx_nand *nand = mtd->priv;
#else
static void rb4xx_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
{
struct rb4xx_nand *nand = chip->priv;
#endif
struct rb4xx_cpld *cpld = nand->cpld;
cpld->write_nand(cpld, buf, len);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,20,0)
static void rb4xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
struct rb4xx_nand *nand = mtd->priv;
#else
static void rb4xx_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
{
struct rb4xx_nand *nand = chip->priv;
#endif
struct rb4xx_cpld *cpld = nand->cpld;
cpld->read_nand(cpld, buf, len);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,20,0)
static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
{
struct rb4xx_nand *nand = mtd->priv;
#else
static void rb4xx_nand_cmd_ctrl(struct nand_chip *chip, int dat,
unsigned int ctrl)
{
struct rb4xx_nand *nand = chip->priv;
#endif
struct rb4xx_cpld *cpld = nand->cpld;
u8 data = dat;
@ -153,15 +128,9 @@ static void rb4xx_nand_cmd_ctrl(struct nand_chip *chip, int dat,
cpld->write_nand(cpld, &data, 1);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,20,0)
static int rb4xx_nand_dev_ready(struct mtd_info *mtd)
{
struct rb4xx_nand *nand = mtd->priv;
#else
static int rb4xx_nand_dev_ready(struct nand_chip *chip)
{
struct rb4xx_nand *nand = chip->priv;
#endif
return gpiod_get_value_cansleep(nand->rdy);
}
@ -224,20 +193,6 @@ static int rb4xx_nand_probe(struct platform_device *pdev)
nand->chip.options = NAND_NO_SUBPAGE_WRITE;
nand->chip.priv = nand;
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,20,0)
nand->chip.read_byte = rb4xx_nand_read_byte;
nand->chip.write_buf = rb4xx_nand_write_buf;
nand->chip.read_buf = rb4xx_nand_read_buf;
nand->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl;
nand->chip.dev_ready = rb4xx_nand_dev_ready;
nand->chip.chip_delay = 25;
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,19,130)
ret = nand_scan(mtd, 1);
#else
ret = nand_scan(&nand->chip, 1);
#endif
#else
nand->chip.legacy.read_byte = rb4xx_nand_read_byte;
nand->chip.legacy.write_buf = rb4xx_nand_write_buf;
nand->chip.legacy.read_buf = rb4xx_nand_read_buf;
@ -246,7 +201,6 @@ static int rb4xx_nand_probe(struct platform_device *pdev)
nand->chip.legacy.chip_delay = 25;
ret = nand_scan(&nand->chip, 1);
#endif
if (ret)
return -ENXIO;

View File

@ -1,8 +1,8 @@
define Device/mikrotik
DEVICE_VENDOR := MikroTik
LOADER_TYPE := elf
KERNEL := kernel-bin | append-dtb | lzma | loader-kernel
KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-kernel
KERNEL_NAME := vmlinuz
KERNEL := kernel-bin | append-dtb-elf
KERNEL_INITRAMFS := kernel-bin | append-dtb-elf
endef
define Device/mikrotik_nor

View File

@ -1,5 +1,7 @@
BOARDNAME := MikroTik devices
FEATURES += minor nand squashfs
KERNELNAME := vmlinux vmlinuz
IMAGES_DIR := ../../..
DEFAULT_PACKAGES += wpad-basic-wolfssl

View File

@ -1,32 +0,0 @@
From 5f5c9858af167f842ee8df053920b98387a71af1 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Mon, 5 Mar 2018 11:41:25 +0100
Subject: [PATCH 02/27] watchdog: ath79: fix maximum timeout
If the userland tries to set a timeout higher than the max_timeout,
then we should fallback to max_timeout.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/watchdog/ath79_wdt.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
--- a/drivers/watchdog/ath79_wdt.c
+++ b/drivers/watchdog/ath79_wdt.c
@@ -115,10 +115,14 @@ static inline void ath79_wdt_disable(voi
static int ath79_wdt_set_timeout(int val)
{
- if (val < 1 || val > max_timeout)
+ if (val < 1)
return -EINVAL;
- timeout = val;
+ if (val > max_timeout)
+ timeout = max_timeout;
+ else
+ timeout = val;
+
ath79_wdt_keepalive();
return 0;

View File

@ -1,186 +0,0 @@
From ecbd9c87f073f097d9fe56390353e64e963e866a Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Tue, 6 Mar 2018 10:03:03 +0100
Subject: [PATCH 03/27] leds: add reset-controller based driver
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/leds/Kconfig | 11 ++++
drivers/leds/Makefile | 1 +
drivers/leds/leds-reset.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 149 insertions(+)
create mode 100644 drivers/leds/leds-reset.c
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -756,6 +756,17 @@ config LEDS_NIC78BX
To compile this driver as a module, choose M here: the module
will be called leds-nic78bx.
+config LEDS_RESET
+ tristate "LED support for reset-controller API"
+ depends on LEDS_CLASS
+ depends on RESET_CONTROLLER
+ help
+ This option enables support for LEDs connected to pins driven by reset
+ controllers. Yes, DNI actual built HW like that.
+
+ To compile this driver as a module, choose M here: the module
+ will be called leds-reset.
+
comment "LED Triggers"
source "drivers/leds/trigger/Kconfig"
--- /dev/null
+++ b/drivers/leds/leds-reset.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2018 John Crispin <john@phrozen.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/err.h>
+#include <linux/reset.h>
+#include <linux/kernel.h>
+#include <linux/leds.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+struct reset_led_data {
+ struct led_classdev cdev;
+ struct reset_control *rst;
+};
+
+static inline struct reset_led_data *
+ cdev_to_reset_led_data(struct led_classdev *led_cdev)
+{
+ return container_of(led_cdev, struct reset_led_data, cdev);
+}
+
+static void reset_led_set(struct led_classdev *led_cdev,
+ enum led_brightness value)
+{
+ struct reset_led_data *led_dat = cdev_to_reset_led_data(led_cdev);
+
+ if (value == LED_OFF)
+ reset_control_assert(led_dat->rst);
+ else
+ reset_control_deassert(led_dat->rst);
+}
+
+struct reset_leds_priv {
+ int num_leds;
+ struct reset_led_data leds[];
+};
+
+static inline int sizeof_reset_leds_priv(int num_leds)
+{
+ return sizeof(struct reset_leds_priv) +
+ (sizeof(struct reset_led_data) * num_leds);
+}
+
+static struct reset_leds_priv *reset_leds_create(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct fwnode_handle *child;
+ struct reset_leds_priv *priv;
+ int count, ret;
+
+ count = device_get_child_node_count(dev);
+ if (!count)
+ return ERR_PTR(-ENODEV);
+
+ priv = devm_kzalloc(dev, sizeof_reset_leds_priv(count), GFP_KERNEL);
+ if (!priv)
+ return ERR_PTR(-ENOMEM);
+
+ device_for_each_child_node(dev, child) {
+ struct reset_led_data *led = &priv->leds[priv->num_leds];
+ struct device_node *np = to_of_node(child);
+
+ ret = fwnode_property_read_string(child, "label", &led->cdev.name);
+ if (!led->cdev.name) {
+ fwnode_handle_put(child);
+ return ERR_PTR(-EINVAL);
+ }
+ led->rst = __of_reset_control_get(np, NULL, 0, 0, 0);
+ if (IS_ERR(led->rst))
+ return ERR_PTR(-EINVAL);
+
+ fwnode_property_read_string(child, "linux,default-trigger",
+ &led->cdev.default_trigger);
+
+ led->cdev.brightness_set = reset_led_set;
+ ret = devm_of_led_classdev_register(&pdev->dev, np, &led->cdev);
+ if (ret < 0)
+ return ERR_PTR(ret);
+ led->cdev.dev->of_node = np;
+ priv->num_leds++;
+ }
+
+ return priv;
+}
+
+static const struct of_device_id of_reset_leds_match[] = {
+ { .compatible = "reset-leds", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, of_reset_leds_match);
+
+static int reset_led_probe(struct platform_device *pdev)
+{
+ struct reset_leds_priv *priv;
+
+ priv = reset_leds_create(pdev);
+ if (IS_ERR(priv))
+ return PTR_ERR(priv);
+
+ platform_set_drvdata(pdev, priv);
+
+ return 0;
+}
+
+static void reset_led_shutdown(struct platform_device *pdev)
+{
+ struct reset_leds_priv *priv = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < priv->num_leds; i++) {
+ struct reset_led_data *led = &priv->leds[i];
+
+ if (!(led->cdev.flags & LED_RETAIN_AT_SHUTDOWN))
+ reset_led_set(&led->cdev, LED_OFF);
+ }
+}
+
+static struct platform_driver reset_led_driver = {
+ .probe = reset_led_probe,
+ .shutdown = reset_led_shutdown,
+ .driver = {
+ .name = "leds-reset",
+ .of_match_table = of_reset_leds_match,
+ },
+};
+
+module_platform_driver(reset_led_driver);
+
+MODULE_AUTHOR("John Crispin <john@phrozen.org>");
+MODULE_DESCRIPTION("reset controller LED driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:leds-reset");
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -78,6 +78,7 @@ obj-$(CONFIG_LEDS_MT6323) += leds-mt632
obj-$(CONFIG_LEDS_LM3692X) += leds-lm3692x.o
obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o
obj-$(CONFIG_LEDS_LM3601X) += leds-lm3601x.o
+obj-$(CONFIG_LEDS_RESET) += leds-reset.o
# LED SPI Drivers
obj-$(CONFIG_LEDS_CR0014114) += leds-cr0014114.o

View File

@ -1,333 +0,0 @@
From 08c9d6ceef01893678a5d2e8a15517c745417f21 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Tue, 6 Mar 2018 10:04:05 +0100
Subject: [PATCH 04/27] phy: add ath79 usb phys
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/phy/Kconfig | 16 ++++++
drivers/phy/Makefile | 2 +
drivers/phy/phy-ar7100-usb.c | 124 +++++++++++++++++++++++++++++++++++++++++++
drivers/phy/phy-ar7200-usb.c | 108 +++++++++++++++++++++++++++++++++++++
4 files changed, 250 insertions(+)
create mode 100644 drivers/phy/phy-ar7100-usb.c
create mode 100644 drivers/phy/phy-ar7200-usb.c
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -15,6 +15,22 @@ config GENERIC_PHY
phy users can obtain reference to the PHY. All the users of this
framework should select this config.
+config PHY_AR7100_USB
+ tristate "Atheros AR7100 USB PHY driver"
+ depends on ATH79 || COMPILE_TEST
+ default y if USB_EHCI_HCD_PLATFORM
+ select PHY_SIMPLE
+ help
+ Enable this to support the USB PHY on Atheros AR7100 SoCs.
+
+config PHY_AR7200_USB
+ tristate "Atheros AR7200 USB PHY driver"
+ depends on ATH79 || COMPILE_TEST
+ default y if USB_EHCI_HCD_PLATFORM
+ select PHY_SIMPLE
+ help
+ Enable this to support the USB PHY on Atheros AR7200 SoCs.
+
config PHY_LPC18XX_USB_OTG
tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver"
depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -4,6 +4,8 @@
#
obj-$(CONFIG_GENERIC_PHY) += phy-core.o
+obj-$(CONFIG_PHY_AR7100_USB) += phy-ar7100-usb.o
+obj-$(CONFIG_PHY_AR7200_USB) += phy-ar7200-usb.o
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
--- /dev/null
+++ b/drivers/phy/phy-ar7100-usb.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2018 John Crispin <john@phrozen.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/delay.h>
+#include <linux/reset.h>
+#include <linux/of_gpio.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+struct ar7100_usb_phy {
+ struct reset_control *rst_phy;
+ struct reset_control *rst_host;
+ struct reset_control *rst_ohci_dll;
+ void __iomem *io_base;
+ struct phy *phy;
+ int gpio;
+};
+
+static int ar7100_usb_phy_power_off(struct phy *phy)
+{
+ struct ar7100_usb_phy *priv = phy_get_drvdata(phy);
+ int err = 0;
+
+ err |= reset_control_assert(priv->rst_host);
+ err |= reset_control_assert(priv->rst_phy);
+ err |= reset_control_assert(priv->rst_ohci_dll);
+
+ return err;
+}
+
+static int ar7100_usb_phy_power_on(struct phy *phy)
+{
+ struct ar7100_usb_phy *priv = phy_get_drvdata(phy);
+ int err = 0;
+
+ err |= ar7100_usb_phy_power_off(phy);
+ mdelay(100);
+ err |= reset_control_deassert(priv->rst_ohci_dll);
+ err |= reset_control_deassert(priv->rst_phy);
+ err |= reset_control_deassert(priv->rst_host);
+ mdelay(500);
+ iowrite32(0xf0000, priv->io_base + AR71XX_USB_CTRL_REG_CONFIG);
+ iowrite32(0x20c00, priv->io_base + AR71XX_USB_CTRL_REG_FLADJ);
+
+ return err;
+}
+
+static const struct phy_ops ar7100_usb_phy_ops = {
+ .power_on = ar7100_usb_phy_power_on,
+ .power_off = ar7100_usb_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int ar7100_usb_phy_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy_provider;
+ struct resource *res;
+ struct ar7100_usb_phy *priv;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->io_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(priv->io_base))
+ return PTR_ERR(priv->io_base);
+
+ priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy");
+ if (IS_ERR(priv->rst_phy)) {
+ dev_err(&pdev->dev, "phy reset is missing\n");
+ return PTR_ERR(priv->rst_phy);
+ }
+
+ priv->rst_host = devm_reset_control_get(&pdev->dev, "usb-host");
+ if (IS_ERR(priv->rst_host)) {
+ dev_err(&pdev->dev, "host reset is missing\n");
+ return PTR_ERR(priv->rst_host);
+ }
+
+ priv->rst_ohci_dll = devm_reset_control_get(&pdev->dev, "usb-ohci-dll");
+ if (IS_ERR(priv->rst_ohci_dll)) {
+ dev_err(&pdev->dev, "ohci-dll reset is missing\n");
+ return PTR_ERR(priv->rst_host);
+ }
+
+ priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7100_usb_phy_ops);
+ if (IS_ERR(priv->phy)) {
+ dev_err(&pdev->dev, "failed to create PHY\n");
+ return PTR_ERR(priv->phy);
+ }
+
+ priv->gpio = of_get_gpio(pdev->dev.of_node, 0);
+ if (priv->gpio >= 0) {
+ int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));
+
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request gpio\n");
+ return ret;
+ }
+ gpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev));
+ gpio_set_value(priv->gpio, 1);
+ }
+
+ phy_set_drvdata(priv->phy, priv);
+
+ phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
+
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id ar7100_usb_phy_of_match[] = {
+ { .compatible = "qca,ar7100-usb-phy" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, ar7100_usb_phy_of_match);
+
+static struct platform_driver ar7100_usb_phy_driver = {
+ .probe = ar7100_usb_phy_probe,
+ .driver = {
+ .of_match_table = ar7100_usb_phy_of_match,
+ .name = "ar7100-usb-phy",
+ }
+};
+module_platform_driver(ar7100_usb_phy_driver);
+
+MODULE_DESCRIPTION("ATH79 USB PHY driver");
+MODULE_AUTHOR("Alban Bedel <albeu@free.fr>");
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/phy/phy-ar7200-usb.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2015 Alban Bedel <albeu@free.fr>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/reset.h>
+#include <linux/of_gpio.h>
+
+struct ar7200_usb_phy {
+ struct reset_control *rst_phy;
+ struct reset_control *rst_phy_analog;
+ struct reset_control *suspend_override;
+ struct phy *phy;
+ int gpio;
+};
+
+static int ar7200_usb_phy_power_on(struct phy *phy)
+{
+ struct ar7200_usb_phy *priv = phy_get_drvdata(phy);
+ int err = 0;
+
+ if (priv->suspend_override)
+ err = reset_control_assert(priv->suspend_override);
+ if (priv->rst_phy)
+ err |= reset_control_deassert(priv->rst_phy);
+ if (priv->rst_phy_analog)
+ err |= reset_control_deassert(priv->rst_phy_analog);
+
+ return err;
+}
+
+static int ar7200_usb_phy_power_off(struct phy *phy)
+{
+ struct ar7200_usb_phy *priv = phy_get_drvdata(phy);
+ int err = 0;
+
+ if (priv->suspend_override)
+ err = reset_control_deassert(priv->suspend_override);
+ if (priv->rst_phy)
+ err |= reset_control_assert(priv->rst_phy);
+ if (priv->rst_phy_analog)
+ err |= reset_control_assert(priv->rst_phy_analog);
+
+ return err;
+}
+
+static const struct phy_ops ar7200_usb_phy_ops = {
+ .power_on = ar7200_usb_phy_power_on,
+ .power_off = ar7200_usb_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int ar7200_usb_phy_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy_provider;
+ struct ar7200_usb_phy *priv;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy");
+ if (IS_ERR(priv->rst_phy)) {
+ if (PTR_ERR(priv->rst_phy) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "phy reset is missing\n");
+ return PTR_ERR(priv->rst_phy);
+ }
+
+ priv->rst_phy_analog = devm_reset_control_get_optional(
+ &pdev->dev, "usb-phy-analog");
+ if (IS_ERR(priv->rst_phy_analog)) {
+ if (PTR_ERR(priv->rst_phy_analog) == -ENOENT)
+ priv->rst_phy_analog = NULL;
+ else
+ return PTR_ERR(priv->rst_phy_analog);
+ }
+
+ priv->suspend_override = devm_reset_control_get_optional(
+ &pdev->dev, "usb-suspend-override");
+ if (IS_ERR(priv->suspend_override)) {
+ if (PTR_ERR(priv->suspend_override) == -ENOENT)
+ priv->suspend_override = NULL;
+ else
+ return PTR_ERR(priv->suspend_override);
+ }
+
+ priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7200_usb_phy_ops);
+ if (IS_ERR(priv->phy)) {
+ dev_err(&pdev->dev, "failed to create PHY\n");
+ return PTR_ERR(priv->phy);
+ }
+
+ priv->gpio = of_get_gpio(pdev->dev.of_node, 0);
+ if (priv->gpio >= 0) {
+ int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));
+
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request gpio\n");
+ return ret;
+ }
+ gpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev));
+ gpio_set_value(priv->gpio, 1);
+ }
+
+ phy_set_drvdata(priv->phy, priv);
+
+ phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id ar7200_usb_phy_of_match[] = {
+ { .compatible = "qca,ar7200-usb-phy" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, ar7200_usb_phy_of_match);
+
+static struct platform_driver ar7200_usb_phy_driver = {
+ .probe = ar7200_usb_phy_probe,
+ .driver = {
+ .of_match_table = ar7200_usb_phy_of_match,
+ .name = "ar7200-usb-phy",
+ }
+};
+module_platform_driver(ar7200_usb_phy_driver);
+
+MODULE_DESCRIPTION("ATH79 USB PHY driver");
+MODULE_AUTHOR("Alban Bedel <albeu@free.fr>");
+MODULE_LICENSE("GPL");

View File

@ -1,24 +0,0 @@
From 2201818e5bd33f389beceb3943fdfcf5a698fc5b Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Tue, 6 Mar 2018 10:01:43 +0100
Subject: [PATCH 05/27] usb: add more OF/quirk properties
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/usb/host/ehci-platform.c | 5 +++++
1 file changed, 5 insertions(+)
--- a/drivers/usb/host/ehci-platform.c
+++ b/drivers/usb/host/ehci-platform.c
@@ -271,6 +271,11 @@ static int ehci_platform_probe(struct pl
ehci = hcd_to_ehci(hcd);
if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
+ of_property_read_u32(dev->dev.of_node, "caps-offset", &pdata->caps_offset);
+
+ if (of_property_read_bool(dev->dev.of_node, "has-synopsys-hc-bug"))
+ pdata->has_synopsys_hc_bug = 1;
+
if (of_property_read_bool(dev->dev.of_node, "big-endian-regs"))
ehci->big_endian_mmio = 1;

View File

@ -1,168 +0,0 @@
From f3eacff2310a60348a755c50a8da6fc251fc8587 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Tue, 6 Mar 2018 09:55:13 +0100
Subject: [PATCH 07/33] irqchip/irq-ath79-intc: add irq cascade driver for
QCA9556 SoCs
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ath79-intc.c | 142 +++++++++++++++++++++++++++++++++++++++
2 files changed, 143 insertions(+)
create mode 100644 drivers/irqchip/irq-ath79-intc.c
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
+obj-$(CONFIG_ATH79) += irq-ath79-intc.o
obj-$(CONFIG_ATH79) += irq-ath79-misc.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
--- /dev/null
+++ b/drivers/irqchip/irq-ath79-intc.c
@@ -0,0 +1,142 @@
+/*
+ * Atheros AR71xx/AR724x/AR913x specific interrupt handling
+ *
+ * Copyright (C) 2018 John Crispin <john@phrozen.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irqchip.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#define ATH79_MAX_INTC_CASCADE 3
+
+struct ath79_intc {
+ struct irq_chip chip;
+ u32 irq;
+ u32 pending_mask;
+ u32 int_status;
+ u32 irq_mask[ATH79_MAX_INTC_CASCADE];
+ u32 irq_wb_chan[ATH79_MAX_INTC_CASCADE];
+};
+
+static void ath79_intc_irq_handler(struct irq_desc *desc)
+{
+ struct irq_domain *domain = irq_desc_get_handler_data(desc);
+ struct ath79_intc *intc = domain->host_data;
+ u32 pending;
+
+ pending = ath79_reset_rr(intc->int_status);
+ pending &= intc->pending_mask;
+
+ if (pending) {
+ int i;
+
+ for (i = 0; i < domain->hwirq_max; i++)
+ if (pending & intc->irq_mask[i]) {
+ if (intc->irq_wb_chan[i] != 0xffffffff)
+ ath79_ddr_wb_flush(intc->irq_wb_chan[i]);
+ generic_handle_irq(irq_find_mapping(domain, i));
+ }
+ } else {
+ spurious_interrupt();
+ }
+}
+
+static void ath79_intc_irq_enable(struct irq_data *d)
+{
+ struct ath79_intc *intc = d->domain->host_data;
+ enable_irq(intc->irq);
+}
+
+static void ath79_intc_irq_disable(struct irq_data *d)
+{
+ struct ath79_intc *intc = d->domain->host_data;
+ disable_irq(intc->irq);
+}
+
+static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+ struct ath79_intc *intc = d->host_data;
+
+ irq_set_chip_and_handler(irq, &intc->chip, handle_level_irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops ath79_irq_domain_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = ath79_intc_map,
+};
+
+static int __init ath79_intc_of_init(
+ struct device_node *node, struct device_node *parent)
+{
+ struct irq_domain *domain;
+ struct ath79_intc *intc;
+ int cnt, cntwb, i, err;
+
+ cnt = of_property_count_u32_elems(node, "qca,pending-bits");
+ if (cnt > ATH79_MAX_INTC_CASCADE)
+ panic("Too many INTC pending bits\n");
+
+ intc = kzalloc(sizeof(*intc), GFP_KERNEL);
+ if (!intc)
+ panic("Failed to allocate INTC memory\n");
+ intc->chip = dummy_irq_chip;
+ intc->chip.name = "INTC";
+ intc->chip.irq_disable = ath79_intc_irq_disable;
+ intc->chip.irq_enable = ath79_intc_irq_enable;
+
+ if (of_property_read_u32(node, "qca,int-status-addr", &intc->int_status) < 0) {
+ panic("Missing address of interrupt status register\n");
+ }
+
+ of_property_read_u32_array(node, "qca,pending-bits", intc->irq_mask, cnt);
+ for (i = 0; i < cnt; i++) {
+ intc->pending_mask |= intc->irq_mask[i];
+ intc->irq_wb_chan[i] = 0xffffffff;
+ }
+
+ cntwb = of_count_phandle_with_args(
+ node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
+
+ for (i = 0; i < cntwb; i++) {
+ struct of_phandle_args args;
+ u32 irq = i;
+
+ of_property_read_u32_index(
+ node, "qca,ddr-wb-channel-interrupts", i, &irq);
+ if (irq >= ATH79_MAX_INTC_CASCADE)
+ continue;
+
+ err = of_parse_phandle_with_args(
+ node, "qca,ddr-wb-channels",
+ "#qca,ddr-wb-channel-cells",
+ i, &args);
+ if (err)
+ return err;
+
+ intc->irq_wb_chan[irq] = args.args[0];
+ }
+
+ intc->irq = irq_of_parse_and_map(node, 0);
+ if (!intc->irq)
+ panic("Failed to get INTC IRQ");
+
+ domain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc);
+ irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain);
+
+ return 0;
+}
+IRQCHIP_DECLARE(ath79_intc, "qca,ar9340-intc",
+ ath79_intc_of_init);

View File

@ -1,23 +0,0 @@
From e029f998594f151008ecbfa024e2957edd2a5189 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Tue, 6 Mar 2018 09:58:19 +0100
Subject: [PATCH 08/33] irqchip/irq-ath79-cpu: drop !OF init helper
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/irqchip/irq-ath79-cpu.c | 7 -------
1 file changed, 7 deletions(-)
--- a/drivers/irqchip/irq-ath79-cpu.c
+++ b/drivers/irqchip/irq-ath79-cpu.c
@@ -88,10 +88,3 @@ static int __init ar79_cpu_intc_of_init(
}
IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
ar79_cpu_intc_of_init);
-
-void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3)
-{
- irq_wb_chan[2] = irq_wb_chan2;
- irq_wb_chan[3] = irq_wb_chan3;
- mips_cpu_irq_init();
-}

View File

@ -1,24 +0,0 @@
From 0c8856211d26f84277f7fcb0b9595e5c646bc464 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Tue, 6 Mar 2018 10:00:55 +0100
Subject: [PATCH 11/33] MIPS: ath79: select the PINCTRL subsystem
The pinmux on QCA SoCs is controlled by a single register. The
"pinctrl-single" driver can be used but requires the target
to select PINCTRL.
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -288,6 +288,7 @@ config BCM63XX
select SYS_HAS_EARLY_PRINTK
select SWAP_IO_SPACE
select GPIOLIB
+ select PINCTRL
select HAVE_CLK
select MIPS_L1_CACHE_SHIFT_4
select CLKDEV_LOOKUP

View File

@ -1,57 +0,0 @@
From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Mon, 25 Jun 2018 15:52:10 +0200
Subject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc
With the driver being converted from platform_data to pure OF, we need to
also add some docs.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: John Crispin <john@phrozen.org>
---
.../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
@@ -0,0 +1,38 @@
+* Qualcomm Atheros AR7100 PCI express root complex
+
+Required properties:
+- compatible: should contain "qcom,ar7100-pci" to identify the core.
+- reg: Should contain the register ranges as listed in the reg-names property.
+- reg-names: Definition: Must include the following entries
+ - "cfg_base" IO Memory
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- ranges: ranges for the PCI memory and I/O regions
+- interrupt-map-mask and interrupt-map: standard PCI
+ properties to define the mapping of the PCIe interface to interrupt
+ numbers.
+- #interrupt-cells: set to <1>
+- interrupt-controller: define to enable the builtin IRQ cascade.
+
+Optional properties:
+- interrupt-parent: phandle to the MIPS IRQ controller
+
+* Example for ar7100
+ pcie-controller@180c0000 {
+ compatible = "qca,ar7100-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0x0>;
+ reg = <0x17010000 0x100>;
+ reg-names = "cfg_base";
+ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000
+ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-map-mask = <0 0 0 1>;
+ interrupt-map = <0 0 0 0 &pcie0 0>;
+ };

View File

@ -1,202 +0,0 @@
From 1855ab6b1d27f5b38a648baf57ff6a534afec26d Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Sat, 23 Jun 2018 15:07:23 +0200
Subject: [PATCH 18/33] MIPS: pci-ar71xx: convert to OF
With the ath79 target getting converted to pure OF, we can drop all the
platform data code and add the missing OF bits to the driver. We also add
a irq domain for the PCI/e controllers cascade, thus making it usable from
dts files.
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/pci/pci-ar71xx.c | 82 +++++++++++++++++++++++-----------------------
1 file changed, 41 insertions(+), 41 deletions(-)
--- a/arch/mips/pci/pci-ar71xx.c
+++ b/arch/mips/pci/pci-ar71xx.c
@@ -18,8 +18,11 @@
#include <linux/pci.h>
#include <linux/pci_regs.h>
#include <linux/interrupt.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/init.h>
#include <linux/platform_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79.h>
@@ -49,12 +52,13 @@
#define AR71XX_PCI_IRQ_COUNT 5
struct ar71xx_pci_controller {
+ struct device_node *np;
void __iomem *cfg_base;
int irq;
- int irq_base;
struct pci_controller pci_ctrl;
struct resource io_res;
struct resource mem_res;
+ struct irq_domain *domain;
};
/* Byte lane enable bits */
@@ -228,29 +232,30 @@ static struct pci_ops ar71xx_pci_ops = {
static void ar71xx_pci_irq_handler(struct irq_desc *desc)
{
- struct ar71xx_pci_controller *apc;
void __iomem *base = ath79_reset_base;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
u32 pending;
- apc = irq_desc_get_handler_data(desc);
-
+ chained_irq_enter(chip, desc);
pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
if (pending & AR71XX_PCI_INT_DEV0)
- generic_handle_irq(apc->irq_base + 0);
+ generic_handle_irq(irq_linear_revmap(apc->domain, 1));
else if (pending & AR71XX_PCI_INT_DEV1)
- generic_handle_irq(apc->irq_base + 1);
+ generic_handle_irq(irq_linear_revmap(apc->domain, 2));
else if (pending & AR71XX_PCI_INT_DEV2)
- generic_handle_irq(apc->irq_base + 2);
+ generic_handle_irq(irq_linear_revmap(apc->domain, 3));
else if (pending & AR71XX_PCI_INT_CORE)
- generic_handle_irq(apc->irq_base + 4);
+ generic_handle_irq(irq_linear_revmap(apc->domain, 4));
else
spurious_interrupt();
+ chained_irq_exit(chip, desc);
}
static void ar71xx_pci_irq_unmask(struct irq_data *d)
@@ -261,7 +266,7 @@ static void ar71xx_pci_irq_unmask(struct
u32 t;
apc = irq_data_get_irq_chip_data(d);
- irq = d->irq - apc->irq_base;
+ irq = irq_linear_revmap(apc->domain, d->irq);
t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
@@ -278,7 +283,7 @@ static void ar71xx_pci_irq_mask(struct i
u32 t;
apc = irq_data_get_irq_chip_data(d);
- irq = d->irq - apc->irq_base;
+ irq = irq_linear_revmap(apc->domain, d->irq);
t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
@@ -294,24 +299,31 @@ static struct irq_chip ar71xx_pci_irq_ch
.irq_mask_ack = ar71xx_pci_irq_mask,
};
+static int ar71xx_pci_irq_map(struct irq_domain *d,
+ unsigned int irq, irq_hw_number_t hw)
+{
+ struct ar71xx_pci_controller *apc = d->host_data;
+
+ irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
+ irq_set_chip_data(irq, apc);
+
+ return 0;
+}
+
+static const struct irq_domain_ops ar71xx_pci_domain_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = ar71xx_pci_irq_map,
+};
+
static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
{
void __iomem *base = ath79_reset_base;
- int i;
__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
- BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
-
- apc->irq_base = ATH79_PCI_IRQ_BASE;
- for (i = apc->irq_base;
- i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
- irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
- handle_level_irq);
- irq_set_chip_data(i, apc);
- }
-
+ apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
+ &ar71xx_pci_domain_ops, apc);
irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
apc);
}
@@ -328,6 +340,11 @@ static void ar71xx_pci_reset(void)
mdelay(100);
}
+static const struct of_device_id ar71xx_pci_ids[] = {
+ { .compatible = "qca,ar7100-pci" },
+ {},
+};
+
static int ar71xx_pci_probe(struct platform_device *pdev)
{
struct ar71xx_pci_controller *apc;
@@ -348,26 +365,6 @@ static int ar71xx_pci_probe(struct platf
if (apc->irq < 0)
return -EINVAL;
- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
- if (!res)
- return -EINVAL;
-
- apc->io_res.parent = res;
- apc->io_res.name = "PCI IO space";
- apc->io_res.start = res->start;
- apc->io_res.end = res->end;
- apc->io_res.flags = IORESOURCE_IO;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
- if (!res)
- return -EINVAL;
-
- apc->mem_res.parent = res;
- apc->mem_res.name = "PCI memory space";
- apc->mem_res.start = res->start;
- apc->mem_res.end = res->end;
- apc->mem_res.flags = IORESOURCE_MEM;
-
ar71xx_pci_reset();
/* setup COMMAND register */
@@ -380,9 +377,11 @@ static int ar71xx_pci_probe(struct platf
ar71xx_pci_irq_init(apc);
+ apc->np = pdev->dev.of_node;
apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
apc->pci_ctrl.mem_resource = &apc->mem_res;
apc->pci_ctrl.io_resource = &apc->io_res;
+ pci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node);
register_pci_controller(&apc->pci_ctrl);
@@ -393,6 +392,7 @@ static struct platform_driver ar71xx_pci
.probe = ar71xx_pci_probe,
.driver = {
.name = "ar71xx-pci",
+ .of_match_table = of_match_ptr(ar71xx_pci_ids),
},
};

View File

@ -1,61 +0,0 @@
From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Mon, 25 Jun 2018 15:52:02 +0200
Subject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc
With the driver being converted from platform_data to pure OF, we need to
also add some docs.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: John Crispin <john@phrozen.org>
---
.../devicetree/bindings/pci/qcom,ar7240-pci.txt | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
@@ -0,0 +1,42 @@
+* Qualcomm Atheros AR724X PCI express root complex
+
+Required properties:
+- compatible: should contain "qcom,ar7240-pci" to identify the core.
+- reg: Should contain the register ranges as listed in the reg-names property.
+- reg-names: Definition: Must include the following entries
+ - "crp_base" Configuration registers
+ - "ctrl_base" Control registers
+ - "cfg_base" IO Memory
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- ranges: ranges for the PCI memory and I/O regions
+- interrupt-map-mask and interrupt-map: standard PCI
+ properties to define the mapping of the PCIe interface to interrupt
+ numbers.
+- #interrupt-cells: set to <1>
+- interrupt-parent: phandle to the MIPS IRQ controller
+
+Optional properties:
+- interrupt-controller: define to enable the builtin IRQ cascade.
+
+* Example for qca9557
+ pcie-controller@180c0000 {
+ compatible = "qcom,ar7240-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0x0>;
+ reg = <0x180c0000 0x1000>,
+ <0x180f0000 0x100>,
+ <0x14000000 0x1000>;
+ reg-names = "crp_base", "ctrl_base", "cfg_base";
+ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000
+ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
+ interrupt-parent = <&intc2>;
+ interrupts = <1>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-map-mask = <0 0 0 1>;
+ interrupt-map = <0 0 0 0 &pcie0 0>;
+ };

View File

@ -1,205 +0,0 @@
From a522ee0199d5d3ea114ca2e211f6ac398d3e8e0b Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Sat, 23 Jun 2018 15:07:37 +0200
Subject: [PATCH 20/33] MIPS: pci-ar724x: convert to OF
With the ath79 target getting converted to pure OF, we can drop all the
platform data code and add the missing OF bits to the driver. We also add
a irq domain for the PCI/e controllers cascade, thus making it usable from
dts files.
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/pci/pci-ar724x.c | 88 ++++++++++++++++++++++------------------------
1 file changed, 42 insertions(+), 46 deletions(-)
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -14,8 +14,11 @@
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
+#include <linux/irqchip/chained_irq.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
#define AR724X_PCI_REG_APP 0x00
#define AR724X_PCI_REG_RESET 0x18
@@ -45,17 +48,20 @@ struct ar724x_pci_controller {
void __iomem *crp_base;
int irq;
- int irq_base;
bool link_up;
bool bar0_is_cached;
u32 bar0_value;
+ struct device_node *np;
struct pci_controller pci_controller;
+ struct irq_domain *domain;
struct resource io_res;
struct resource mem_res;
};
+static struct irq_chip ar724x_pci_irq_chip;
+
static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
{
u32 reset;
@@ -231,35 +237,31 @@ static struct pci_ops ar724x_pci_ops = {
static void ar724x_pci_irq_handler(struct irq_desc *desc)
{
- struct ar724x_pci_controller *apc;
- void __iomem *base;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc);
u32 pending;
- apc = irq_desc_get_handler_data(desc);
- base = apc->ctrl_base;
-
- pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
- __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ chained_irq_enter(chip, desc);
+ pending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) &
+ __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK);
if (pending & AR724X_PCI_INT_DEV0)
- generic_handle_irq(apc->irq_base + 0);
-
+ generic_handle_irq(irq_linear_revmap(apc->domain, 1));
else
spurious_interrupt();
+ chained_irq_exit(chip, desc);
}
static void ar724x_pci_irq_unmask(struct irq_data *d)
{
struct ar724x_pci_controller *apc;
void __iomem *base;
- int offset;
u32 t;
apc = irq_data_get_irq_chip_data(d);
base = apc->ctrl_base;
- offset = apc->irq_base - d->irq;
- switch (offset) {
+ switch (irq_linear_revmap(apc->domain, d->irq)) {
case 0:
t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
__raw_writel(t | AR724X_PCI_INT_DEV0,
@@ -273,14 +275,12 @@ static void ar724x_pci_irq_mask(struct i
{
struct ar724x_pci_controller *apc;
void __iomem *base;
- int offset;
u32 t;
apc = irq_data_get_irq_chip_data(d);
base = apc->ctrl_base;
- offset = apc->irq_base - d->irq;
- switch (offset) {
+ switch (irq_linear_revmap(apc->domain, d->irq)) {
case 0:
t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
__raw_writel(t & ~AR724X_PCI_INT_DEV0,
@@ -305,26 +305,34 @@ static struct irq_chip ar724x_pci_irq_ch
.irq_mask_ack = ar724x_pci_irq_mask,
};
+static int ar724x_pci_irq_map(struct irq_domain *d,
+ unsigned int irq, irq_hw_number_t hw)
+{
+ struct ar724x_pci_controller *apc = d->host_data;
+
+ irq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq);
+ irq_set_chip_data(irq, apc);
+
+ return 0;
+}
+
+static const struct irq_domain_ops ar724x_pci_domain_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = ar724x_pci_irq_map,
+};
+
static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
int id)
{
void __iomem *base;
- int i;
base = apc->ctrl_base;
__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
- apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
-
- for (i = apc->irq_base;
- i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
- irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
- handle_level_irq);
- irq_set_chip_data(i, apc);
- }
-
+ apc->domain = irq_domain_add_linear(apc->np, 2,
+ &ar724x_pci_domain_ops, apc);
irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
apc);
}
@@ -394,29 +402,11 @@ static int ar724x_pci_probe(struct platf
if (apc->irq < 0)
return -EINVAL;
- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
- if (!res)
- return -EINVAL;
-
- apc->io_res.parent = res;
- apc->io_res.name = "PCI IO space";
- apc->io_res.start = res->start;
- apc->io_res.end = res->end;
- apc->io_res.flags = IORESOURCE_IO;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
- if (!res)
- return -EINVAL;
-
- apc->mem_res.parent = res;
- apc->mem_res.name = "PCI memory space";
- apc->mem_res.start = res->start;
- apc->mem_res.end = res->end;
- apc->mem_res.flags = IORESOURCE_MEM;
-
+ apc->np = pdev->dev.of_node;
apc->pci_controller.pci_ops = &ar724x_pci_ops;
apc->pci_controller.io_resource = &apc->io_res;
apc->pci_controller.mem_resource = &apc->mem_res;
+ pci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node);
/*
* Do the full PCIE Root Complex Initialization Sequence if the PCIe
@@ -438,10 +428,16 @@ static int ar724x_pci_probe(struct platf
return 0;
}
+static const struct of_device_id ar724x_pci_ids[] = {
+ { .compatible = "qcom,ar7240-pci" },
+ {},
+};
+
static struct platform_driver ar724x_pci_driver = {
.probe = ar724x_pci_probe,
.driver = {
.name = "ar724x-pci",
+ .of_match_table = of_match_ptr(ar724x_pci_ids),
},
};

View File

@ -1,243 +0,0 @@
From 288a8eb0d41f09fda242e05f8a7bd1f5b3489477 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:19:26 +0100
Subject: [PATCH 21/33] MIPS: ath79: add helpers for setting clocks and expose
the ref clock
Preparation for transitioning the legacy clock setup code over
to OF.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 128 ++++++++++++++++++----------------
include/dt-bindings/clock/ath79-clk.h | 3 +-
2 files changed, 68 insertions(+), 63 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -37,20 +37,46 @@ static struct clk_onecell_data clk_data
.clk_num = ARRAY_SIZE(clks),
};
-static struct clk *__init ath79_add_sys_clkdev(
- const char *id, unsigned long rate)
+static const char * const clk_names[ATH79_CLK_END] = {
+ [ATH79_CLK_CPU] = "cpu",
+ [ATH79_CLK_DDR] = "ddr",
+ [ATH79_CLK_AHB] = "ahb",
+ [ATH79_CLK_REF] = "ref",
+};
+
+static const char * __init ath79_clk_name(int type)
{
- struct clk *clk;
- int err;
+ BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
+ return clk_names[type];
+}
- clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
+static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
+{
if (IS_ERR(clk))
- panic("failed to allocate %s clock structure", id);
+ panic("failed to allocate %s clock structure", clk_names[type]);
- err = clk_register_clkdev(clk, id, NULL);
- if (err)
- panic("unable to register %s clock device", id);
+ clks[type] = clk;
+ clk_register_clkdev(clk, name, NULL);
+}
+static struct clk * __init ath79_set_clk(int type, unsigned long rate)
+{
+ const char *name = ath79_clk_name(type);
+ struct clk *clk;
+
+ clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
+ __ath79_set_clk(type, name, clk);
+ return clk;
+}
+
+static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
+ unsigned int mult, unsigned int div)
+{
+ const char *name = ath79_clk_name(type);
+ struct clk *clk;
+
+ clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
+ __ath79_set_clk(type, name, clk);
return clk;
}
@@ -80,27 +106,15 @@ static void __init ar71xx_clocks_init(vo
div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
ahb_rate = cpu_rate / div;
- ath79_add_sys_clkdev("ref", ref_rate);
- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ahb", NULL);
}
-static struct clk * __init ath79_reg_ffclk(const char *name,
- const char *parent_name, unsigned int mult, unsigned int div)
-{
- struct clk *clk;
-
- clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
- if (IS_ERR(clk))
- panic("failed to allocate %s clock structure", name);
-
- return clk;
-}
-
static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
{
u32 pll;
@@ -114,24 +128,19 @@ static void __init ar724x_clk_init(struc
ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
}
static void __init ar724x_clocks_init(void)
{
struct clk *ref_clk;
- ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
+ ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
ar724x_clk_init(ref_clk, ath79_pll_base);
- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
-
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ahb", NULL);
}
@@ -186,12 +195,12 @@ static void __init ar9330_clk_init(struc
AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
}
- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
- ninit_mul, ref_div * out_div * cpu_div);
- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
- ninit_mul, ref_div * out_div * ddr_div);
- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
- ninit_mul, ref_div * out_div * ahb_div);
+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
+ ref_div * out_div * cpu_div);
+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
+ ref_div * out_div * ddr_div);
+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
+ ref_div * out_div * ahb_div);
}
static void __init ar933x_clocks_init(void)
@@ -206,15 +215,10 @@ static void __init ar933x_clocks_init(vo
else
ref_rate = (25 * 1000 * 1000);
- ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
+ ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
ar9330_clk_init(ref_clk, ath79_pll_base);
- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
-
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
}
@@ -344,10 +348,10 @@ static void __init ar934x_clocks_init(vo
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_add_sys_clkdev("ref", ref_rate);
- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
@@ -431,10 +435,10 @@ static void __init qca953x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_add_sys_clkdev("ref", ref_rate);
- ath79_add_sys_clkdev("cpu", cpu_rate);
- ath79_add_sys_clkdev("ddr", ddr_rate);
- ath79_add_sys_clkdev("ahb", ahb_rate);
+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
@@ -516,10 +520,10 @@ static void __init qca955x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_add_sys_clkdev("ref", ref_rate);
- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
@@ -620,10 +624,10 @@ static void __init qca956x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_add_sys_clkdev("ref", ref_rate);
- ath79_add_sys_clkdev("cpu", cpu_rate);
- ath79_add_sys_clkdev("ddr", ddr_rate);
- ath79_add_sys_clkdev("ahb", ahb_rate);
+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
--- a/include/dt-bindings/clock/ath79-clk.h
+++ b/include/dt-bindings/clock/ath79-clk.h
@@ -13,7 +13,8 @@
#define ATH79_CLK_CPU 0
#define ATH79_CLK_DDR 1
#define ATH79_CLK_AHB 2
+#define ATH79_CLK_REF 3
-#define ATH79_CLK_END 3
+#define ATH79_CLK_END 4
#endif /* __DT_BINDINGS_ATH79_CLK_H */

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@ -1,114 +0,0 @@
From 339c191a95e978353c9ba3aafab0261e14de109b Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:22:43 +0100
Subject: [PATCH 22/33] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
out of soc init
Preparation for reusing functions for DT
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 38 +++++++++++++++++---------------------
1 file changed, 17 insertions(+), 21 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -110,9 +110,6 @@ static void __init ar71xx_clocks_init(vo
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ahb", NULL);
- clk_add_alias("uart", NULL, "ahb", NULL);
}
static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
@@ -140,9 +137,6 @@ static void __init ar724x_clocks_init(vo
ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
ar724x_clk_init(ref_clk, ath79_pll_base);
-
- clk_add_alias("wdt", NULL, "ahb", NULL);
- clk_add_alias("uart", NULL, "ahb", NULL);
}
static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
@@ -218,9 +212,6 @@ static void __init ar933x_clocks_init(vo
ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
ar9330_clk_init(ref_clk, ath79_pll_base);
-
- clk_add_alias("wdt", NULL, "ahb", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
}
static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
@@ -353,9 +344,6 @@ static void __init ar934x_clocks_init(vo
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
-
iounmap(dpll_base);
}
@@ -439,9 +427,6 @@ static void __init qca953x_clocks_init(v
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
}
static void __init qca955x_clocks_init(void)
@@ -524,9 +509,6 @@ static void __init qca955x_clocks_init(v
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
}
static void __init qca956x_clocks_init(void)
@@ -628,13 +610,13 @@ static void __init qca956x_clocks_init(v
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
}
void __init ath79_clocks_init(void)
{
+ const char *wdt;
+ const char *uart;
+
if (soc_is_ar71xx())
ar71xx_clocks_init();
else if (soc_is_ar724x() || soc_is_ar913x())
@@ -651,6 +633,20 @@ void __init ath79_clocks_init(void)
qca956x_clocks_init();
else
BUG();
+
+ if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
+ wdt = "ahb";
+ uart = "ahb";
+ } else if (soc_is_ar933x()) {
+ wdt = "ahb";
+ uart = "ref";
+ } else {
+ wdt = "ref";
+ uart = "ref";
+ }
+
+ clk_add_alias("wdt", NULL, wdt, NULL);
+ clk_add_alias("uart", NULL, uart, NULL);
}
unsigned long __init

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@ -1,242 +0,0 @@
From 6350b2c36c522fecbc91a80b63f49319dafd2a72 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:23:20 +0100
Subject: [PATCH 23/33] MIPS: ath79: pass PLL base to clock init functions
Preparation for passing the mapped base via DT
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 60 ++++++++++++++++++++++++-------------------------
1 file changed, 30 insertions(+), 30 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -80,7 +80,7 @@ static struct clk * __init ath79_set_ff_
return clk;
}
-static void __init ar71xx_clocks_init(void)
+static void __init ar71xx_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
unsigned long cpu_rate;
@@ -92,7 +92,7 @@ static void __init ar71xx_clocks_init(vo
ref_rate = AR71XX_BASE_FREQ;
- pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
+ pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
freq = div * ref_rate;
@@ -130,13 +130,13 @@ static void __init ar724x_clk_init(struc
ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
}
-static void __init ar724x_clocks_init(void)
+static void __init ar724x_clocks_init(void __iomem *pll_base)
{
struct clk *ref_clk;
ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
- ar724x_clk_init(ref_clk, ath79_pll_base);
+ ar724x_clk_init(ref_clk, pll_base);
}
static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
@@ -197,7 +197,7 @@ static void __init ar9330_clk_init(struc
ref_div * out_div * ahb_div);
}
-static void __init ar933x_clocks_init(void)
+static void __init ar933x_clocks_init(void __iomem *pll_base)
{
struct clk *ref_clk;
unsigned long ref_rate;
@@ -234,7 +234,7 @@ static u32 __init ar934x_get_pll_freq(u3
return ret;
}
-static void __init ar934x_clocks_init(void)
+static void __init ar934x_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
unsigned long cpu_rate;
@@ -265,7 +265,7 @@ static void __init ar934x_clocks_init(vo
AR934X_SRIF_DPLL1_REFDIV_MASK;
frac = 1 << 18;
} else {
- pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
+ pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
@@ -292,7 +292,7 @@ static void __init ar934x_clocks_init(vo
AR934X_SRIF_DPLL1_REFDIV_MASK;
frac = 1 << 18;
} else {
- pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
+ pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
@@ -307,7 +307,7 @@ static void __init ar934x_clocks_init(vo
ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
nfrac, frac, out_div);
- clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -347,7 +347,7 @@ static void __init ar934x_clocks_init(vo
iounmap(dpll_base);
}
-static void __init qca953x_clocks_init(void)
+static void __init qca953x_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
unsigned long cpu_rate;
@@ -363,7 +363,7 @@ static void __init qca953x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
- pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
@@ -377,7 +377,7 @@ static void __init qca953x_clocks_init(v
cpu_pll += frac * (ref_rate >> 6) / ref_div;
cpu_pll /= (1 << out_div);
- pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
@@ -391,7 +391,7 @@ static void __init qca953x_clocks_init(v
ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
ddr_pll /= (1 << out_div);
- clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
+ clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -429,7 +429,7 @@ static void __init qca953x_clocks_init(v
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
}
-static void __init qca955x_clocks_init(void)
+static void __init qca955x_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
unsigned long cpu_rate;
@@ -445,7 +445,7 @@ static void __init qca955x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
- pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
@@ -459,7 +459,7 @@ static void __init qca955x_clocks_init(v
cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
cpu_pll /= (1 << out_div);
- pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
@@ -473,7 +473,7 @@ static void __init qca955x_clocks_init(v
ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
ddr_pll /= (1 << out_div);
- clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
+ clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -511,7 +511,7 @@ static void __init qca955x_clocks_init(v
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
}
-static void __init qca956x_clocks_init(void)
+static void __init qca956x_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
unsigned long cpu_rate;
@@ -537,13 +537,13 @@ static void __init qca956x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
@@ -556,12 +556,12 @@ static void __init qca956x_clocks_init(v
cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
cpu_pll /= (1 << out_div);
- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
@@ -574,7 +574,7 @@ static void __init qca956x_clocks_init(v
ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
ddr_pll /= (1 << out_div);
- clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
+ clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -618,19 +618,19 @@ void __init ath79_clocks_init(void)
const char *uart;
if (soc_is_ar71xx())
- ar71xx_clocks_init();
+ ar71xx_clocks_init(ath79_pll_base);
else if (soc_is_ar724x() || soc_is_ar913x())
- ar724x_clocks_init();
+ ar724x_clocks_init(ath79_pll_base);
else if (soc_is_ar933x())
- ar933x_clocks_init();
+ ar933x_clocks_init(ath79_pll_base);
else if (soc_is_ar934x())
- ar934x_clocks_init();
+ ar934x_clocks_init(ath79_pll_base);
else if (soc_is_qca953x())
- qca953x_clocks_init();
+ qca953x_clocks_init(ath79_pll_base);
else if (soc_is_qca955x())
- qca955x_clocks_init();
+ qca955x_clocks_init(ath79_pll_base);
else if (soc_is_qca956x() || soc_is_tp9343())
- qca956x_clocks_init();
+ qca956x_clocks_init(ath79_pll_base);
else
BUG();

View File

@ -1,229 +0,0 @@
From 5fadb2544ed0bb72ddddd846aa303bb9ed2d211c Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:24:07 +0100
Subject: [PATCH 24/33] MIPS: ath79: make specifying the reference clock in DT
optional
It can be autodetected for many SoCs using the strapping options.
If the clock is specified in DT, the autodetected value is ignored
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 84 +++++++++++++++++++++++--------------------------
1 file changed, 40 insertions(+), 44 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -80,6 +80,18 @@ static struct clk * __init ath79_set_ff_
return clk;
}
+static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
+{
+ struct clk *clk = clks[ATH79_CLK_REF];
+
+ if (clk)
+ rate = clk_get_rate(clk);
+ else
+ clk = ath79_set_clk(ATH79_CLK_REF, rate);
+
+ return rate;
+}
+
static void __init ar71xx_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
@@ -90,7 +102,7 @@ static void __init ar71xx_clocks_init(vo
u32 freq;
u32 div;
- ref_rate = AR71XX_BASE_FREQ;
+ ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
@@ -106,16 +118,17 @@ static void __init ar71xx_clocks_init(vo
div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
ahb_rate = cpu_rate / div;
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
}
-static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+static void __init ar724x_clocks_init(void __iomem *pll_base)
{
- u32 pll;
u32 mult, div, ddr_div, ahb_div;
+ u32 pll;
+
+ ath79_setup_ref_clk(AR71XX_BASE_FREQ);
pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
@@ -130,17 +143,9 @@ static void __init ar724x_clk_init(struc
ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
}
-static void __init ar724x_clocks_init(void __iomem *pll_base)
-{
- struct clk *ref_clk;
-
- ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
-
- ar724x_clk_init(ref_clk, pll_base);
-}
-
-static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+static void __init ar933x_clocks_init(void __iomem *pll_base)
{
+ unsigned long ref_rate;
u32 clock_ctrl;
u32 ref_div;
u32 ninit_mul;
@@ -149,6 +154,15 @@ static void __init ar9330_clk_init(struc
u32 cpu_div;
u32 ddr_div;
u32 ahb_div;
+ u32 t;
+
+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+ ref_rate = (40 * 1000 * 1000);
+ else
+ ref_rate = (25 * 1000 * 1000);
+
+ ath79_setup_ref_clk(ref_rate);
clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
@@ -197,23 +211,6 @@ static void __init ar9330_clk_init(struc
ref_div * out_div * ahb_div);
}
-static void __init ar933x_clocks_init(void __iomem *pll_base)
-{
- struct clk *ref_clk;
- unsigned long ref_rate;
- u32 t;
-
- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
- ref_rate = (40 * 1000 * 1000);
- else
- ref_rate = (25 * 1000 * 1000);
-
- ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
-
- ar9330_clk_init(ref_clk, ath79_pll_base);
-}
-
static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
u32 frac, u32 out_div)
{
@@ -253,6 +250,8 @@ static void __init ar934x_clocks_init(vo
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
@@ -339,7 +338,6 @@ static void __init ar934x_clocks_init(vo
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -363,6 +361,8 @@ static void __init qca953x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -423,7 +423,6 @@ static void __init qca953x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -445,6 +444,8 @@ static void __init qca955x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -505,7 +506,6 @@ static void __init qca955x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -537,6 +537,8 @@ static void __init qca956x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -606,7 +608,6 @@ static void __init qca956x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -682,10 +683,8 @@ static void __init ath79_clocks_init_dt_
void __iomem *pll_base;
ref_clk = of_clk_get(np, 0);
- if (IS_ERR(ref_clk)) {
- pr_err("%pOF: of_clk_get failed\n", np);
- goto err;
- }
+ if (!IS_ERR(ref_clk))
+ clks[ATH79_CLK_REF] = ref_clk;
pll_base = of_iomap(np, 0);
if (!pll_base) {
@@ -694,9 +693,9 @@ static void __init ath79_clocks_init_dt_
}
if (of_device_is_compatible(np, "qca,ar9130-pll"))
- ar724x_clk_init(ref_clk, pll_base);
+ ar724x_clocks_init(pll_base);
else if (of_device_is_compatible(np, "qca,ar9330-pll"))
- ar9330_clk_init(ref_clk, pll_base);
+ ar933x_clocks_init(pll_base);
else {
pr_err("%pOF: could not find any appropriate clk_init()\n", np);
goto err_iounmap;
@@ -714,9 +713,6 @@ err_iounmap:
err_clk:
clk_put(ref_clk);
-
-err:
- return;
}
CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);

View File

@ -1,77 +0,0 @@
From 6325626de001df98aebe51f3008b1aca05798d19 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:26:27 +0100
Subject: [PATCH 25/33] MIPS: ath79: support setting up clock via DT on all SoC
types
Use the same functions as the legacy code
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 39 ++++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -669,16 +669,6 @@ ath79_get_sys_clk_rate(const char *id)
#ifdef CONFIG_OF
static void __init ath79_clocks_init_dt(struct device_node *np)
{
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-}
-
-CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
-
-static void __init ath79_clocks_init_dt_ng(struct device_node *np)
-{
struct clk *ref_clk;
void __iomem *pll_base;
@@ -692,14 +682,21 @@ static void __init ath79_clocks_init_dt_
goto err_clk;
}
- if (of_device_is_compatible(np, "qca,ar9130-pll"))
+ if (of_device_is_compatible(np, "qca,ar7100-pll"))
+ ar71xx_clocks_init(pll_base);
+ else if (of_device_is_compatible(np, "qca,ar7240-pll") ||
+ of_device_is_compatible(np, "qca,ar9130-pll"))
ar724x_clocks_init(pll_base);
else if (of_device_is_compatible(np, "qca,ar9330-pll"))
ar933x_clocks_init(pll_base);
- else {
- pr_err("%pOF: could not find any appropriate clk_init()\n", np);
- goto err_iounmap;
- }
+ else if (of_device_is_compatible(np, "qca,ar9340-pll"))
+ ar934x_clocks_init(pll_base);
+ else if (of_device_is_compatible(np, "qca,qca9530-pll"))
+ qca953x_clocks_init(pll_base);
+ else if (of_device_is_compatible(np, "qca,qca9550-pll"))
+ qca955x_clocks_init(pll_base);
+ else if (of_device_is_compatible(np, "qca,qca9560-pll"))
+ qca956x_clocks_init(pll_base);
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
pr_err("%pOF: could not register clk provider\n", np);
@@ -714,6 +711,14 @@ err_iounmap:
err_clk:
clk_put(ref_clk);
}
-CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
-CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
+
+CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
+
#endif

View File

@ -1,59 +0,0 @@
From 78538d673801902108797f2c813e70cfbce280c9 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:27:28 +0100
Subject: [PATCH 26/33] MIPS: ath79: export switch MDIO reference clock
On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
clock. If that feature is not used, it defaults to the main reference
clock, like on all other SoC.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 8 ++++++++
include/dt-bindings/clock/ath79-clk.h | 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7
[ATH79_CLK_DDR] = "ddr",
[ATH79_CLK_AHB] = "ahb",
[ATH79_CLK_REF] = "ref",
+ [ATH79_CLK_MDIO] = "mdio",
};
static const char * __init ath79_clk_name(int type)
@@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(vo
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
+ ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
+
iounmap(dpll_base);
}
@@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt(
else if (of_device_is_compatible(np, "qca,qca9560-pll"))
qca956x_clocks_init(pll_base);
+ if (!clks[ATH79_CLK_MDIO])
+ clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
+
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
pr_err("%pOF: could not register clk provider\n", np);
goto err_iounmap;
--- a/include/dt-bindings/clock/ath79-clk.h
+++ b/include/dt-bindings/clock/ath79-clk.h
@@ -14,7 +14,8 @@
#define ATH79_CLK_DDR 1
#define ATH79_CLK_AHB 2
#define ATH79_CLK_REF 3
+#define ATH79_CLK_MDIO 4
-#define ATH79_CLK_END 4
+#define ATH79_CLK_END 5
#endif /* __DT_BINDINGS_ATH79_CLK_H */

View File

@ -1,233 +0,0 @@
From 3765b1f79593a0a9098ed15e48074c95403a53ee Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Sat, 23 Jun 2018 15:05:08 +0200
Subject: [PATCH 27/33] MIPS: ath79: drop legacy IRQ code
With the target now being fully OF based, we can drop the legacy IRQ code.
All IRQs are now handled via the new irqchip drivers.
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/Makefile | 2 +-
arch/mips/ath79/irq.c | 169 -------------------------------
arch/mips/ath79/setup.c | 6 ++
arch/mips/include/asm/mach-ath79/ath79.h | 4 -
4 files changed, 7 insertions(+), 174 deletions(-)
delete mode 100644 arch/mips/ath79/irq.c
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -8,7 +8,7 @@
# under the terms of the GNU General Public License version 2 as published
# by the Free Software Foundation.
-obj-y := prom.o setup.o irq.o common.o clock.o
+obj-y := prom.o setup.o common.o clock.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_PCI) += pci.o
--- a/arch/mips/ath79/irq.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Atheros AR71xx/AR724x/AR913x specific interrupt handling
- *
- * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irqchip.h>
-#include <linux/of_irq.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-
-#include <asm/mach-ath79/ath79.h>
-#include <asm/mach-ath79/ar71xx_regs.h>
-#include "common.h"
-#include "machtypes.h"
-
-
-static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
-{
- u32 status;
-
- status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
-
- if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
- ath79_ddr_wb_flush(3);
- generic_handle_irq(ATH79_IP2_IRQ(0));
- } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
- ath79_ddr_wb_flush(4);
- generic_handle_irq(ATH79_IP2_IRQ(1));
- } else {
- spurious_interrupt();
- }
-}
-
-static void ar934x_ip2_irq_init(void)
-{
- int i;
-
- for (i = ATH79_IP2_IRQ_BASE;
- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
- irq_set_chip_and_handler(i, &dummy_irq_chip,
- handle_level_irq);
-
- irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
-}
-
-static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
-{
- u32 status;
-
- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
- status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
-
- if (status == 0) {
- spurious_interrupt();
- return;
- }
-
- if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
- /* TODO: flush DDR? */
- generic_handle_irq(ATH79_IP2_IRQ(0));
- }
-
- if (status & QCA955X_EXT_INT_WMAC_ALL) {
- /* TODO: flush DDR? */
- generic_handle_irq(ATH79_IP2_IRQ(1));
- }
-}
-
-static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
-{
- u32 status;
-
- status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
- status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
- QCA955X_EXT_INT_USB1 |
- QCA955X_EXT_INT_USB2;
-
- if (status == 0) {
- spurious_interrupt();
- return;
- }
-
- if (status & QCA955X_EXT_INT_USB1) {
- /* TODO: flush DDR? */
- generic_handle_irq(ATH79_IP3_IRQ(0));
- }
-
- if (status & QCA955X_EXT_INT_USB2) {
- /* TODO: flush DDR? */
- generic_handle_irq(ATH79_IP3_IRQ(1));
- }
-
- if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
- /* TODO: flush DDR? */
- generic_handle_irq(ATH79_IP3_IRQ(2));
- }
-}
-
-static void qca955x_irq_init(void)
-{
- int i;
-
- for (i = ATH79_IP2_IRQ_BASE;
- i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
- irq_set_chip_and_handler(i, &dummy_irq_chip,
- handle_level_irq);
-
- irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
-
- for (i = ATH79_IP3_IRQ_BASE;
- i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
- irq_set_chip_and_handler(i, &dummy_irq_chip,
- handle_level_irq);
-
- irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
-}
-
-void __init arch_init_irq(void)
-{
- unsigned irq_wb_chan2 = -1;
- unsigned irq_wb_chan3 = -1;
- bool misc_is_ar71xx;
-
- if (mips_machtype == ATH79_MACH_GENERIC_OF) {
- irqchip_init();
- return;
- }
-
- if (soc_is_ar71xx() || soc_is_ar724x() ||
- soc_is_ar913x() || soc_is_ar933x()) {
- irq_wb_chan2 = 3;
- irq_wb_chan3 = 2;
- } else if (soc_is_ar934x()) {
- irq_wb_chan3 = 2;
- }
-
- ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
-
- if (soc_is_ar71xx() || soc_is_ar913x())
- misc_is_ar71xx = true;
- else if (soc_is_ar724x() ||
- soc_is_ar933x() ||
- soc_is_ar934x() ||
- soc_is_qca955x())
- misc_is_ar71xx = false;
- else
- BUG();
- ath79_misc_irq_init(
- ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
- ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
-
- if (soc_is_ar934x())
- ar934x_ip2_irq_init();
- else if (soc_is_qca955x())
- qca955x_irq_init();
-}
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -19,6 +19,7 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_fdt.h>
+#include <linux/irqchip.h>
#include <asm/bootinfo.h>
#include <asm/idle.h>
@@ -305,6 +306,11 @@ void __init plat_time_init(void)
mips_hpt_frequency = cpu_clk_rate / 2;
}
+void __init arch_init_irq(void)
+{
+ irqchip_init();
+}
+
static int __init ath79_setup(void)
{
if (mips_machtype == ATH79_MACH_GENERIC_OF)
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -178,8 +178,4 @@ static inline u32 ath79_reset_rr(unsigne
void ath79_device_reset_set(u32 mask);
void ath79_device_reset_clear(u32 mask);
-void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
-void ath79_misc_irq_init(void __iomem *regs, int irq,
- int irq_base, bool is_ar71xx);
-
#endif /* __ASM_MACH_ATH79_H */

View File

@ -1,379 +0,0 @@
From d0f1420702ed47a82572aaf39e7407055518d14e Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Sat, 23 Jun 2018 15:05:19 +0200
Subject: [PATCH 29/33] MIPS: ath79: drop legacy pci code
With the target now being fully OF based, we can drop the legacy pci
platform code. The only bits that we need to keep is the fixup code
which we move to its own code file.
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/Makefile | 1 -
arch/mips/ath79/pci.c | 273 --------------------------------------------
arch/mips/ath79/pci.h | 35 ------
arch/mips/pci/Makefile | 1 +
arch/mips/pci/fixup-ath79.c | 21 ++++
5 files changed, 22 insertions(+), 309 deletions(-)
delete mode 100644 arch/mips/ath79/pci.c
delete mode 100644 arch/mips/ath79/pci.h
create mode 100644 arch/mips/pci/fixup-ath79.c
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -11,7 +11,6 @@
obj-y := prom.o setup.o common.o clock.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-obj-$(CONFIG_PCI) += pci.o
#
# Devices
--- a/arch/mips/ath79/pci.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * Atheros AR71XX/AR724X specific PCI setup code
- *
- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * Parts of this file are based on Atheros' 2.6.15 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/resource.h>
-#include <linux/platform_device.h>
-#include <asm/mach-ath79/ar71xx_regs.h>
-#include <asm/mach-ath79/ath79.h>
-#include <asm/mach-ath79/irq.h>
-#include "pci.h"
-
-static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
-static const struct ath79_pci_irq *ath79_pci_irq_map;
-static unsigned ath79_pci_nr_irqs;
-
-static const struct ath79_pci_irq ar71xx_pci_irq_map[] = {
- {
- .slot = 17,
- .pin = 1,
- .irq = ATH79_PCI_IRQ(0),
- }, {
- .slot = 18,
- .pin = 1,
- .irq = ATH79_PCI_IRQ(1),
- }, {
- .slot = 19,
- .pin = 1,
- .irq = ATH79_PCI_IRQ(2),
- }
-};
-
-static const struct ath79_pci_irq ar724x_pci_irq_map[] = {
- {
- .slot = 0,
- .pin = 1,
- .irq = ATH79_PCI_IRQ(0),
- }
-};
-
-static const struct ath79_pci_irq qca955x_pci_irq_map[] = {
- {
- .bus = 0,
- .slot = 0,
- .pin = 1,
- .irq = ATH79_PCI_IRQ(0),
- },
- {
- .bus = 1,
- .slot = 0,
- .pin = 1,
- .irq = ATH79_PCI_IRQ(1),
- },
-};
-
-int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
-{
- int irq = -1;
- int i;
-
- if (ath79_pci_nr_irqs == 0 ||
- ath79_pci_irq_map == NULL) {
- if (soc_is_ar71xx()) {
- ath79_pci_irq_map = ar71xx_pci_irq_map;
- ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
- } else if (soc_is_ar724x() ||
- soc_is_ar9342() ||
- soc_is_ar9344()) {
- ath79_pci_irq_map = ar724x_pci_irq_map;
- ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
- } else if (soc_is_qca955x()) {
- ath79_pci_irq_map = qca955x_pci_irq_map;
- ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
- } else {
- pr_crit("pci %s: invalid irq map\n",
- pci_name((struct pci_dev *) dev));
- return irq;
- }
- }
-
- for (i = 0; i < ath79_pci_nr_irqs; i++) {
- const struct ath79_pci_irq *entry;
-
- entry = &ath79_pci_irq_map[i];
- if (entry->bus == dev->bus->number &&
- entry->slot == slot &&
- entry->pin == pin) {
- irq = entry->irq;
- break;
- }
- }
-
- if (irq < 0)
- pr_crit("pci %s: no irq found for pin %u\n",
- pci_name((struct pci_dev *) dev), pin);
- else
- pr_info("pci %s: using irq %d for pin %u\n",
- pci_name((struct pci_dev *) dev), irq, pin);
-
- return irq;
-}
-
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- if (ath79_pci_plat_dev_init)
- return ath79_pci_plat_dev_init(dev);
-
- return 0;
-}
-
-void __init ath79_pci_set_irq_map(unsigned nr_irqs,
- const struct ath79_pci_irq *map)
-{
- ath79_pci_nr_irqs = nr_irqs;
- ath79_pci_irq_map = map;
-}
-
-void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
-{
- ath79_pci_plat_dev_init = func;
-}
-
-static struct platform_device *
-ath79_register_pci_ar71xx(void)
-{
- struct platform_device *pdev;
- struct resource res[4];
-
- memset(res, 0, sizeof(res));
-
- res[0].name = "cfg_base";
- res[0].flags = IORESOURCE_MEM;
- res[0].start = AR71XX_PCI_CFG_BASE;
- res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
-
- res[1].flags = IORESOURCE_IRQ;
- res[1].start = ATH79_CPU_IRQ(2);
- res[1].end = ATH79_CPU_IRQ(2);
-
- res[2].name = "io_base";
- res[2].flags = IORESOURCE_IO;
- res[2].start = 0;
- res[2].end = 0;
-
- res[3].name = "mem_base";
- res[3].flags = IORESOURCE_MEM;
- res[3].start = AR71XX_PCI_MEM_BASE;
- res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
-
- pdev = platform_device_register_simple("ar71xx-pci", -1,
- res, ARRAY_SIZE(res));
- return pdev;
-}
-
-static struct platform_device *
-ath79_register_pci_ar724x(int id,
- unsigned long cfg_base,
- unsigned long ctrl_base,
- unsigned long crp_base,
- unsigned long mem_base,
- unsigned long mem_size,
- unsigned long io_base,
- int irq)
-{
- struct platform_device *pdev;
- struct resource res[6];
-
- memset(res, 0, sizeof(res));
-
- res[0].name = "cfg_base";
- res[0].flags = IORESOURCE_MEM;
- res[0].start = cfg_base;
- res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
-
- res[1].name = "ctrl_base";
- res[1].flags = IORESOURCE_MEM;
- res[1].start = ctrl_base;
- res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
-
- res[2].flags = IORESOURCE_IRQ;
- res[2].start = irq;
- res[2].end = irq;
-
- res[3].name = "mem_base";
- res[3].flags = IORESOURCE_MEM;
- res[3].start = mem_base;
- res[3].end = mem_base + mem_size - 1;
-
- res[4].name = "io_base";
- res[4].flags = IORESOURCE_IO;
- res[4].start = io_base;
- res[4].end = io_base;
-
- res[5].name = "crp_base";
- res[5].flags = IORESOURCE_MEM;
- res[5].start = crp_base;
- res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
-
- pdev = platform_device_register_simple("ar724x-pci", id,
- res, ARRAY_SIZE(res));
- return pdev;
-}
-
-int __init ath79_register_pci(void)
-{
- struct platform_device *pdev = NULL;
-
- if (soc_is_ar71xx()) {
- pdev = ath79_register_pci_ar71xx();
- } else if (soc_is_ar724x()) {
- pdev = ath79_register_pci_ar724x(-1,
- AR724X_PCI_CFG_BASE,
- AR724X_PCI_CTRL_BASE,
- AR724X_PCI_CRP_BASE,
- AR724X_PCI_MEM_BASE,
- AR724X_PCI_MEM_SIZE,
- 0,
- ATH79_CPU_IRQ(2));
- } else if (soc_is_ar9342() ||
- soc_is_ar9344()) {
- u32 bootstrap;
-
- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
- if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
- return -ENODEV;
-
- pdev = ath79_register_pci_ar724x(-1,
- AR724X_PCI_CFG_BASE,
- AR724X_PCI_CTRL_BASE,
- AR724X_PCI_CRP_BASE,
- AR724X_PCI_MEM_BASE,
- AR724X_PCI_MEM_SIZE,
- 0,
- ATH79_IP2_IRQ(0));
- } else if (soc_is_qca9558()) {
- pdev = ath79_register_pci_ar724x(0,
- QCA955X_PCI_CFG_BASE0,
- QCA955X_PCI_CTRL_BASE0,
- QCA955X_PCI_CRP_BASE0,
- QCA955X_PCI_MEM_BASE0,
- QCA955X_PCI_MEM_SIZE,
- 0,
- ATH79_IP2_IRQ(0));
-
- pdev = ath79_register_pci_ar724x(1,
- QCA955X_PCI_CFG_BASE1,
- QCA955X_PCI_CTRL_BASE1,
- QCA955X_PCI_CRP_BASE1,
- QCA955X_PCI_MEM_BASE1,
- QCA955X_PCI_MEM_SIZE,
- 1,
- ATH79_IP3_IRQ(2));
- } else {
- /* No PCI support */
- return -ENODEV;
- }
-
- if (!pdev)
- pr_err("unable to register PCI controller device\n");
-
- return pdev ? 0 : -ENODEV;
-}
--- a/arch/mips/ath79/pci.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Atheros AR71XX/AR724X PCI support
- *
- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _ATH79_PCI_H
-#define _ATH79_PCI_H
-
-struct ath79_pci_irq {
- int bus;
- u8 slot;
- u8 pin;
- int irq;
-};
-
-#ifdef CONFIG_PCI
-void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map);
-void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
-int ath79_register_pci(void);
-#else
-static inline void
-ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {}
-static inline void
-ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {}
-static inline int ath79_register_pci(void) { return 0; }
-#endif
-
-#endif /* _ATH79_PCI_H */
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-vir
#
# These are still pretty much in the old state, watch, go blind.
#
+obj-$(CONFIG_ATH79) += fixup-ath79.o
obj-$(CONFIG_LASAT) += pci-lasat.o
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
--- /dev/null
+++ b/arch/mips/pci/fixup-ath79.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2018 John Crispin <john@phrozen.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+//#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ return of_irq_parse_and_map_pci(dev, slot, pin);
+}

View File

@ -1,933 +0,0 @@
From dce930fba8ad3a90ccd164f199e57c2d61937ccd Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Sat, 23 Jun 2018 15:12:38 +0200
Subject: [PATCH 30/33] MIPS: ath79: drop platform device registration code
With the target now being fully OF based, we can drop the legacy platform
device registration code. All devices and their drivers are now probed
via OF.
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/Makefile | 10 --
arch/mips/ath79/common.h | 2 -
arch/mips/ath79/dev-common.c | 159 ------------------------
arch/mips/ath79/dev-common.h | 18 ---
arch/mips/ath79/dev-gpio-buttons.c | 56 ---------
arch/mips/ath79/dev-gpio-buttons.h | 23 ----
arch/mips/ath79/dev-leds-gpio.c | 54 ---------
arch/mips/ath79/dev-leds-gpio.h | 21 ----
arch/mips/ath79/dev-spi.c | 38 ------
arch/mips/ath79/dev-spi.h | 22 ----
arch/mips/ath79/dev-usb.c | 242 -------------------------------------
arch/mips/ath79/dev-usb.h | 17 ---
arch/mips/ath79/dev-wmac.c | 155 ------------------------
arch/mips/ath79/dev-wmac.h | 17 ---
arch/mips/ath79/setup.c | 1 -
15 files changed, 835 deletions(-)
delete mode 100644 arch/mips/ath79/dev-common.c
delete mode 100644 arch/mips/ath79/dev-common.h
delete mode 100644 arch/mips/ath79/dev-gpio-buttons.c
delete mode 100644 arch/mips/ath79/dev-gpio-buttons.h
delete mode 100644 arch/mips/ath79/dev-leds-gpio.c
delete mode 100644 arch/mips/ath79/dev-leds-gpio.h
delete mode 100644 arch/mips/ath79/dev-spi.c
delete mode 100644 arch/mips/ath79/dev-spi.h
delete mode 100644 arch/mips/ath79/dev-usb.c
delete mode 100644 arch/mips/ath79/dev-usb.h
delete mode 100644 arch/mips/ath79/dev-wmac.c
delete mode 100644 arch/mips/ath79/dev-wmac.h
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -11,13 +11,3 @@
obj-y := prom.o setup.o common.o clock.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-
-#
-# Devices
-#
-obj-y += dev-common.o
-obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
-obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
-obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
-obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
-obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
--- a/arch/mips/ath79/common.h
+++ b/arch/mips/ath79/common.h
@@ -24,6 +24,4 @@ unsigned long ath79_get_sys_clk_rate(con
void ath79_ddr_ctrl_init(void);
-void ath79_gpio_init(void);
-
#endif /* __ATH79_COMMON_H */
--- a/arch/mips/ath79/dev-common.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Atheros AR71XX/AR724X/AR913X common devices
- *
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * Parts of this file are based on Atheros' 2.6.15 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/gpio-ath79.h>
-#include <linux/serial_8250.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-
-#include <asm/mach-ath79/ath79.h>
-#include <asm/mach-ath79/ar71xx_regs.h>
-#include "common.h"
-#include "dev-common.h"
-
-static struct resource ath79_uart_resources[] = {
- {
- .start = AR71XX_UART_BASE,
- .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
-static struct plat_serial8250_port ath79_uart_data[] = {
- {
- .mapbase = AR71XX_UART_BASE,
- .irq = ATH79_MISC_IRQ(3),
- .flags = AR71XX_UART_FLAGS,
- .iotype = UPIO_MEM32,
- .regshift = 2,
- }, {
- /* terminating entry */
- }
-};
-
-static struct platform_device ath79_uart_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .resource = ath79_uart_resources,
- .num_resources = ARRAY_SIZE(ath79_uart_resources),
- .dev = {
- .platform_data = ath79_uart_data
- },
-};
-
-static struct resource ar933x_uart_resources[] = {
- {
- .start = AR933X_UART_BASE,
- .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = ATH79_MISC_IRQ(3),
- .end = ATH79_MISC_IRQ(3),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device ar933x_uart_device = {
- .name = "ar933x-uart",
- .id = -1,
- .resource = ar933x_uart_resources,
- .num_resources = ARRAY_SIZE(ar933x_uart_resources),
-};
-
-void __init ath79_register_uart(void)
-{
- unsigned long uart_clk_rate;
-
- uart_clk_rate = ath79_get_sys_clk_rate("uart");
-
- if (soc_is_ar71xx() ||
- soc_is_ar724x() ||
- soc_is_ar913x() ||
- soc_is_ar934x() ||
- soc_is_qca955x()) {
- ath79_uart_data[0].uartclk = uart_clk_rate;
- platform_device_register(&ath79_uart_device);
- } else if (soc_is_ar933x()) {
- platform_device_register(&ar933x_uart_device);
- } else {
- BUG();
- }
-}
-
-void __init ath79_register_wdt(void)
-{
- struct resource res;
-
- memset(&res, 0, sizeof(res));
-
- res.flags = IORESOURCE_MEM;
- res.start = AR71XX_RESET_BASE + AR71XX_RESET_REG_WDOG_CTRL;
- res.end = res.start + 0x8 - 1;
-
- platform_device_register_simple("ath79-wdt", -1, &res, 1);
-}
-
-static struct ath79_gpio_platform_data ath79_gpio_pdata;
-
-static struct resource ath79_gpio_resources[] = {
- {
- .flags = IORESOURCE_MEM,
- .start = AR71XX_GPIO_BASE,
- .end = AR71XX_GPIO_BASE + AR71XX_GPIO_SIZE - 1,
- },
- {
- .start = ATH79_MISC_IRQ(2),
- .end = ATH79_MISC_IRQ(2),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device ath79_gpio_device = {
- .name = "ath79-gpio",
- .id = -1,
- .resource = ath79_gpio_resources,
- .num_resources = ARRAY_SIZE(ath79_gpio_resources),
- .dev = {
- .platform_data = &ath79_gpio_pdata
- },
-};
-
-void __init ath79_gpio_init(void)
-{
- if (soc_is_ar71xx()) {
- ath79_gpio_pdata.ngpios = AR71XX_GPIO_COUNT;
- } else if (soc_is_ar7240()) {
- ath79_gpio_pdata.ngpios = AR7240_GPIO_COUNT;
- } else if (soc_is_ar7241() || soc_is_ar7242()) {
- ath79_gpio_pdata.ngpios = AR7241_GPIO_COUNT;
- } else if (soc_is_ar913x()) {
- ath79_gpio_pdata.ngpios = AR913X_GPIO_COUNT;
- } else if (soc_is_ar933x()) {
- ath79_gpio_pdata.ngpios = AR933X_GPIO_COUNT;
- } else if (soc_is_ar934x()) {
- ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
- ath79_gpio_pdata.oe_inverted = 1;
- } else if (soc_is_qca955x()) {
- ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
- ath79_gpio_pdata.oe_inverted = 1;
- } else {
- BUG();
- }
-
- platform_device_register(&ath79_gpio_device);
-}
--- a/arch/mips/ath79/dev-common.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Atheros AR71XX/AR724X/AR913X common devices
- *
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _ATH79_DEV_COMMON_H
-#define _ATH79_DEV_COMMON_H
-
-void ath79_register_uart(void);
-void ath79_register_wdt(void);
-
-#endif /* _ATH79_DEV_COMMON_H */
--- a/arch/mips/ath79/dev-gpio-buttons.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Atheros AR71XX/AR724X/AR913X GPIO button support
- *
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include "linux/init.h"
-#include "linux/slab.h"
-#include <linux/platform_device.h>
-
-#include "dev-gpio-buttons.h"
-
-void __init ath79_register_gpio_keys_polled(int id,
- unsigned poll_interval,
- unsigned nbuttons,
- struct gpio_keys_button *buttons)
-{
- struct platform_device *pdev;
- struct gpio_keys_platform_data pdata;
- struct gpio_keys_button *p;
- int err;
-
- p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL);
- if (!p)
- return;
-
- pdev = platform_device_alloc("gpio-keys-polled", id);
- if (!pdev)
- goto err_free_buttons;
-
- memset(&pdata, 0, sizeof(pdata));
- pdata.poll_interval = poll_interval;
- pdata.nbuttons = nbuttons;
- pdata.buttons = p;
-
- err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
- if (err)
- goto err_put_pdev;
-
- err = platform_device_add(pdev);
- if (err)
- goto err_put_pdev;
-
- return;
-
-err_put_pdev:
- platform_device_put(pdev);
-
-err_free_buttons:
- kfree(p);
-}
--- a/arch/mips/ath79/dev-gpio-buttons.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Atheros AR71XX/AR724X/AR913X GPIO button support
- *
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _ATH79_DEV_GPIO_BUTTONS_H
-#define _ATH79_DEV_GPIO_BUTTONS_H
-
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-void ath79_register_gpio_keys_polled(int id,
- unsigned poll_interval,
- unsigned nbuttons,
- struct gpio_keys_button *buttons);
-
-#endif /* _ATH79_DEV_GPIO_BUTTONS_H */
--- a/arch/mips/ath79/dev-leds-gpio.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support
- *
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-
-#include "dev-leds-gpio.h"
-
-void __init ath79_register_leds_gpio(int id,
- unsigned num_leds,
- struct gpio_led *leds)
-{
- struct platform_device *pdev;
- struct gpio_led_platform_data pdata;
- struct gpio_led *p;
- int err;
-
- p = kmemdup(leds, num_leds * sizeof(*p), GFP_KERNEL);
- if (!p)
- return;
-
- pdev = platform_device_alloc("leds-gpio", id);
- if (!pdev)
- goto err_free_leds;
-
- memset(&pdata, 0, sizeof(pdata));
- pdata.num_leds = num_leds;
- pdata.leds = p;
-
- err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
- if (err)
- goto err_put_pdev;
-
- err = platform_device_add(pdev);
- if (err)
- goto err_put_pdev;
-
- return;
-
-err_put_pdev:
- platform_device_put(pdev);
-
-err_free_leds:
- kfree(p);
-}
--- a/arch/mips/ath79/dev-leds-gpio.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support
- *
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _ATH79_DEV_LEDS_GPIO_H
-#define _ATH79_DEV_LEDS_GPIO_H
-
-#include <linux/leds.h>
-
-void ath79_register_leds_gpio(int id,
- unsigned num_leds,
- struct gpio_led *leds);
-
-#endif /* _ATH79_DEV_LEDS_GPIO_H */
--- a/arch/mips/ath79/dev-spi.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Atheros AR71XX/AR724X/AR913X SPI controller device
- *
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <asm/mach-ath79/ar71xx_regs.h>
-#include "dev-spi.h"
-
-static struct resource ath79_spi_resources[] = {
- {
- .start = AR71XX_SPI_BASE,
- .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device ath79_spi_device = {
- .name = "ath79-spi",
- .id = -1,
- .resource = ath79_spi_resources,
- .num_resources = ARRAY_SIZE(ath79_spi_resources),
-};
-
-void __init ath79_register_spi(struct ath79_spi_platform_data *pdata,
- struct spi_board_info const *info,
- unsigned n)
-{
- spi_register_board_info(info, n);
- ath79_spi_device.dev.platform_data = pdata;
- platform_device_register(&ath79_spi_device);
-}
--- a/arch/mips/ath79/dev-spi.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Atheros AR71XX/AR724X/AR913X SPI controller device
- *
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _ATH79_DEV_SPI_H
-#define _ATH79_DEV_SPI_H
-
-#include <linux/spi/spi.h>
-#include <asm/mach-ath79/ath79_spi_platform.h>
-
-void ath79_register_spi(struct ath79_spi_platform_data *pdata,
- struct spi_board_info const *info,
- unsigned n);
-
-#endif /* _ATH79_DEV_SPI_H */
--- a/arch/mips/ath79/dev-usb.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Atheros AR7XXX/AR9XXX USB Host Controller device
- *
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * Parts of this file are based on Atheros' 2.6.15 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/usb/ehci_pdriver.h>
-#include <linux/usb/ohci_pdriver.h>
-
-#include <asm/mach-ath79/ath79.h>
-#include <asm/mach-ath79/ar71xx_regs.h>
-#include "common.h"
-#include "dev-usb.h"
-
-static u64 ath79_usb_dmamask = DMA_BIT_MASK(32);
-
-static struct usb_ohci_pdata ath79_ohci_pdata = {
-};
-
-static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
- .has_synopsys_hc_bug = 1,
-};
-
-static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
- .caps_offset = 0x100,
- .has_tt = 1,
-};
-
-static void __init ath79_usb_register(const char *name, int id,
- unsigned long base, unsigned long size,
- int irq, const void *data,
- size_t data_size)
-{
- struct resource res[2];
- struct platform_device *pdev;
-
- memset(res, 0, sizeof(res));
-
- res[0].flags = IORESOURCE_MEM;
- res[0].start = base;
- res[0].end = base + size - 1;
-
- res[1].flags = IORESOURCE_IRQ;
- res[1].start = irq;
- res[1].end = irq;
-
- pdev = platform_device_register_resndata(NULL, name, id,
- res, ARRAY_SIZE(res),
- data, data_size);
-
- if (IS_ERR(pdev)) {
- pr_err("ath79: unable to register USB at %08lx, err=%d\n",
- base, (int) PTR_ERR(pdev));
- return;
- }
-
- pdev->dev.dma_mask = &ath79_usb_dmamask;
- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-}
-
-#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
- AR71XX_RESET_USB_PHY | \
- AR71XX_RESET_USB_OHCI_DLL)
-
-static void __init ath79_usb_setup(void)
-{
- void __iomem *usb_ctrl_base;
-
- ath79_device_reset_set(AR71XX_USB_RESET_MASK);
- mdelay(1000);
- ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
-
- usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
-
- /* Turning on the Buff and Desc swap bits */
- __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
-
- /* WAR for HW bug. Here it adjusts the duration between two SOFS */
- __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
-
- iounmap(usb_ctrl_base);
-
- mdelay(900);
-
- ath79_usb_register("ohci-platform", -1,
- AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE,
- ATH79_MISC_IRQ(6),
- &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
-
- ath79_usb_register("ehci-platform", -1,
- AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE,
- ATH79_CPU_IRQ(3),
- &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1));
-}
-
-static void __init ar7240_usb_setup(void)
-{
- void __iomem *usb_ctrl_base;
-
- ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
- ath79_device_reset_set(AR7240_RESET_USB_HOST);
-
- mdelay(1000);
-
- ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
- ath79_device_reset_clear(AR7240_RESET_USB_HOST);
-
- usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
-
- /* WAR for HW bug. Here it adjusts the duration between two SOFS */
- __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
-
- iounmap(usb_ctrl_base);
-
- ath79_usb_register("ohci-platform", -1,
- AR7240_OHCI_BASE, AR7240_OHCI_SIZE,
- ATH79_CPU_IRQ(3),
- &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
-}
-
-static void __init ar724x_usb_setup(void)
-{
- ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
- mdelay(10);
-
- ath79_device_reset_clear(AR724X_RESET_USB_HOST);
- mdelay(10);
-
- ath79_device_reset_clear(AR724X_RESET_USB_PHY);
- mdelay(10);
-
- ath79_usb_register("ehci-platform", -1,
- AR724X_EHCI_BASE, AR724X_EHCI_SIZE,
- ATH79_CPU_IRQ(3),
- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
-}
-
-static void __init ar913x_usb_setup(void)
-{
- ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
- mdelay(10);
-
- ath79_device_reset_clear(AR913X_RESET_USB_HOST);
- mdelay(10);
-
- ath79_device_reset_clear(AR913X_RESET_USB_PHY);
- mdelay(10);
-
- ath79_usb_register("ehci-platform", -1,
- AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
- ATH79_CPU_IRQ(3),
- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
-}
-
-static void __init ar933x_usb_setup(void)
-{
- ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
- mdelay(10);
-
- ath79_device_reset_clear(AR933X_RESET_USB_HOST);
- mdelay(10);
-
- ath79_device_reset_clear(AR933X_RESET_USB_PHY);
- mdelay(10);
-
- ath79_usb_register("ehci-platform", -1,
- AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
- ATH79_CPU_IRQ(3),
- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
-}
-
-static void __init ar934x_usb_setup(void)
-{
- u32 bootstrap;
-
- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
- return;
-
- ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
- udelay(1000);
-
- ath79_device_reset_clear(AR934X_RESET_USB_PHY);
- udelay(1000);
-
- ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
- udelay(1000);
-
- ath79_device_reset_clear(AR934X_RESET_USB_HOST);
- udelay(1000);
-
- ath79_usb_register("ehci-platform", -1,
- AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
- ATH79_CPU_IRQ(3),
- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
-}
-
-static void __init qca955x_usb_setup(void)
-{
- ath79_usb_register("ehci-platform", 0,
- QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
- ATH79_IP3_IRQ(0),
- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
-
- ath79_usb_register("ehci-platform", 1,
- QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
- ATH79_IP3_IRQ(1),
- &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
-}
-
-void __init ath79_register_usb(void)
-{
- if (soc_is_ar71xx())
- ath79_usb_setup();
- else if (soc_is_ar7240())
- ar7240_usb_setup();
- else if (soc_is_ar7241() || soc_is_ar7242())
- ar724x_usb_setup();
- else if (soc_is_ar913x())
- ar913x_usb_setup();
- else if (soc_is_ar933x())
- ar933x_usb_setup();
- else if (soc_is_ar934x())
- ar934x_usb_setup();
- else if (soc_is_qca955x())
- qca955x_usb_setup();
- else
- BUG();
-}
--- a/arch/mips/ath79/dev-usb.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Atheros AR71XX/AR724X/AR913X USB Host Controller support
- *
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _ATH79_DEV_USB_H
-#define _ATH79_DEV_USB_H
-
-void ath79_register_usb(void);
-
-#endif /* _ATH79_DEV_USB_H */
--- a/arch/mips/ath79/dev-wmac.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Atheros AR913X/AR933X SoC built-in WMAC device support
- *
- * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/ath9k_platform.h>
-
-#include <asm/mach-ath79/ath79.h>
-#include <asm/mach-ath79/ar71xx_regs.h>
-#include "dev-wmac.h"
-
-static struct ath9k_platform_data ath79_wmac_data;
-
-static struct resource ath79_wmac_resources[] = {
- {
- /* .start and .end fields are filled dynamically */
- .flags = IORESOURCE_MEM,
- }, {
- /* .start and .end fields are filled dynamically */
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device ath79_wmac_device = {
- .name = "ath9k",
- .id = -1,
- .resource = ath79_wmac_resources,
- .num_resources = ARRAY_SIZE(ath79_wmac_resources),
- .dev = {
- .platform_data = &ath79_wmac_data,
- },
-};
-
-static void __init ar913x_wmac_setup(void)
-{
- /* reset the WMAC */
- ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
- mdelay(10);
-
- ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
- mdelay(10);
-
- ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
- ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
- ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
- ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
-}
-
-
-static int ar933x_wmac_reset(void)
-{
- ath79_device_reset_set(AR933X_RESET_WMAC);
- ath79_device_reset_clear(AR933X_RESET_WMAC);
-
- return 0;
-}
-
-static int ar933x_r1_get_wmac_revision(void)
-{
- return ath79_soc_rev;
-}
-
-static void __init ar933x_wmac_setup(void)
-{
- u32 t;
-
- ar933x_wmac_reset();
-
- ath79_wmac_device.name = "ar933x_wmac";
-
- ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
- ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
- ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
- ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
-
- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
- ath79_wmac_data.is_clk_25mhz = false;
- else
- ath79_wmac_data.is_clk_25mhz = true;
-
- if (ath79_soc_rev == 1)
- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
-
- ath79_wmac_data.external_reset = ar933x_wmac_reset;
-}
-
-static void ar934x_wmac_setup(void)
-{
- u32 t;
-
- ath79_wmac_device.name = "ar934x_wmac";
-
- ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
- ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
- ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
- ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
-
- t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
- if (t & AR934X_BOOTSTRAP_REF_CLK_40)
- ath79_wmac_data.is_clk_25mhz = false;
- else
- ath79_wmac_data.is_clk_25mhz = true;
-}
-
-static void qca955x_wmac_setup(void)
-{
- u32 t;
-
- ath79_wmac_device.name = "qca955x_wmac";
-
- ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
- ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
- ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
- ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
-
- t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
- if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
- ath79_wmac_data.is_clk_25mhz = false;
- else
- ath79_wmac_data.is_clk_25mhz = true;
-}
-
-void __init ath79_register_wmac(u8 *cal_data)
-{
- if (soc_is_ar913x())
- ar913x_wmac_setup();
- else if (soc_is_ar933x())
- ar933x_wmac_setup();
- else if (soc_is_ar934x())
- ar934x_wmac_setup();
- else if (soc_is_qca955x())
- qca955x_wmac_setup();
- else
- BUG();
-
- if (cal_data)
- memcpy(ath79_wmac_data.eeprom_data, cal_data,
- sizeof(ath79_wmac_data.eeprom_data));
-
- platform_device_register(&ath79_wmac_device);
-}
--- a/arch/mips/ath79/dev-wmac.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Atheros AR913X/AR933X SoC built-in WMAC device support
- *
- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _ATH79_DEV_WMAC_H
-#define _ATH79_DEV_WMAC_H
-
-void ath79_register_wmac(u8 *cal_data);
-
-#endif /* _ATH79_DEV_WMAC_H */
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -32,7 +32,6 @@
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
-#include "dev-common.h"
#define ATH79_SYS_TYPE_LEN 64

View File

@ -1,95 +0,0 @@
From 00e4313da4609074fff134e61dd9ffe3fd37474d Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Sun, 24 Jun 2018 09:39:41 +0200
Subject: [PATCH 31/33] MIPS: ath79: drop !OF clock code
With the target now being fully OF based, we can drop the legacy clock
registration code. All clocks are now probed via devicetree.
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 56 ------------------------------------------------
arch/mips/ath79/common.h | 3 ---
2 files changed, 59 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -617,60 +617,6 @@ static void __init qca956x_clocks_init(v
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
}
-void __init ath79_clocks_init(void)
-{
- const char *wdt;
- const char *uart;
-
- if (soc_is_ar71xx())
- ar71xx_clocks_init(ath79_pll_base);
- else if (soc_is_ar724x() || soc_is_ar913x())
- ar724x_clocks_init(ath79_pll_base);
- else if (soc_is_ar933x())
- ar933x_clocks_init(ath79_pll_base);
- else if (soc_is_ar934x())
- ar934x_clocks_init(ath79_pll_base);
- else if (soc_is_qca953x())
- qca953x_clocks_init(ath79_pll_base);
- else if (soc_is_qca955x())
- qca955x_clocks_init(ath79_pll_base);
- else if (soc_is_qca956x() || soc_is_tp9343())
- qca956x_clocks_init(ath79_pll_base);
- else
- BUG();
-
- if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
- wdt = "ahb";
- uart = "ahb";
- } else if (soc_is_ar933x()) {
- wdt = "ahb";
- uart = "ref";
- } else {
- wdt = "ref";
- uart = "ref";
- }
-
- clk_add_alias("wdt", NULL, wdt, NULL);
- clk_add_alias("uart", NULL, uart, NULL);
-}
-
-unsigned long __init
-ath79_get_sys_clk_rate(const char *id)
-{
- struct clk *clk;
- unsigned long rate;
-
- clk = clk_get(NULL, id);
- if (IS_ERR(clk))
- panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
-
- rate = clk_get_rate(clk);
- clk_put(clk);
-
- return rate;
-}
-
-#ifdef CONFIG_OF
static void __init ath79_clocks_init_dt(struct device_node *np)
{
struct clk *ref_clk;
@@ -727,5 +673,3 @@ CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-p
CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
-
-#endif
--- a/arch/mips/ath79/common.h
+++ b/arch/mips/ath79/common.h
@@ -19,9 +19,6 @@
#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
#define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024)
-void ath79_clocks_init(void);
-unsigned long ath79_get_sys_clk_rate(const char *id);
-
void ath79_ddr_ctrl_init(void);
#endif /* __ATH79_COMMON_H */

View File

@ -1,93 +0,0 @@
From 3fc8585cf76022dba7496627074d42af88c30718 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Sat, 23 Jun 2018 15:16:55 +0200
Subject: [PATCH 32/33] MIPS: ath79: sanitize symbols
We no longer need to select which SoCs are supported as the whole arch
code is always built. So lets drop all the SoC symbols
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/Kconfig | 2 ++
arch/mips/ath79/Kconfig | 44 +++++---------------------------------------
arch/mips/pci/Makefile | 2 +-
3 files changed, 8 insertions(+), 40 deletions(-)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -208,6 +208,8 @@ config ATH79
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_ZBOOT_UART_PROM
+ select HW_HAS_PCI
+ select USB_ARCH_HAS_EHCI
select USE_OF
select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
help
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -1,48 +1,14 @@
# SPDX-License-Identifier: GPL-2.0
if ATH79
-config SOC_AR71XX
- select HW_HAS_PCI
- def_bool n
-
-config SOC_AR724X
- select HW_HAS_PCI
- select PCI_AR724X if PCI
- def_bool n
-
-config SOC_AR913X
- def_bool n
-
-config SOC_AR933X
- def_bool n
-
-config SOC_AR934X
- select HW_HAS_PCI
- select PCI_AR724X if PCI
- def_bool n
-
-config SOC_QCA955X
- select HW_HAS_PCI
- select PCI_AR724X if PCI
+config PCI_AR71XX
+ bool "PCI support for AR7100 type SoCs"
+ depends on PCI
def_bool n
config PCI_AR724X
- def_bool n
-
-config ATH79_DEV_GPIO_BUTTONS
- def_bool n
-
-config ATH79_DEV_LEDS_GPIO
- def_bool n
-
-config ATH79_DEV_SPI
- def_bool n
-
-config ATH79_DEV_USB
- def_bool n
-
-config ATH79_DEV_WMAC
- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
+ bool "PCI support for AR724x type SoCs"
+ depends on PCI
def_bool n
endif
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o
ops-bcm63xx.o
obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
-obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
+obj-$(CONFIG_PCI_AR71XX) += pci-ar71xx.o
obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
#

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@ -1,73 +0,0 @@
From c4e197bbcecc7233aa9e553e7047fa50e4e1fe77 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Mon, 25 Jun 2018 15:52:34 +0200
Subject: [PATCH 33/33] spi: ath79: drop pdata support
The target is being converted to pure OF. We can therefore drop all of the
platform data code from the driver.
Cc: linux-spi@vger.kernel.org
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/include/asm/mach-ath79/ath79_spi_platform.h | 19 -------------------
drivers/spi/spi-ath79.c | 8 --------
2 files changed, 27 deletions(-)
delete mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller
- *
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _ATH79_SPI_PLATFORM_H
-#define _ATH79_SPI_PLATFORM_H
-
-struct ath79_spi_platform_data {
- unsigned bus_num;
- unsigned num_chipselect;
-};
-
-#endif /* _ATH79_SPI_PLATFORM_H */
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -26,7 +26,6 @@
#include <linux/err.h>
#include <asm/mach-ath79/ar71xx_regs.h>
-#include <asm/mach-ath79/ath79_spi_platform.h>
#define DRV_NAME "ath79-spi"
@@ -208,7 +207,6 @@ static int ath79_spi_probe(struct platfo
{
struct spi_master *master;
struct ath79_spi *sp;
- struct ath79_spi_platform_data *pdata;
struct resource *r;
unsigned long rate;
int ret;
@@ -223,15 +221,9 @@ static int ath79_spi_probe(struct platfo
master->dev.of_node = pdev->dev.of_node;
platform_set_drvdata(pdev, sp);
- pdata = dev_get_platdata(&pdev->dev);
-
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
master->setup = ath79_spi_setup;
master->cleanup = ath79_spi_cleanup;
- if (pdata) {
- master->bus_num = pdata->bus_num;
- master->num_chipselect = pdata->num_chipselect;
- }
sp->bitbang.master = master;
sp->bitbang.chipselect = ath79_spi_chipselect;

View File

@ -1,27 +0,0 @@
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -34,11 +34,13 @@ EXPORT_SYMBOL_GPL(ath79_ddr_freq);
enum ath79_soc_type ath79_soc;
unsigned int ath79_soc_rev;
+EXPORT_SYMBOL_GPL(ath79_soc_rev);
void __iomem *ath79_pll_base;
void __iomem *ath79_reset_base;
EXPORT_SYMBOL_GPL(ath79_reset_base);
-static void __iomem *ath79_ddr_base;
+void __iomem *ath79_ddr_base;
+EXPORT_SYMBOL_GPL(ath79_ddr_base);
static void __iomem *ath79_ddr_wb_flush_base;
static void __iomem *ath79_ddr_pci_win_base;
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -152,6 +152,7 @@ void ath79_ddr_wb_flush(unsigned int reg
void ath79_ddr_set_pci_windows(void);
extern void __iomem *ath79_pll_base;
+extern void __iomem *ath79_ddr_base;
extern void __iomem *ath79_reset_base;
static inline void ath79_pll_wr(unsigned reg, u32 val)

View File

@ -1,165 +0,0 @@
From 4267880319bc1a2270d352e0ded6d6386242a7ef Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 12 Aug 2014 20:49:27 +0200
Subject: [PATCH 24/53] GPIO: add named gpio exports
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++
drivers/gpio/gpiolib-sysfs.c | 10 +++++-
include/asm-generic/gpio.h | 6 ++++
include/linux/gpio/consumer.h | 8 +++++
4 files changed, 91 insertions(+), 1 deletion(-)
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -23,6 +23,8 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/slab.h>
#include <linux/gpio/machine.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
#include "gpiolib.h"
@@ -660,3 +662,68 @@ void of_gpiochip_remove(struct gpio_chip
gpiochip_remove_pin_ranges(chip);
of_node_put(chip->of_node);
}
+
+static struct of_device_id gpio_export_ids[] = {
+ { .compatible = "gpio-export" },
+ { /* sentinel */ }
+};
+
+static int of_gpio_export_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *cnp;
+ u32 val;
+ int nb = 0;
+
+ for_each_child_of_node(np, cnp) {
+ const char *name = NULL;
+ int gpio;
+ bool dmc;
+ int max_gpio = 1;
+ int i;
+
+ of_property_read_string(cnp, "gpio-export,name", &name);
+
+ if (!name)
+ max_gpio = of_gpio_count(cnp);
+
+ for (i = 0; i < max_gpio; i++) {
+ unsigned flags = 0;
+ enum of_gpio_flags of_flags;
+
+ gpio = of_get_gpio_flags(cnp, i, &of_flags);
+ if (!gpio_is_valid(gpio))
+ return gpio;
+
+ if (of_flags == OF_GPIO_ACTIVE_LOW)
+ flags |= GPIOF_ACTIVE_LOW;
+
+ if (!of_property_read_u32(cnp, "gpio-export,output", &val))
+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
+ else
+ flags |= GPIOF_IN;
+
+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
+ continue;
+
+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
+ gpio_export_with_name(gpio, dmc, name);
+ nb++;
+ }
+ }
+
+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
+
+ return 0;
+}
+
+static struct platform_driver gpio_export_driver = {
+ .driver = {
+ .name = "gpio-export",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(gpio_export_ids),
+ },
+ .probe = of_gpio_export_probe,
+};
+
+module_platform_driver(gpio_export_driver);
--- a/drivers/gpio/gpiolib-sysfs.c
+++ b/drivers/gpio/gpiolib-sysfs.c
@@ -568,7 +568,7 @@ static struct class gpio_class = {
*
* Returns zero on success, else an error.
*/
-int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
{
struct gpio_chip *chip;
struct gpio_device *gdev;
@@ -630,6 +630,8 @@ int gpiod_export(struct gpio_desc *desc,
offset = gpio_chip_hwgpio(desc);
if (chip->names && chip->names[offset])
ioname = chip->names[offset];
+ if (name)
+ ioname = name;
dev = device_create_with_groups(&gpio_class, &gdev->dev,
MKDEV(0, 0), data, gpio_groups,
@@ -651,6 +653,12 @@ err_unlock:
gpiod_dbg(desc, "%s: status %d\n", __func__, status);
return status;
}
+EXPORT_SYMBOL_GPL(__gpiod_export);
+
+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
+{
+ return __gpiod_export(desc, direction_may_change, NULL);
+}
EXPORT_SYMBOL_GPL(gpiod_export);
static int match_export(struct device *dev, const void *desc)
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g
return gpiod_export(gpio_to_desc(gpio), direction_may_change);
}
+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
+{
+ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
+}
+
static inline int gpio_export_link(struct device *dev, const char *name,
unsigned gpio)
{
--- a/include/linux/gpio/consumer.h
+++ b/include/linux/gpio/consumer.h
@@ -533,6 +533,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_
#if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
int gpiod_export_link(struct device *dev, const char *name,
struct gpio_desc *desc);
@@ -540,6 +541,13 @@ void gpiod_unexport(struct gpio_desc *de
#else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
+static inline int _gpiod_export(struct gpio_desc *desc,
+ bool direction_may_change,
+ const char *name)
+{
+ return -ENOSYS;
+}
+
static inline int gpiod_export(struct gpio_desc *desc,
bool direction_may_change)
{

View File

@ -1,139 +0,0 @@
--- a/arch/mips/pci/pci-ar71xx.c
+++ b/arch/mips/pci/pci-ar71xx.c
@@ -54,11 +54,9 @@
struct ar71xx_pci_controller {
struct device_node *np;
void __iomem *cfg_base;
- int irq;
struct pci_controller pci_ctrl;
struct resource io_res;
struct resource mem_res;
- struct irq_domain *domain;
};
/* Byte lane enable bits */
@@ -230,104 +228,6 @@ static struct pci_ops ar71xx_pci_ops = {
.write = ar71xx_pci_write_config,
};
-static void ar71xx_pci_irq_handler(struct irq_desc *desc)
-{
- void __iomem *base = ath79_reset_base;
- struct irq_chip *chip = irq_desc_get_chip(desc);
- struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
- u32 pending;
-
- chained_irq_enter(chip, desc);
- pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-
- if (pending & AR71XX_PCI_INT_DEV0)
- generic_handle_irq(irq_linear_revmap(apc->domain, 1));
-
- else if (pending & AR71XX_PCI_INT_DEV1)
- generic_handle_irq(irq_linear_revmap(apc->domain, 2));
-
- else if (pending & AR71XX_PCI_INT_DEV2)
- generic_handle_irq(irq_linear_revmap(apc->domain, 3));
-
- else if (pending & AR71XX_PCI_INT_CORE)
- generic_handle_irq(irq_linear_revmap(apc->domain, 4));
-
- else
- spurious_interrupt();
- chained_irq_exit(chip, desc);
-}
-
-static void ar71xx_pci_irq_unmask(struct irq_data *d)
-{
- struct ar71xx_pci_controller *apc;
- unsigned int irq;
- void __iomem *base = ath79_reset_base;
- u32 t;
-
- apc = irq_data_get_irq_chip_data(d);
- irq = irq_linear_revmap(apc->domain, d->irq);
-
- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
- __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-
- /* flush write */
- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-}
-
-static void ar71xx_pci_irq_mask(struct irq_data *d)
-{
- struct ar71xx_pci_controller *apc;
- unsigned int irq;
- void __iomem *base = ath79_reset_base;
- u32 t;
-
- apc = irq_data_get_irq_chip_data(d);
- irq = irq_linear_revmap(apc->domain, d->irq);
-
- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
- __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-
- /* flush write */
- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-}
-
-static struct irq_chip ar71xx_pci_irq_chip = {
- .name = "AR71XX PCI",
- .irq_mask = ar71xx_pci_irq_mask,
- .irq_unmask = ar71xx_pci_irq_unmask,
- .irq_mask_ack = ar71xx_pci_irq_mask,
-};
-
-static int ar71xx_pci_irq_map(struct irq_domain *d,
- unsigned int irq, irq_hw_number_t hw)
-{
- struct ar71xx_pci_controller *apc = d->host_data;
-
- irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
- irq_set_chip_data(irq, apc);
-
- return 0;
-}
-
-static const struct irq_domain_ops ar71xx_pci_domain_ops = {
- .xlate = irq_domain_xlate_onecell,
- .map = ar71xx_pci_irq_map,
-};
-
-static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
-{
- void __iomem *base = ath79_reset_base;
-
- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
-
- apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
- &ar71xx_pci_domain_ops, apc);
- irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
- apc);
-}
-
static void ar71xx_pci_reset(void)
{
ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
@@ -361,10 +261,6 @@ static int ar71xx_pci_probe(struct platf
if (IS_ERR(apc->cfg_base))
return PTR_ERR(apc->cfg_base);
- apc->irq = platform_get_irq(pdev, 0);
- if (apc->irq < 0)
- return -EINVAL;
-
ar71xx_pci_reset();
/* setup COMMAND register */
@@ -375,8 +271,6 @@ static int ar71xx_pci_probe(struct platf
/* clear bus errors */
ar71xx_pci_check_error(apc, 1);
- ar71xx_pci_irq_init(apc);
-
apc->np = pdev->dev.of_node;
apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
apc->pci_ctrl.mem_resource = &apc->mem_res;

View File

@ -1,21 +0,0 @@
commit f3ffac90bc7266b7d917616f3233f58e8c08a196
Author: Christian Lamparter <chunkeey@gmail.com>
Date: Fri Aug 10 23:24:47 2018 +0200
ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -1229,6 +1229,10 @@
#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
+#define AR934X_ETH_CFG_TXD_DELAY_MASK 0x3
+#define AR934X_ETH_CFG_TXD_DELAY_SHIFT 18
+#define AR934X_ETH_CFG_TXE_DELAY_MASK 0x3
+#define AR934X_ETH_CFG_TXE_DELAY_SHIFT 20
/*
* QCA953X GMAC Interface

View File

@ -1,90 +0,0 @@
From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Mon, 18 Mar 2019 00:54:06 +0100
Subject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers
This adds missing GMAC register definitions for the Qualcomm Atheros
QCA955X series MIPS SoCs.
They originate from the platforms U-Boot code and the AVM FRITZ!WLAN
Repeater 450E's GPL tarball.
Signed-off-by: David Bauer <mail@david-bauer.net>
---
.../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -1249,7 +1249,12 @@
*/
#define QCA955X_GMAC_REG_ETH_CFG 0x00
+#define QCA955X_GMAC_REG_SGMII_RESET 0x14
#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
+#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c
+#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20
+#define QCA955X_GMAC_REG_SGMII_CONFIG 0x34
+#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58
#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
@@ -1271,9 +1276,58 @@
#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
+#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0
+#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0)
+#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1)
+#define QCA955X_SGMII_RESET_RX_125M_N BIT(2)
+#define QCA955X_SGMII_RESET_TX_125M_N BIT(3)
+#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4)
+
#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
+
+#define QCA955X_MR_AN_CONTROL_SPEED_SEL1 BIT(6)
+#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE BIT(8)
+#define QCA955X_MR_AN_CONTROL_RESTART_AN BIT(9)
+#define QCA955X_MR_AN_CONTROL_POWER_DOWN BIT(11)
+#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12)
+#define QCA955X_MR_AN_CONTROL_SPEED_SEL0 BIT(13)
+#define QCA955X_MR_AN_CONTROL_LOOPBACK BIT(14)
+#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15)
+
+#define QCA955X_MR_AN_STATUS_EXT_CAP BIT(0)
+#define QCA955X_MR_AN_STATUS_LINK_UP BIT(2)
+#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3)
+#define QCA955X_MR_AN_STATUS_REMOTE_FAULT BIT(4)
+#define QCA955X_MR_AN_STATUS_AN_COMPLETE BIT(5)
+#define QCA955X_MR_AN_STATUS_NO_PREAMBLE BIT(6)
+#define QCA955X_MR_AN_STATUS_BASE_PAGE BIT(7)
+
+#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
+#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
+#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3)
+#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4)
+#define QCA955X_SGMII_CONFIG_FORCE_SPEED BIT(5)
+#define QCA955X_SGMII_CONFIG_SPEED_SHIFT 6
+#define QCA955X_SGMII_CONFIG_SPEED_MASK 0xc0
+#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8)
+#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9)
+#define QCA955X_SGMII_CONFIG_MDIO_ENABLE BIT(10)
+#define QCA955X_SGMII_CONFIG_MDIO_PULSE BIT(11)
+#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE BIT(12)
+#define QCA955X_SGMII_CONFIG_PRBS_ENABLE BIT(13)
+#define QCA955X_SGMII_CONFIG_BERT_ENABLE BIT(14)
+
+#define QCA955X_SGMII_DEBUG_TX_STATE_MASK 0xff
+#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT 0
+#define QCA955X_SGMII_DEBUG_RX_STATE_MASK 0xff00
+#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT 8
+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff0000
+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16
+#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK 0xf000000
+#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT 24
+
/*
* QCA956X GMAC Interface
*/

View File

@ -1,27 +0,0 @@
Until upstream commit 6d4cd041f0af("net: phy: at803x: disable delay
only for RGMII mode"), delays were not disabled on driver probe
for the Atheros AR803x PHYs, although the RX delay is enabled on
soft and hard reset.
In addition, the TX delay setting is retained on soft-reset.
This patch disables both delays on config init to align the behavior
with kernel 5.1 and higher. It can be safely dropped with kernel 5.1.
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -279,6 +279,14 @@ static int at803x_config_init(struct phy
if (ret < 0)
return ret;
+ /* Disable RX delay */
+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
+ AT803X_DEBUG_RX_CLK_DLY_EN, 0);
+
+ /* Disable TX delay */
+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
+ AT803X_DEBUG_TX_CLK_DLY_EN, 0);
+
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
ret = at803x_enable_rx_delay(phydev);

View File

@ -1,52 +0,0 @@
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7
[ATH79_CLK_AHB] = "ahb",
[ATH79_CLK_REF] = "ref",
[ATH79_CLK_MDIO] = "mdio",
+ [ATH79_CLK_UART1] = "uart1",
};
static const char * __init ath79_clk_name(int type)
@@ -346,6 +347,9 @@ static void __init ar934x_clocks_init(vo
if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)
+ ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);
+
iounmap(dpll_base);
}
@@ -651,6 +655,9 @@ static void __init ath79_clocks_init_dt(
if (!clks[ATH79_CLK_MDIO])
clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
+ if (!clks[ATH79_CLK_UART1])
+ clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];
+
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
pr_err("%pOF: could not register clk provider\n", np);
goto err_iounmap;
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -351,6 +351,7 @@
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL BIT(7)
#define QCA953X_PLL_CPU_CONFIG_REG 0x00
#define QCA953X_PLL_DDR_CONFIG_REG 0x04
--- a/include/dt-bindings/clock/ath79-clk.h
+++ b/include/dt-bindings/clock/ath79-clk.h
@@ -15,7 +15,8 @@
#define ATH79_CLK_AHB 2
#define ATH79_CLK_REF 3
#define ATH79_CLK_MDIO 4
+#define ATH79_CLK_UART1 5
-#define ATH79_CLK_END 5
+#define ATH79_CLK_END 6
#endif /* __DT_BINDINGS_ATH79_CLK_H */

View File

@ -1,18 +0,0 @@
HACK: register the GPIO driver earlier to ensure that gpio_request calls
from mach files succeed.
--- a/drivers/gpio/gpio-ath79.c
+++ b/drivers/gpio/gpio-ath79.c
@@ -325,7 +325,11 @@ static struct platform_driver ath79_gpio
.remove = ath79_gpio_remove,
};
-module_platform_driver(ath79_gpio_driver);
+static int __init ath79_gpio_init(void)
+{
+ return platform_driver_register(&ath79_gpio_driver);
+}
+postcore_initcall(ath79_gpio_init);
MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
MODULE_LICENSE("GPL v2");

View File

@ -1,61 +0,0 @@
From 7945f929f1a77a1c8887a97ca07f87626858ff42 Mon Sep 17 00:00:00 2001
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Date: Wed, 20 Feb 2019 11:12:39 +0000
Subject: [PATCH] drivers: provide devm_platform_ioremap_resource()
There are currently 1200+ instances of using platform_get_resource()
and devm_ioremap_resource() together in the kernel tree.
This patch wraps these two calls in a single helper. Thanks to that
we don't have to declare a local variable for struct resource * and can
omit the redundant argument for resource type. We also have one
function call less.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/base/platform.c | 18 ++++++++++++++++++
include/linux/platform_device.h | 3 +++
2 files changed, 21 insertions(+)
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -81,6 +81,24 @@ struct resource *platform_get_resource(s
EXPORT_SYMBOL_GPL(platform_get_resource);
/**
+ * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform
+ * device
+ *
+ * @pdev: platform device to use both for memory resource lookup as well as
+ * resource managemend
+ * @index: resource index
+ */
+void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev,
+ unsigned int index)
+{
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, index);
+ return devm_ioremap_resource(&pdev->dev, res);
+}
+EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource);
+
+/**
* platform_get_irq - get an IRQ for a device
* @dev: platform device
* @num: IRQ number index
--- a/include/linux/platform_device.h
+++ b/include/linux/platform_device.h
@@ -51,6 +51,9 @@ extern struct device platform_bus;
extern void arch_setup_pdev_archdata(struct platform_device *);
extern struct resource *platform_get_resource(struct platform_device *,
unsigned int, unsigned int);
+extern void __iomem *
+devm_platform_ioremap_resource(struct platform_device *pdev,
+ unsigned int index);
extern int platform_get_irq(struct platform_device *, unsigned int);
extern int platform_irq_count(struct platform_device *);
extern struct resource *platform_get_resource_byname(struct platform_device *,

View File

@ -1,283 +0,0 @@
From 7e161c423a232ef7ddf6c11b09ebe471dd5a23cf Mon Sep 17 00:00:00 2001
From: Chuanhong Guo <gch981213@gmail.com>
Date: Wed, 5 Feb 2020 18:25:37 +0800
Subject: [PATCH v4 1/2] spi: add driver for ar934x spi controller
This patch adds driver for SPI controller found in Qualcomm Atheros
AR934x/QCA95xx SoCs.
This controller is a superset of the already supported qca,ar7100-spi.
Besides the bit-bang mode in spi-ath79.c, this new controller added
a new "shift register" mode, allowing faster spi operations.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
drivers/spi/Kconfig | 7 ++
drivers/spi/Makefile | 1 +
drivers/spi/spi-ar934x.c | 235 +++++++++++++++++++++++++++++++++++++++
3 files changed, 243 insertions(+)
create mode 100644 drivers/spi/spi-ar934x.c
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -61,6 +61,13 @@ config SPI_ALTERA
help
This is the driver for the Altera SPI Controller.
+config SPI_AR934X
+ tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
+ depends on ATH79 || COMPILE_TEST
+ help
+ This enables support for the SPI controller present on the
+ Qualcomm Atheros AR934X/QCA95XX SoCs.
+
config SPI_ATH79
tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
depends on ATH79 && GPIOLIB
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-
# SPI master controller drivers (bus)
obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
+obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
--- /dev/null
+++ b/drivers/spi/spi-ar934x.c
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
+//
+// Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
+//
+// Based on spi-mt7621.c:
+// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
+// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
+// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/spi/spi.h>
+
+#define DRIVER_NAME "spi-ar934x"
+
+#define AR934X_SPI_REG_FS 0x00
+#define AR934X_SPI_ENABLE BIT(0)
+
+#define AR934X_SPI_REG_IOC 0x08
+#define AR934X_SPI_IOC_INITVAL 0x70000
+
+#define AR934X_SPI_REG_CTRL 0x04
+#define AR934X_SPI_CLK_MASK GENMASK(5, 0)
+
+#define AR934X_SPI_DATAOUT 0x10
+
+#define AR934X_SPI_REG_SHIFT_CTRL 0x14
+#define AR934X_SPI_SHIFT_EN BIT(31)
+#define AR934X_SPI_SHIFT_CS(n) BIT(28 + (n))
+#define AR934X_SPI_SHIFT_TERM 26
+#define AR934X_SPI_SHIFT_VAL(cs, term, count) \
+ (AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) | \
+ (term) << AR934X_SPI_SHIFT_TERM | (count))
+
+#define AR934X_SPI_DATAIN 0x18
+
+struct ar934x_spi {
+ struct spi_controller *ctlr;
+ void __iomem *base;
+ struct clk *clk;
+ unsigned int clk_freq;
+};
+
+static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
+{
+ int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
+
+ if (div < 0)
+ return 0;
+ else if (div > AR934X_SPI_CLK_MASK)
+ return -EINVAL;
+ else
+ return div;
+}
+
+static int ar934x_spi_setup(struct spi_device *spi)
+{
+ struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);
+
+ if ((spi->max_speed_hz == 0) ||
+ (spi->max_speed_hz > (sp->clk_freq / 2))) {
+ spi->max_speed_hz = sp->clk_freq / 2;
+ } else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
+ dev_err(&spi->dev, "spi clock is too low\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ar934x_spi_transfer_one_message(struct spi_controller *master,
+ struct spi_message *m)
+{
+ struct ar934x_spi *sp = spi_controller_get_devdata(master);
+ struct spi_transfer *t = NULL;
+ struct spi_device *spi = m->spi;
+ unsigned long trx_done, trx_cur;
+ int stat = 0;
+ u8 term = 0;
+ int div, i;
+ u32 reg;
+ const u8 *tx_buf;
+ u8 *buf;
+
+ m->actual_length = 0;
+ list_for_each_entry(t, &m->transfers, transfer_list) {
+ if (t->speed_hz)
+ div = ar934x_spi_clk_div(sp, t->speed_hz);
+ else
+ div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
+ if (div < 0) {
+ stat = -EIO;
+ goto msg_done;
+ }
+
+ reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
+ reg &= ~AR934X_SPI_CLK_MASK;
+ reg |= div;
+ iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
+ iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
+
+ for (trx_done = 0; trx_done < t->len; trx_done += 4) {
+ trx_cur = t->len - trx_done;
+ if (trx_cur > 4)
+ trx_cur = 4;
+ else if (list_is_last(&t->transfer_list, &m->transfers))
+ term = 1;
+
+ if (t->tx_buf) {
+ tx_buf = t->tx_buf + trx_done;
+ reg = tx_buf[0];
+ for (i = 1; i < trx_cur; i++)
+ reg = reg << 8 | tx_buf[i];
+ iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
+ }
+
+ reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
+ trx_cur * 8);
+ iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
+ stat = readl_poll_timeout(
+ sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
+ !(reg & AR934X_SPI_SHIFT_EN), 0, 5);
+ if (stat < 0)
+ goto msg_done;
+
+ if (t->rx_buf) {
+ reg = ioread32(sp->base + AR934X_SPI_DATAIN);
+ buf = t->rx_buf + trx_done;
+ for (i = 0; i < trx_cur; i++) {
+ buf[trx_cur - i - 1] = reg & 0xff;
+ reg >>= 8;
+ }
+ }
+ }
+ m->actual_length += t->len;
+ }
+
+msg_done:
+ m->status = stat;
+ spi_finalize_current_message(master);
+
+ return 0;
+}
+
+static const struct of_device_id ar934x_spi_match[] = {
+ { .compatible = "qca,ar934x-spi" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ar934x_spi_match);
+
+static int ar934x_spi_probe(struct platform_device *pdev)
+{
+ struct spi_controller *ctlr;
+ struct ar934x_spi *sp;
+ void __iomem *base;
+ struct clk *clk;
+ int ret;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "failed to get clock\n");
+ return PTR_ERR(clk);
+ }
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ return ret;
+
+ ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
+ if (!ctlr) {
+ dev_info(&pdev->dev, "failed to allocate spi controller\n");
+ return -ENOMEM;
+ }
+
+ /* disable flash mapping and expose spi controller registers */
+ iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
+ /* restore pins to default state: CSn=1 DO=CLK=0 */
+ iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
+
+ ctlr->mode_bits = SPI_LSB_FIRST;
+ ctlr->setup = ar934x_spi_setup;
+ ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
+ ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
+ ctlr->dev.of_node = pdev->dev.of_node;
+ ctlr->num_chipselect = 3;
+
+ dev_set_drvdata(&pdev->dev, ctlr);
+
+ sp = spi_controller_get_devdata(ctlr);
+ sp->base = base;
+ sp->clk = clk;
+ sp->clk_freq = clk_get_rate(clk);
+ sp->ctlr = ctlr;
+
+ return devm_spi_register_controller(&pdev->dev, ctlr);
+}
+
+static int ar934x_spi_remove(struct platform_device *pdev)
+{
+ struct spi_controller *ctlr;
+ struct ar934x_spi *sp;
+
+ ctlr = dev_get_drvdata(&pdev->dev);
+ sp = spi_controller_get_devdata(ctlr);
+
+ clk_disable_unprepare(sp->clk);
+
+ return 0;
+}
+
+static struct platform_driver ar934x_spi_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = ar934x_spi_match,
+ },
+ .probe = ar934x_spi_probe,
+ .remove = ar934x_spi_remove,
+};
+
+module_platform_driver(ar934x_spi_driver);
+
+MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
+MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);

View File

@ -1,64 +0,0 @@
From patchwork Fri Feb 7 09:53:35 2020
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
X-Patchwork-Id: 1190470
Date: Fri, 7 Feb 2020 11:53:35 +0200
From: Daniel Golle <daniel@makrotopia.org>
To: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jslaby@suse.com>,
Chuanhong Guo <gch981213@gmail.com>,
Eitan Cohen <eitan@neot-semadar.com>,
Ori Gofen <origofen@gmail.com>
Subject: [PATCH] serial: ar933x_uart: set UART_CS_{RX,TX}_READY_ORIDE
Message-ID: <20200207095335.GA179836@makrotopia.org>
MIME-Version: 1.0
Content-Disposition: inline
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
On AR934x this UART is usually not initialized by the bootloader
as it is only used as a secondary serial port while the primary
UART is a newly introduced NS16550-compatible.
In order to make use of the ar933x-uart on AR934x without RTS/CTS
hardware flow control, one needs to set the
UART_CS_{RX,TX}_READY_ORIDE bits as other than on AR933x where this
UART is used as primary/console, the bootloader on AR934x typically
doesn't set those bits.
Setting them explicitely on AR933x should not do any harm, so just
set them unconditionally.
Tested-by: Chuanhong Guo <gch981213@gmail.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/tty/serial/ar933x_uart.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/drivers/tty/serial/ar933x_uart.c
+++ b/drivers/tty/serial/ar933x_uart.c
@@ -290,6 +290,10 @@ static void ar933x_uart_set_termios(stru
ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
+ /* enable RX and TX ready overide */
+ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+ AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
+
/* reenable the UART */
ar933x_uart_rmw(up, AR933X_UART_CS_REG,
AR933X_UART_CS_IF_MODE_M << AR933X_UART_CS_IF_MODE_S,
@@ -424,6 +428,10 @@ static int ar933x_uart_startup(struct ua
/* enable RX and TX ready overide */
ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+ AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
+
+ /* enable RX and TX ready overide */
+ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
/* Enable RX interrupts */

View File

@ -1,267 +0,0 @@
From patchwork Fri Feb 21 21:23:31 2020
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
X-Patchwork-Id: 1198835
Date: Fri, 21 Feb 2020 22:23:31 +0100
From: Daniel Golle <daniel@makrotopia.org>
To: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jslaby@suse.com>, Petr =?utf-8?q?=C5=A0tetiar?= <ynezz@true.cz>,
Chuanhong Guo <gch981213@gmail.com>, Piotr Dymacz <pepe2k@gmail.com>
Subject: [PATCH v2] serial: ar933x_uart: add RS485 support
Message-ID: <20200221212331.GA21467@makrotopia.org>
MIME-Version: 1.0
Content-Disposition: inline
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
Emulate half-duplex operation and use mctrl_gpio to add support for
RS485 tranceiver with transmit/receive switch hooked to RTS GPIO line.
This is needed to make use of the RS485 port found on Teltonika RUT955.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
v2: use bool to indicate ongoing half-duplex send, use it afterwards
to decide whether we've just been in a send operation.
drivers/tty/serial/Kconfig | 1 +
drivers/tty/serial/ar933x_uart.c | 113 +++++++++++++++++++++++++++++--
2 files changed, 108 insertions(+), 6 deletions(-)
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1296,6 +1296,7 @@ config SERIAL_AR933X
tristate "AR933X serial port support"
depends on HAVE_CLK && ATH79
select SERIAL_CORE
+ select SERIAL_MCTRL_GPIO if GPIOLIB
help
If you have an Atheros AR933X SOC based board and want to use the
built-in UART of the SoC, say Y to this option.
--- a/drivers/tty/serial/ar933x_uart.c
+++ b/drivers/tty/serial/ar933x_uart.c
@@ -13,6 +13,7 @@
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_platform.h>
@@ -29,6 +30,8 @@
#include <asm/mach-ath79/ar933x_uart.h>
+#include "serial_mctrl_gpio.h"
+
#define DRIVER_NAME "ar933x-uart"
#define AR933X_UART_MAX_SCALE 0xff
@@ -47,6 +50,8 @@ struct ar933x_uart_port {
unsigned int min_baud;
unsigned int max_baud;
struct clk *clk;
+ struct mctrl_gpios *gpios;
+ struct gpio_desc *rts_gpiod;
};
static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up,
@@ -100,6 +105,18 @@ static inline void ar933x_uart_stop_tx_i
ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
}
+static inline void ar933x_uart_start_rx_interrupt(struct ar933x_uart_port *up)
+{
+ up->ier |= AR933X_UART_INT_RX_VALID;
+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+}
+
+static inline void ar933x_uart_stop_rx_interrupt(struct ar933x_uart_port *up)
+{
+ up->ier &= ~AR933X_UART_INT_RX_VALID;
+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+}
+
static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch)
{
unsigned int rdata;
@@ -125,11 +142,21 @@ static unsigned int ar933x_uart_tx_empty
static unsigned int ar933x_uart_get_mctrl(struct uart_port *port)
{
- return TIOCM_CAR;
+ struct ar933x_uart_port *up =
+ container_of(port, struct ar933x_uart_port, port);
+ int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
+
+ mctrl_gpio_get(up->gpios, &ret);
+
+ return ret;
}
static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
+ struct ar933x_uart_port *up =
+ container_of(port, struct ar933x_uart_port, port);
+
+ mctrl_gpio_set(up->gpios, mctrl);
}
static void ar933x_uart_start_tx(struct uart_port *port)
@@ -140,6 +167,37 @@ static void ar933x_uart_start_tx(struct
ar933x_uart_start_tx_interrupt(up);
}
+static void ar933x_uart_wait_tx_complete(struct ar933x_uart_port *up)
+{
+ unsigned int status;
+ unsigned int timeout = 60000;
+
+ /* Wait up to 60ms for the character(s) to be sent. */
+ do {
+ status = ar933x_uart_read(up, AR933X_UART_CS_REG);
+ if (--timeout == 0)
+ break;
+ udelay(1);
+ } while (status & AR933X_UART_CS_TX_BUSY);
+
+ if (timeout == 0)
+ dev_err(up->port.dev, "waiting for TX timed out\n");
+}
+
+static void ar933x_uart_rx_flush(struct ar933x_uart_port *up)
+{
+ unsigned int status;
+
+ /* clear RX_VALID interrupt */
+ ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_RX_VALID);
+
+ /* remove characters from the RX FIFO */
+ do {
+ ar933x_uart_write(up, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR);
+ status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+ } while (status & AR933X_UART_DATA_RX_CSR);
+}
+
static void ar933x_uart_stop_tx(struct uart_port *port)
{
struct ar933x_uart_port *up =
@@ -153,8 +211,7 @@ static void ar933x_uart_stop_rx(struct u
struct ar933x_uart_port *up =
container_of(port, struct ar933x_uart_port, port);
- up->ier &= ~AR933X_UART_INT_RX_VALID;
- ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+ ar933x_uart_stop_rx_interrupt(up);
}
static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
@@ -340,11 +397,20 @@ static void ar933x_uart_rx_chars(struct
static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
{
struct circ_buf *xmit = &up->port.state->xmit;
+ struct serial_rs485 *rs485conf = &up->port.rs485;
int count;
+ bool half_duplex_send = false;
if (uart_tx_stopped(&up->port))
return;
+ if ((rs485conf->flags & SER_RS485_ENABLED) &&
+ (up->port.x_char || !uart_circ_empty(xmit))) {
+ ar933x_uart_stop_rx_interrupt(up);
+ gpiod_set_value(up->rts_gpiod, !!(rs485conf->flags & SER_RS485_RTS_ON_SEND));
+ half_duplex_send = true;
+ }
+
count = up->port.fifosize;
do {
unsigned int rdata;
@@ -372,8 +438,14 @@ static void ar933x_uart_tx_chars(struct
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&up->port);
- if (!uart_circ_empty(xmit))
+ if (!uart_circ_empty(xmit)) {
ar933x_uart_start_tx_interrupt(up);
+ } else if (half_duplex_send) {
+ ar933x_uart_wait_tx_complete(up);
+ ar933x_uart_rx_flush(up);
+ ar933x_uart_start_rx_interrupt(up);
+ gpiod_set_value(up->rts_gpiod, !!(rs485conf->flags & SER_RS485_RTS_AFTER_SEND));
+ }
}
static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
@@ -435,8 +507,7 @@ static int ar933x_uart_startup(struct ua
AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
/* Enable RX interrupts */
- up->ier = AR933X_UART_INT_RX_VALID;
- ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+ ar933x_uart_start_rx_interrupt(up);
spin_unlock_irqrestore(&up->port.lock, flags);
@@ -519,6 +590,21 @@ static const struct uart_ops ar933x_uart
.verify_port = ar933x_uart_verify_port,
};
+static int ar933x_config_rs485(struct uart_port *port,
+ struct serial_rs485 *rs485conf)
+{
+ struct ar933x_uart_port *up =
+ container_of(port, struct ar933x_uart_port, port);
+
+ if ((rs485conf->flags & SER_RS485_ENABLED) &&
+ !up->rts_gpiod) {
+ dev_err(port->dev, "RS485 needs rts-gpio\n");
+ return 1;
+ }
+ port->rs485 = *rs485conf;
+ return 0;
+}
+
#ifdef CONFIG_SERIAL_AR933X_CONSOLE
static struct ar933x_uart_port *
ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS];
@@ -688,6 +774,8 @@ static int ar933x_uart_probe(struct plat
goto err_disable_clk;
}
+ uart_get_rs485_mode(&pdev->dev, &port->rs485);
+
port->mapbase = mem_res->start;
port->line = id;
port->irq = irq_res->start;
@@ -698,6 +786,7 @@ static int ar933x_uart_probe(struct plat
port->regshift = 2;
port->fifosize = AR933X_UART_FIFO_SIZE;
port->ops = &ar933x_uart_ops;
+ port->rs485_config = ar933x_config_rs485;
baud = ar933x_uart_get_baud(port->uartclk, AR933X_UART_MAX_SCALE, 1);
up->min_baud = max_t(unsigned int, baud, AR933X_UART_MIN_BAUD);
@@ -705,6 +794,18 @@ static int ar933x_uart_probe(struct plat
baud = ar933x_uart_get_baud(port->uartclk, 0, AR933X_UART_MAX_STEP);
up->max_baud = min_t(unsigned int, baud, AR933X_UART_MAX_BAUD);
+ up->gpios = mctrl_gpio_init(port, 0);
+ if (IS_ERR(up->gpios) && PTR_ERR(up->gpios) != -ENOSYS)
+ return PTR_ERR(up->gpios);
+
+ up->rts_gpiod = mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS);
+
+ if ((port->rs485.flags & SER_RS485_ENABLED) &&
+ !up->rts_gpiod) {
+ dev_err(&pdev->dev, "lacking rts-gpio, disabling RS485\n");
+ port->rs485.flags &= ~SER_RS485_ENABLED;
+ }
+
#ifdef CONFIG_SERIAL_AR933X_CONSOLE
ar933x_console_ports[up->port.line] = up;
#endif

View File

@ -1,130 +0,0 @@
From: David Bauer <mail@david-bauer.net>
Date: Sat, 11 Apr 2020 14:03:12 +0200
Subject: MIPS: pci-ar724x: add QCA9550 reset sequence
The QCA9550 family of SoCs have a slightly different reset
sequence compared to older chips.
Normally the bootloader performs this sequence, however
some bootloader implementation expect the operating system
to clear the reset.
Also get the resets from OF to support handling of the second
PCIe root-complex on the QCA9558.
Signed-off-by: David Bauer <mail@david-bauer.net>
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -394,6 +394,7 @@
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
+#define QCA955X_PLL_PCIE_CONFIG_REG 0x0c
#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
@@ -479,6 +480,9 @@
#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+#define QCA955X_PLL_PCIE_CONFIG_PLL_PWD BIT(30)
+#define QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS BIT(16)
+
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7)
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -11,6 +11,7 @@
#include <linux/irq.h>
#include <linux/pci.h>
+#include <linux/reset.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
@@ -58,6 +59,9 @@ struct ar724x_pci_controller {
struct irq_domain *domain;
struct resource io_res;
struct resource mem_res;
+
+ struct reset_control *hc_reset;
+ struct reset_control *phy_reset;
};
static struct irq_chip ar724x_pci_irq_chip;
@@ -343,18 +347,30 @@ static void ar724x_pci_hw_init(struct ar
int wait = 0;
/* deassert PCIe host controller and PCIe PHY reset */
- ath79_device_reset_clear(AR724X_RESET_PCIE);
- ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
+ reset_control_deassert(apc->hc_reset);
+ reset_control_deassert(apc->phy_reset);
- /* remove the reset of the PCIE PLL */
- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
-
- /* deassert bypass for the PCIE PLL */
- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
+ if (of_device_is_compatible(apc->np, "qcom,qca9550-pci")) {
+ /* remove the reset of the PCIE PLL */
+ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
+ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_PWD;
+ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
+
+ /* deassert bypass for the PCIE PLL */
+ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
+ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS;
+ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
+ } else {
+ /* remove the reset of the PCIE PLL */
+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
+
+ /* deassert bypass for the PCIE PLL */
+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
+ }
/* set PCIE Application Control to ready */
app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
@@ -402,6 +418,14 @@ static int ar724x_pci_probe(struct platf
if (apc->irq < 0)
return -EINVAL;
+ apc->hc_reset = devm_reset_control_get_exclusive(&pdev->dev, "hc");
+ if (IS_ERR(apc->hc_reset))
+ return PTR_ERR(apc->hc_reset);
+
+ apc->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, "phy");
+ if (IS_ERR(apc->phy_reset))
+ return PTR_ERR(apc->phy_reset);
+
apc->np = pdev->dev.of_node;
apc->pci_controller.pci_ops = &ar724x_pci_ops;
apc->pci_controller.io_resource = &apc->io_res;
@@ -412,7 +436,7 @@ static int ar724x_pci_probe(struct platf
* Do the full PCIE Root Complex Initialization Sequence if the PCIe
* host controller is in reset.
*/
- if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
+ if (reset_control_status(apc->hc_reset))
ar724x_pci_hw_init(apc);
apc->link_up = ar724x_pci_check_link(apc);
@@ -430,6 +454,7 @@ static int ar724x_pci_probe(struct platf
static const struct of_device_id ar724x_pci_ids[] = {
{ .compatible = "qcom,ar7240-pci" },
+ { .compatible = "qcom,qca9550-pci" },
{},
};

View File

@ -1,21 +0,0 @@
--- a/drivers/mtd/parsers/Makefile
+++ b/drivers/mtd/parsers/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_MTD_PARSER_CYBERTAN) += parser_cybertan.o
obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o
obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o
obj-$(CONFIG_MTD_ROUTERBOOT_PARTS) += routerbootpart.o
--- a/drivers/mtd/parsers/Kconfig
+++ b/drivers/mtd/parsers/Kconfig
@@ -1,3 +1,11 @@
+config MTD_PARSER_CYBERTAN
+ tristate "Parser for Cybertan format partitions"
+ depends on MTD && (ATH79 || COMPILE_TEST)
+ help
+ Cybertan has a proprietory header than encompasses a Broadcom trx
+ header. This driver will parse the header and take care of the
+ special offsets that result in the extra headers.
+
config MTD_PARSER_TRX
tristate "Parser for TRX format partitions"
depends on MTD && (BCM47XX || ARCH_BCM_5301X || COMPILE_TEST)

View File

@ -1,44 +0,0 @@
--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
@@ -76,12 +76,18 @@ static int parse_redboot_partitions(stru
static char nullstring[] = "unallocated";
#endif
+ buf = vmalloc(master->erasesize);
+ if (!buf)
+ return -ENOMEM;
+
+ restart:
if ( directory < 0 ) {
offset = master->size + directory * master->erasesize;
while (mtd_block_isbad(master, offset)) {
if (!offset) {
nogood:
printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
+ vfree(buf);
return -EIO;
}
offset -= master->erasesize;
@@ -94,10 +100,6 @@ static int parse_redboot_partitions(stru
goto nogood;
}
}
- buf = vmalloc(master->erasesize);
-
- if (!buf)
- return -ENOMEM;
printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
master->name, offset);
@@ -170,6 +172,11 @@ static int parse_redboot_partitions(stru
}
if (i == numslots) {
/* Didn't find it */
+ if (offset + master->erasesize < master->size) {
+ /* not at the end of the flash yet, maybe next block :) */
+ directory++;
+ goto restart;
+ }
printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
master->name);
ret = 0;

View File

@ -1,68 +0,0 @@
From 8d8cdb4a6ccee5b62cc0dc64651c3946364514dc Mon Sep 17 00:00:00 2001
From: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Date: Mon, 10 Feb 2020 16:11:27 -0300
Subject: [PATCH] spi: ath79: Implement the spi_mem interface
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
drivers/spi/spi-ath79.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -19,6 +19,7 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
@@ -203,6 +204,39 @@ static u32 ath79_spi_txrx_mode0(struct s
return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
}
+static int ath79_exec_mem_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);
+
+ /* Ensures that reading is performed on device connected
+ to hardware cs0 */
+ if (mem->spi->chip_select || gpio_is_valid(mem->spi->cs_gpio))
+ return -ENOTSUPP;
+
+ /* Only use for fast-read op. */
+ if (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN ||
+ op->addr.nbytes != 3 || op->dummy.nbytes != 1)
+ return -ENOTSUPP;
+
+ /* disable GPIO mode */
+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
+
+ memcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes);
+
+ /* enable GPIO mode */
+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
+
+ /* restore IOC register */
+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+
+ return 0;
+}
+
+static const struct spi_controller_mem_ops ath79_mem_ops = {
+ .exec_op = ath79_exec_mem_op,
+};
+
static int ath79_spi_probe(struct platform_device *pdev)
{
struct spi_master *master;
@@ -237,6 +271,7 @@ static int ath79_spi_probe(struct platfo
ret = PTR_ERR(sp->base);
goto err_put_master;
}
+ master->mem_ops = &ath79_mem_ops;
sp->clk = devm_clk_get(&pdev->dev, "ahb");
if (IS_ERR(sp->clk)) {

View File

@ -1,28 +0,0 @@
--- a/drivers/net/ethernet/atheros/Kconfig
+++ b/drivers/net/ethernet/atheros/Kconfig
@@ -5,7 +5,7 @@
config NET_VENDOR_ATHEROS
bool "Atheros devices"
default y
- depends on PCI
+ depends on (PCI || ATH79)
---help---
If you have a network (Ethernet) card belonging to this class, say Y.
@@ -78,4 +78,6 @@ config ALX
To compile this driver as a module, choose M here. The module
will be called alx.
+source drivers/net/ethernet/atheros/ag71xx/Kconfig
+
endif # NET_VENDOR_ATHEROS
--- a/drivers/net/ethernet/atheros/Makefile
+++ b/drivers/net/ethernet/atheros/Makefile
@@ -3,6 +3,7 @@
# Makefile for the Atheros network device drivers.
#
+obj-$(CONFIG_AG71XX) += ag71xx/
obj-$(CONFIG_ATL1) += atlx/
obj-$(CONFIG_ATL2) += atlx/
obj-$(CONFIG_ATL1E) += atl1e/

View File

@ -1,16 +0,0 @@
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -391,6 +391,13 @@ static int at803x_aneg_done(struct phy_d
if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
pr_warn("803x_aneg_done: SGMII link is not ok\n");
aneg_done = 0;
+#ifdef CONFIG_OF_MDIO
+ if (phydev->mdio.dev.of_node &&
+ of_property_read_bool(phydev->mdio.dev.of_node,
+ "at803x-override-sgmii-link-check")) {
+ aneg_done = 1;
+ }
+#endif
}
/* switch back to copper page */
phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);

View File

@ -1,12 +0,0 @@
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -80,8 +80,8 @@ obj-y += scsi/
obj-y += nvme/
obj-$(CONFIG_ATA) += ata/
obj-$(CONFIG_TARGET_CORE) += target/
-obj-$(CONFIG_MTD) += mtd/
obj-$(CONFIG_SPI) += spi/
+obj-$(CONFIG_MTD) += mtd/
obj-$(CONFIG_SPMI) += spmi/
obj-$(CONFIG_HSI) += hsi/
obj-$(CONFIG_SLIMBUS) += slimbus/

View File

@ -1,25 +0,0 @@
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -561,4 +561,12 @@ config MTD_NAND_TEGRA
is supported. Extra OOB bytes when using HW ECC are currently
not supported.
+config MTD_NAND_AR934X
+ tristate "Support for NAND controller on Qualcomm Atheros AR934x/QCA955x SoCs"
+ depends on ATH79 || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ Enables support for NAND controller on Qualcomm Atheros SoCs.
+ This controller is found on AR934x and QCA955x SoCs.
+
endif # MTD_NAND
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcm
obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
+obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nand.o
nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
nand-objs += nand_amd.o

View File

@ -1,98 +0,0 @@
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
+#define __ASM_MACH_ATH79_MANGLE_PORT_H
+
+#ifdef CONFIG_PCI_AR71XX
+extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
+extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
+#else
+#define ath79_pci_swizzle_b(port) (port)
+#define ath79_pci_swizzle_w(port) (port)
+#endif
+
+#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port)
+#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port)
+#define __swizzle_addr_l(port) (port)
+#define __swizzle_addr_q(port) (port)
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) (x)
+# define __mem_ioswabw(a, x) cpu_to_le16(x)
+# define ioswabl(a, x) (x)
+# define __mem_ioswabl(a, x) cpu_to_le32(x)
+# define ioswabq(a, x) (x)
+# define __mem_ioswabq(a, x) cpu_to_le64(x)
+
+#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
--- a/arch/mips/pci/pci-ar71xx.c
+++ b/arch/mips/pci/pci-ar71xx.c
@@ -71,6 +71,45 @@ static const u32 ar71xx_pci_read_mask[8]
0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
};
+static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
+static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
+
+static inline bool ar71xx_is_pci_addr(unsigned long port)
+{
+ unsigned long phys = CPHYSADDR(port);
+
+ return (phys >= AR71XX_PCI_MEM_BASE &&
+ phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
+}
+
+static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
+{
+ return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
+}
+
+static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
+{
+ return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
+}
+
+unsigned long ath79_pci_swizzle_b(unsigned long port)
+{
+ if (__ath79_pci_swizzle_b)
+ return __ath79_pci_swizzle_b(port);
+
+ return port;
+}
+EXPORT_SYMBOL(ath79_pci_swizzle_b);
+
+unsigned long ath79_pci_swizzle_w(unsigned long port)
+{
+ if (__ath79_pci_swizzle_w)
+ return __ath79_pci_swizzle_w(port);
+
+ return port;
+}
+EXPORT_SYMBOL(ath79_pci_swizzle_w);
+
static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
{
u32 t;
@@ -279,6 +318,9 @@ static int ar71xx_pci_probe(struct platf
register_pci_controller(&apc->pci_ctrl);
+ __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
+ __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
+
return 0;
}

View File

@ -1,107 +0,0 @@
From 71dd6c0dff51b5f1fef2e9dfa6f6a948aac975f3 Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Wed, 17 Apr 2019 23:59:21 +0200
Subject: [PATCH] net: phy: add support for reset-controller
This commit adds support for PHY reset pins handled by a reset controller.
Signed-off-by: David Bauer <mail@david-bauer.net>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/mdio_bus.c | 27 +++++++++++++++++++++++++--
drivers/net/phy/mdio_device.c | 13 +++++++++++--
include/linux/mdio.h | 1 +
3 files changed, 37 insertions(+), 4 deletions(-)
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -29,6 +29,7 @@
#include <linux/of_gpio.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
+#include <linux/reset.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
@@ -65,8 +66,23 @@ static int mdiobus_register_gpiod(struct
mdiodev->reset = gpiod;
- /* Assert the reset signal again */
- mdio_device_reset(mdiodev, 1);
+ return 0;
+}
+
+static int mdiobus_register_reset(struct mdio_device *mdiodev)
+{
+ struct reset_control *reset = NULL;
+
+ if (mdiodev->dev.of_node)
+ reset = devm_reset_control_get_exclusive(&mdiodev->dev,
+ "phy");
+ if (PTR_ERR(reset) == -ENOENT ||
+ PTR_ERR(reset) == -ENOTSUPP)
+ reset = NULL;
+ else if (IS_ERR(reset))
+ return PTR_ERR(reset);
+
+ mdiodev->reset_ctrl = reset;
return 0;
}
@@ -82,6 +98,13 @@ int mdiobus_register_device(struct mdio_
err = mdiobus_register_gpiod(mdiodev);
if (err)
return err;
+
+ err = mdiobus_register_reset(mdiodev);
+ if (err)
+ return err;
+
+ /* Assert the reset signal */
+ mdio_device_reset(mdiodev, 1);
}
mdiodev->bus->mdio_map[mdiodev->addr] = mdiodev;
--- a/drivers/net/phy/mdio_device.c
+++ b/drivers/net/phy/mdio_device.c
@@ -21,6 +21,7 @@
#include <linux/mii.h>
#include <linux/module.h>
#include <linux/phy.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/unistd.h>
@@ -121,10 +122,18 @@ void mdio_device_reset(struct mdio_devic
{
unsigned int d;
- if (!mdiodev->reset)
+ if (!mdiodev->reset && !mdiodev->reset_ctrl)
return;
- gpiod_set_value(mdiodev->reset, value);
+ if (mdiodev->reset)
+ gpiod_set_value(mdiodev->reset, value);
+
+ if (mdiodev->reset_ctrl) {
+ if (value)
+ reset_control_assert(mdiodev->reset_ctrl);
+ else
+ reset_control_deassert(mdiodev->reset_ctrl);
+ }
d = value ? mdiodev->reset_assert_delay : mdiodev->reset_deassert_delay;
if (d)
--- a/include/linux/mdio.h
+++ b/include/linux/mdio.h
@@ -40,6 +40,7 @@ struct mdio_device {
int addr;
int flags;
struct gpio_desc *reset;
+ struct reset_control *reset_ctrl;
unsigned int reset_assert_delay;
unsigned int reset_deassert_delay;
};

View File

@ -1,44 +0,0 @@
From 32085f25d7b68404055f3525c780142fc72e543f Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Fri, 22 Nov 2019 22:44:51 +0100
Subject: [PATCH] mdio_bus: don't use managed reset-controller
Geert Uytterhoeven reported that using devm_reset_controller_get leads
to a WARNING when probing a reset-controlled PHY. This is because the
device devm_reset_controller_get gets supplied is not actually the
one being probed.
Acquire an unmanaged reset-control as well as free the reset_control on
unregister to fix this.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
CC: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David Bauer <mail@david-bauer.net>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/mdio_bus.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -74,8 +74,8 @@ static int mdiobus_register_reset(struct
struct reset_control *reset = NULL;
if (mdiodev->dev.of_node)
- reset = devm_reset_control_get_exclusive(&mdiodev->dev,
- "phy");
+ reset = of_reset_control_get_exclusive(mdiodev->dev.of_node,
+ "phy");
if (PTR_ERR(reset) == -ENOENT ||
PTR_ERR(reset) == -ENOTSUPP)
reset = NULL;
@@ -118,6 +118,8 @@ int mdiobus_unregister_device(struct mdi
if (mdiodev->bus->mdio_map[mdiodev->addr] != mdiodev)
return -EINVAL;
+ reset_control_put(mdiodev->reset_ctrl);
+
mdiodev->bus->mdio_map[mdiodev->addr] = NULL;
return 0;

View File

@ -1,32 +0,0 @@
--- a/drivers/net/phy/mdio-bitbang.c
+++ b/drivers/net/phy/mdio-bitbang.c
@@ -155,7 +155,7 @@ static int mdiobb_cmd_addr(struct mdiobb
static int mdiobb_read(struct mii_bus *bus, int phy, int reg)
{
struct mdiobb_ctrl *ctrl = bus->priv;
- int ret, i;
+ int ret;
if (reg & MII_ADDR_C45) {
reg = mdiobb_cmd_addr(ctrl, phy, reg);
@@ -165,19 +165,7 @@ static int mdiobb_read(struct mii_bus *b
ctrl->ops->set_mdio_dir(ctrl, 0);
- /* check the turnaround bit: the PHY should be driving it to zero, if this
- * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that
- */
- if (mdiobb_get_bit(ctrl) != 0 &&
- !(bus->phy_ignore_ta_mask & (1 << phy))) {
- /* PHY didn't drive TA low -- flush any bits it
- * may be trying to send.
- */
- for (i = 0; i < 32; i++)
- mdiobb_get_bit(ctrl);
-
- return 0xffff;
- }
+ mdiobb_get_bit(ctrl);
ret = mdiobb_get_num(ctrl, 16);
mdiobb_get_bit(ctrl);

View File

@ -1,61 +0,0 @@
From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Tue, 16 Jun 2015 13:15:08 +0200
Subject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command
It seems some phys have some maximum timings for accessing the MDIO line,
resulting in bit errors under cpu stress. Prevent this from happening by
disabling interrupts when sending commands.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
drivers/net/phy/mdio-bitbang.c | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/drivers/net/phy/mdio-bitbang.c
+++ b/drivers/net/phy/mdio-bitbang.c
@@ -17,6 +17,7 @@
* kind, whether express or implied.
*/
+#include <linux/irqflags.h>
#include <linux/module.h>
#include <linux/mdio-bitbang.h>
#include <linux/types.h>
@@ -156,7 +157,9 @@ static int mdiobb_read(struct mii_bus *b
{
struct mdiobb_ctrl *ctrl = bus->priv;
int ret;
+ unsigned long flags;
+ local_irq_save(flags);
if (reg & MII_ADDR_C45) {
reg = mdiobb_cmd_addr(ctrl, phy, reg);
mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg);
@@ -169,13 +172,17 @@ static int mdiobb_read(struct mii_bus *b
ret = mdiobb_get_num(ctrl, 16);
mdiobb_get_bit(ctrl);
+ local_irq_restore(flags);
+
return ret;
}
static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
{
struct mdiobb_ctrl *ctrl = bus->priv;
+ unsigned long flags;
+ local_irq_save(flags);
if (reg & MII_ADDR_C45) {
reg = mdiobb_cmd_addr(ctrl, phy, reg);
mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg);
@@ -190,6 +197,8 @@ static int mdiobb_write(struct mii_bus *
ctrl->ops->set_mdio_dir(ctrl, 0);
mdiobb_get_bit(ctrl);
+ local_irq_restore(flags);
+
return 0;
}

View File

@ -1,891 +0,0 @@
--- a/arch/mips/include/asm/checksum.h
+++ b/arch/mips/include/asm/checksum.h
@@ -134,26 +134,30 @@ static inline __sum16 ip_fast_csum(const
const unsigned int *stop = word + ihl;
unsigned int csum;
int carry;
+ unsigned int w;
- csum = word[0];
- csum += word[1];
- carry = (csum < word[1]);
+ csum = net_hdr_word(word++);
+
+ w = net_hdr_word(word++);
+ csum += w;
+ carry = (csum < w);
csum += carry;
- csum += word[2];
- carry = (csum < word[2]);
+ w = net_hdr_word(word++);
+ csum += w;
+ carry = (csum < w);
csum += carry;
- csum += word[3];
- carry = (csum < word[3]);
+ w = net_hdr_word(word++);
+ csum += w;
+ carry = (csum < w);
csum += carry;
- word += 4;
do {
- csum += *word;
- carry = (csum < *word);
+ w = net_hdr_word(word++);
+ csum += w;
+ carry = (csum < w);
csum += carry;
- word++;
} while (word != stop);
return csum_fold(csum);
@@ -214,73 +218,6 @@ static inline __sum16 ip_compute_csum(co
return csum_fold(csum_partial(buff, len, 0));
}
-#define _HAVE_ARCH_IPV6_CSUM
-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
- const struct in6_addr *daddr,
- __u32 len, __u8 proto,
- __wsum sum)
-{
- __wsum tmp;
-
- __asm__(
- " .set push # csum_ipv6_magic\n"
- " .set noreorder \n"
- " .set noat \n"
- " addu %0, %5 # proto (long in network byte order)\n"
- " sltu $1, %0, %5 \n"
- " addu %0, $1 \n"
-
- " addu %0, %6 # csum\n"
- " sltu $1, %0, %6 \n"
- " lw %1, 0(%2) # four words source address\n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 4(%2) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 8(%2) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 12(%2) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 0(%3) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 4(%3) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 8(%3) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " lw %1, 12(%3) \n"
- " addu %0, $1 \n"
- " addu %0, %1 \n"
- " sltu $1, %0, %1 \n"
-
- " addu %0, $1 # Add final carry\n"
- " .set pop"
- : "=&r" (sum), "=&r" (tmp)
- : "r" (saddr), "r" (daddr),
- "0" (htonl(len)), "r" (htonl(proto)), "r" (sum));
-
- return csum_fold(sum);
-}
-
#include <asm-generic/checksum.h>
#endif /* CONFIG_GENERIC_CSUM */
--- a/include/uapi/linux/ip.h
+++ b/include/uapi/linux/ip.h
@@ -103,7 +103,7 @@ struct iphdr {
__be32 saddr;
__be32 daddr;
/*The options start here. */
-};
+} __attribute__((packed, aligned(2)));
struct ip_auth_hdr {
--- a/include/uapi/linux/ipv6.h
+++ b/include/uapi/linux/ipv6.h
@@ -131,7 +131,7 @@ struct ipv6hdr {
struct in6_addr saddr;
struct in6_addr daddr;
-};
+} __attribute__((packed, aligned(2)));
/* index values for the variables in ipv6_devconf */
--- a/include/uapi/linux/tcp.h
+++ b/include/uapi/linux/tcp.h
@@ -55,7 +55,7 @@ struct tcphdr {
__be16 window;
__sum16 check;
__be16 urg_ptr;
-};
+} __attribute__((packed, aligned(2)));
/*
* The union cast uses a gcc extension to avoid aliasing problems
@@ -65,7 +65,7 @@ struct tcphdr {
union tcp_word_hdr {
struct tcphdr hdr;
__be32 words[5];
-};
+} __attribute__((packed, aligned(2)));
#define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3])
--- a/include/uapi/linux/udp.h
+++ b/include/uapi/linux/udp.h
@@ -25,7 +25,7 @@ struct udphdr {
__be16 dest;
__be16 len;
__sum16 check;
-};
+} __attribute__((packed, aligned(2)));
/* UDP socket options */
#define UDP_CORK 1 /* Never send partially complete segments */
--- a/net/netfilter/nf_conntrack_core.c
+++ b/net/netfilter/nf_conntrack_core.c
@@ -263,8 +263,8 @@ nf_ct_get_tuple(const struct sk_buff *sk
switch (l3num) {
case NFPROTO_IPV4:
- tuple->src.u3.ip = ap[0];
- tuple->dst.u3.ip = ap[1];
+ tuple->src.u3.ip = net_hdr_word(ap++);
+ tuple->dst.u3.ip = net_hdr_word(ap);
break;
case NFPROTO_IPV6:
memcpy(tuple->src.u3.ip6, ap, sizeof(tuple->src.u3.ip6));
--- a/include/uapi/linux/icmp.h
+++ b/include/uapi/linux/icmp.h
@@ -82,7 +82,7 @@ struct icmphdr {
} frag;
__u8 reserved[4];
} un;
-};
+} __attribute__((packed, aligned(2)));
/*
--- a/include/uapi/linux/in6.h
+++ b/include/uapi/linux/in6.h
@@ -43,7 +43,7 @@ struct in6_addr {
#define s6_addr16 in6_u.u6_addr16
#define s6_addr32 in6_u.u6_addr32
#endif
-};
+} __attribute__((packed, aligned(2)));
#endif /* __UAPI_DEF_IN6_ADDR */
#if __UAPI_DEF_SOCKADDR_IN6
--- a/net/ipv6/tcp_ipv6.c
+++ b/net/ipv6/tcp_ipv6.c
@@ -39,6 +39,7 @@
#include <linux/ipsec.h>
#include <linux/times.h>
#include <linux/slab.h>
+#include <asm/unaligned.h>
#include <linux/uaccess.h>
#include <linux/ipv6.h>
#include <linux/icmpv6.h>
@@ -836,10 +837,10 @@ static void tcp_v6_send_response(const s
topt = (__be32 *)(t1 + 1);
if (tsecr) {
- *topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
- (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP);
- *topt++ = htonl(tsval);
- *topt++ = htonl(tsecr);
+ put_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
+ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++);
+ put_unaligned_be32(tsval, topt++);
+ put_unaligned_be32(tsecr, topt++);
}
#ifdef CONFIG_TCP_MD5SIG
--- a/include/linux/ipv6.h
+++ b/include/linux/ipv6.h
@@ -6,6 +6,7 @@
#define ipv6_optlen(p) (((p)->hdrlen+1) << 3)
#define ipv6_authlen(p) (((p)->hdrlen+2) << 2)
+
/*
* This structure contains configuration options per IPv6 link.
*/
--- a/net/ipv6/datagram.c
+++ b/net/ipv6/datagram.c
@@ -480,7 +480,7 @@ int ipv6_recv_error(struct sock *sk, str
ipv6_iface_scope_id(&sin->sin6_addr,
IP6CB(skb)->iif);
} else {
- ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset),
+ ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset),
&sin->sin6_addr);
sin->sin6_scope_id = 0;
}
@@ -830,12 +830,12 @@ int ip6_datagram_send_ctl(struct net *ne
}
if (fl6->flowlabel&IPV6_FLOWINFO_MASK) {
- if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) {
+ if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) {
err = -EINVAL;
goto exit_f;
}
}
- fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg);
+ fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg));
break;
case IPV6_2292HOPOPTS:
--- a/net/ipv6/ip6_gre.c
+++ b/net/ipv6/ip6_gre.c
@@ -455,7 +455,7 @@ static void ip6gre_err(struct sk_buff *s
return;
ipv6h = (const struct ipv6hdr *)skb->data;
greh = (const struct gre_base_hdr *)(skb->data + offset);
- key = key_off ? *(__be32 *)(skb->data + key_off) : 0;
+ key = key_off ? net_hdr_word((__be32 *)(skb->data + key_off)) : 0;
t = ip6gre_tunnel_lookup(skb->dev, &ipv6h->daddr, &ipv6h->saddr,
key, greh->protocol);
--- a/net/ipv6/exthdrs.c
+++ b/net/ipv6/exthdrs.c
@@ -756,7 +756,7 @@ static bool ipv6_hop_jumbo(struct sk_buf
goto drop;
}
- pkt_len = ntohl(*(__be32 *)(nh + optoff + 2));
+ pkt_len = ntohl(net_hdr_word(nh + optoff + 2));
if (pkt_len <= IPV6_MAXPLEN) {
__IP6_INC_STATS(net, idev, IPSTATS_MIB_INHDRERRORS);
icmpv6_param_prob(skb, ICMPV6_HDR_FIELD, optoff+2);
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -230,5 +230,11 @@ struct callback_head {
typedef void (*rcu_callback_t)(struct rcu_head *head);
typedef void (*call_rcu_func_t)(struct rcu_head *head, rcu_callback_t func);
+struct net_hdr_word {
+ u32 words[1];
+} __attribute__((packed, aligned(2)));
+
+#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0])
+
#endif /* __ASSEMBLY__ */
#endif /* _LINUX_TYPES_H */
--- a/net/ipv4/af_inet.c
+++ b/net/ipv4/af_inet.c
@@ -1422,8 +1422,8 @@ struct sk_buff *inet_gro_receive(struct
if (unlikely(ip_fast_csum((u8 *)iph, 5)))
goto out_unlock;
- id = ntohl(*(__be32 *)&iph->id);
- flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF));
+ id = ntohl(net_hdr_word(&iph->id));
+ flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF));
id >>= 16;
list_for_each_entry(p, head, list) {
--- a/net/ipv4/route.c
+++ b/net/ipv4/route.c
@@ -449,7 +449,7 @@ static struct neighbour *ipv4_neigh_look
else if (skb)
pkey = &ip_hdr(skb)->daddr;
- n = __ipv4_neigh_lookup(dev, *(__force u32 *)pkey);
+ n = __ipv4_neigh_lookup(dev, net_hdr_word(pkey));
if (n)
return n;
return neigh_create(&arp_tbl, pkey, dev);
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -447,48 +447,53 @@ static void tcp_options_write(__be32 *pt
u16 options = opts->options; /* mungable copy */
if (unlikely(OPTION_MD5 & options)) {
- *ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
- (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
+ net_hdr_word(ptr++) =
+ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
+ (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
/* overload cookie hash location */
opts->hash_location = (__u8 *)ptr;
ptr += 4;
}
if (unlikely(opts->mss)) {
- *ptr++ = htonl((TCPOPT_MSS << 24) |
- (TCPOLEN_MSS << 16) |
- opts->mss);
+ net_hdr_word(ptr++) =
+ htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) |
+ opts->mss);
}
if (likely(OPTION_TS & options)) {
if (unlikely(OPTION_SACK_ADVERTISE & options)) {
- *ptr++ = htonl((TCPOPT_SACK_PERM << 24) |
- (TCPOLEN_SACK_PERM << 16) |
- (TCPOPT_TIMESTAMP << 8) |
- TCPOLEN_TIMESTAMP);
+ net_hdr_word(ptr++) =
+ htonl((TCPOPT_SACK_PERM << 24) |
+ (TCPOLEN_SACK_PERM << 16) |
+ (TCPOPT_TIMESTAMP << 8) |
+ TCPOLEN_TIMESTAMP);
options &= ~OPTION_SACK_ADVERTISE;
} else {
- *ptr++ = htonl((TCPOPT_NOP << 24) |
- (TCPOPT_NOP << 16) |
- (TCPOPT_TIMESTAMP << 8) |
- TCPOLEN_TIMESTAMP);
+ net_hdr_word(ptr++) =
+ htonl((TCPOPT_NOP << 24) |
+ (TCPOPT_NOP << 16) |
+ (TCPOPT_TIMESTAMP << 8) |
+ TCPOLEN_TIMESTAMP);
}
- *ptr++ = htonl(opts->tsval);
- *ptr++ = htonl(opts->tsecr);
+ net_hdr_word(ptr++) = htonl(opts->tsval);
+ net_hdr_word(ptr++) = htonl(opts->tsecr);
}
if (unlikely(OPTION_SACK_ADVERTISE & options)) {
- *ptr++ = htonl((TCPOPT_NOP << 24) |
- (TCPOPT_NOP << 16) |
- (TCPOPT_SACK_PERM << 8) |
- TCPOLEN_SACK_PERM);
+ net_hdr_word(ptr++) =
+ htonl((TCPOPT_NOP << 24) |
+ (TCPOPT_NOP << 16) |
+ (TCPOPT_SACK_PERM << 8) |
+ TCPOLEN_SACK_PERM);
}
if (unlikely(OPTION_WSCALE & options)) {
- *ptr++ = htonl((TCPOPT_NOP << 24) |
- (TCPOPT_WINDOW << 16) |
- (TCPOLEN_WINDOW << 8) |
- opts->ws);
+ net_hdr_word(ptr++) =
+ htonl((TCPOPT_NOP << 24) |
+ (TCPOPT_WINDOW << 16) |
+ (TCPOLEN_WINDOW << 8) |
+ opts->ws);
}
if (unlikely(opts->num_sack_blocks)) {
@@ -496,16 +501,17 @@ static void tcp_options_write(__be32 *pt
tp->duplicate_sack : tp->selective_acks;
int this_sack;
- *ptr++ = htonl((TCPOPT_NOP << 24) |
- (TCPOPT_NOP << 16) |
- (TCPOPT_SACK << 8) |
- (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
+ net_hdr_word(ptr++) =
+ htonl((TCPOPT_NOP << 24) |
+ (TCPOPT_NOP << 16) |
+ (TCPOPT_SACK << 8) |
+ (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
TCPOLEN_SACK_PERBLOCK)));
for (this_sack = 0; this_sack < opts->num_sack_blocks;
++this_sack) {
- *ptr++ = htonl(sp[this_sack].start_seq);
- *ptr++ = htonl(sp[this_sack].end_seq);
+ net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq);
+ net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq);
}
tp->rx_opt.dsack = 0;
@@ -518,13 +524,14 @@ static void tcp_options_write(__be32 *pt
if (foc->exp) {
len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;
- *ptr = htonl((TCPOPT_EXP << 24) | (len << 16) |
+ net_hdr_word(ptr) =
+ htonl((TCPOPT_EXP << 24) | (len << 16) |
TCPOPT_FASTOPEN_MAGIC);
p += TCPOLEN_EXP_FASTOPEN_BASE;
} else {
len = TCPOLEN_FASTOPEN_BASE + foc->len;
- *p++ = TCPOPT_FASTOPEN;
- *p++ = len;
+ net_hdr_word(p++) = TCPOPT_FASTOPEN;
+ net_hdr_word(p++) = len;
}
memcpy(p, foc->val, foc->len);
--- a/include/uapi/linux/igmp.h
+++ b/include/uapi/linux/igmp.h
@@ -33,7 +33,7 @@ struct igmphdr {
__u8 code; /* For newer IGMP */
__sum16 csum;
__be32 group;
-};
+} __attribute__((packed, aligned(2)));
/* V3 group record types [grec_type] */
#define IGMPV3_MODE_IS_INCLUDE 1
@@ -49,7 +49,7 @@ struct igmpv3_grec {
__be16 grec_nsrcs;
__be32 grec_mca;
__be32 grec_src[0];
-};
+} __attribute__((packed, aligned(2)));
struct igmpv3_report {
__u8 type;
@@ -58,7 +58,7 @@ struct igmpv3_report {
__be16 resv2;
__be16 ngrec;
struct igmpv3_grec grec[0];
-};
+} __attribute__((packed, aligned(2)));
struct igmpv3_query {
__u8 type;
@@ -79,7 +79,7 @@ struct igmpv3_query {
__u8 qqic;
__be16 nsrcs;
__be32 srcs[0];
-};
+} __attribute__((packed, aligned(2)));
#define IGMP_HOST_MEMBERSHIP_QUERY 0x11 /* From RFC1112 */
#define IGMP_HOST_MEMBERSHIP_REPORT 0x12 /* Ditto */
--- a/net/core/flow_dissector.c
+++ b/net/core/flow_dissector.c
@@ -111,7 +111,7 @@ __be32 __skb_flow_get_ports(const struct
ports = __skb_header_pointer(skb, thoff + poff,
sizeof(_ports), data, hlen, &_ports);
if (ports)
- return *ports;
+ return (__be32)net_hdr_word(ports);
}
return 0;
--- a/include/uapi/linux/icmpv6.h
+++ b/include/uapi/linux/icmpv6.h
@@ -77,7 +77,7 @@ struct icmp6hdr {
#define icmp6_addrconf_other icmp6_dataun.u_nd_ra.other
#define icmp6_rt_lifetime icmp6_dataun.u_nd_ra.rt_lifetime
#define icmp6_router_pref icmp6_dataun.u_nd_ra.router_pref
-};
+} __attribute__((packed, aligned(2)));
#define ICMPV6_ROUTER_PREF_LOW 0x3
--- a/include/net/ndisc.h
+++ b/include/net/ndisc.h
@@ -89,7 +89,7 @@ struct ra_msg {
struct icmp6hdr icmph;
__be32 reachable_time;
__be32 retrans_timer;
-};
+} __attribute__((packed, aligned(2)));
struct rd_msg {
struct icmp6hdr icmph;
@@ -368,10 +368,10 @@ static inline u32 ndisc_hashfn(const voi
{
const u32 *p32 = pkey;
- return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) +
- (p32[1] * hash_rnd[1]) +
- (p32[2] * hash_rnd[2]) +
- (p32[3] * hash_rnd[3]));
+ return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) +
+ (net_hdr_word(&p32[1]) * hash_rnd[1]) +
+ (net_hdr_word(&p32[2]) * hash_rnd[2]) +
+ (net_hdr_word(&p32[3]) * hash_rnd[3]));
}
static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey)
--- a/net/sched/cls_u32.c
+++ b/net/sched/cls_u32.c
@@ -165,7 +165,7 @@ next_knode:
data = skb_header_pointer(skb, toff, 4, &hdata);
if (!data)
goto out;
- if ((*data ^ key->val) & key->mask) {
+ if ((net_hdr_word(data) ^ key->val) & key->mask) {
n = rcu_dereference_bh(n->next);
goto next_knode;
}
@@ -218,8 +218,8 @@ check_terminal:
&hdata);
if (!data)
goto out;
- sel = ht->divisor & u32_hash_fold(*data, &n->sel,
- n->fshift);
+ sel = ht->divisor & u32_hash_fold(net_hdr_word(data),
+ &n->sel, n->fshift);
}
if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT)))
goto next_ht;
--- a/net/ipv6/ip6_offload.c
+++ b/net/ipv6/ip6_offload.c
@@ -223,7 +223,7 @@ static struct sk_buff *ipv6_gro_receive(
continue;
iph2 = (struct ipv6hdr *)(p->data + off);
- first_word = *(__be32 *)iph ^ *(__be32 *)iph2;
+ first_word = net_hdr_word(iph) ^ net_hdr_word(iph2);
/* All fields must match except length and Traffic Class.
* XXX skbs on the gro_list have all been parsed and pulled
--- a/include/net/addrconf.h
+++ b/include/net/addrconf.h
@@ -47,7 +47,7 @@ struct prefix_info {
__be32 reserved2;
struct in6_addr prefix;
-};
+} __attribute__((packed, aligned(2)));
#include <linux/netdevice.h>
#include <net/if_inet6.h>
--- a/include/net/inet_ecn.h
+++ b/include/net/inet_ecn.h
@@ -126,9 +126,9 @@ static inline int IP6_ECN_set_ce(struct
if (INET_ECN_is_not_ect(ipv6_get_dsfield(iph)))
return 0;
- from = *(__be32 *)iph;
+ from = net_hdr_word(iph);
to = from | htonl(INET_ECN_CE << 20);
- *(__be32 *)iph = to;
+ net_hdr_word(iph) = to;
if (skb->ip_summed == CHECKSUM_COMPLETE)
skb->csum = csum_add(csum_sub(skb->csum, (__force __wsum)from),
(__force __wsum)to);
--- a/include/net/ipv6.h
+++ b/include/net/ipv6.h
@@ -149,7 +149,7 @@ struct frag_hdr {
__u8 reserved;
__be16 frag_off;
__be32 identification;
-};
+} __attribute__((packed, aligned(2)));
#define IP6_MF 0x0001
#define IP6_OFFSET 0xFFF8
@@ -499,8 +499,8 @@ static inline void __ipv6_addr_set_half(
}
#endif
#endif
- addr[0] = wh;
- addr[1] = wl;
+ net_hdr_word(&addr[0]) = wh;
+ net_hdr_word(&addr[1]) = wl;
}
static inline void ipv6_addr_set(struct in6_addr *addr,
@@ -559,6 +559,8 @@ static inline bool ipv6_prefix_equal(con
const __be32 *a1 = addr1->s6_addr32;
const __be32 *a2 = addr2->s6_addr32;
unsigned int pdw, pbi;
+ /* Used for last <32-bit fraction of prefix */
+ u32 pbia1, pbia2;
/* check complete u32 in prefix */
pdw = prefixlen >> 5;
@@ -567,7 +569,9 @@ static inline bool ipv6_prefix_equal(con
/* check incomplete u32 in prefix */
pbi = prefixlen & 0x1f;
- if (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi))))
+ pbia1 = net_hdr_word(&a1[pdw]);
+ pbia2 = net_hdr_word(&a2[pdw]);
+ if (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi))))
return false;
return true;
@@ -683,13 +687,13 @@ static inline void ipv6_addr_set_v4mappe
*/
static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen)
{
- const __be32 *a1 = token1, *a2 = token2;
+ const struct in6_addr *a1 = token1, *a2 = token2;
int i;
addrlen >>= 2;
for (i = 0; i < addrlen; i++) {
- __be32 xb = a1[i] ^ a2[i];
+ __be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i];
if (xb)
return i * 32 + 31 - __fls(ntohl(xb));
}
@@ -876,17 +880,18 @@ static inline int ip6_multipath_hash_pol
static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass,
__be32 flowlabel)
{
- *(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel;
+ net_hdr_word((__be32 *)hdr) =
+ htonl(0x60000000 | (tclass << 20)) | flowlabel;
}
static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr)
{
- return *(__be32 *)hdr & IPV6_FLOWINFO_MASK;
+ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK;
}
static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr)
{
- return *(__be32 *)hdr & IPV6_FLOWLABEL_MASK;
+ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK;
}
static inline u8 ip6_tclass(__be32 flowinfo)
--- a/include/net/secure_seq.h
+++ b/include/net/secure_seq.h
@@ -3,6 +3,7 @@
#define _NET_SECURE_SEQ
#include <linux/types.h>
+#include <linux/in6.h>
u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport);
u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr,
--- a/include/uapi/linux/in.h
+++ b/include/uapi/linux/in.h
@@ -84,7 +84,7 @@ enum {
/* Internet address. */
struct in_addr {
__be32 s_addr;
-};
+} __attribute__((packed, aligned(2)));
#endif
#define IP_TOS 1
--- a/net/ipv6/ip6_fib.c
+++ b/net/ipv6/ip6_fib.c
@@ -142,7 +142,7 @@ static __be32 addr_bit_set(const void *t
* See include/asm-generic/bitops/le.h.
*/
return (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) &
- addr[fn_bit >> 5];
+ net_hdr_word(&addr[fn_bit >> 5]);
}
struct fib6_info *fib6_info_alloc(gfp_t gfp_flags)
--- a/net/netfilter/nf_conntrack_proto_tcp.c
+++ b/net/netfilter/nf_conntrack_proto_tcp.c
@@ -423,7 +423,7 @@ static void tcp_sack(const struct sk_buf
/* Fast path for timestamp-only option */
if (length == TCPOLEN_TSTAMP_ALIGNED
- && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24)
+ && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24)
| (TCPOPT_NOP << 16)
| (TCPOPT_TIMESTAMP << 8)
| TCPOLEN_TIMESTAMP))
--- a/net/xfrm/xfrm_input.c
+++ b/net/xfrm/xfrm_input.c
@@ -194,8 +194,8 @@ int xfrm_parse_spi(struct sk_buff *skb,
if (!pskb_may_pull(skb, hlen))
return -EINVAL;
- *spi = *(__be32 *)(skb_transport_header(skb) + offset);
- *seq = *(__be32 *)(skb_transport_header(skb) + offset_seq);
+ *spi = net_hdr_word(skb_transport_header(skb) + offset);
+ *seq = net_hdr_word(skb_transport_header(skb) + offset_seq);
return 0;
}
EXPORT_SYMBOL(xfrm_parse_spi);
--- a/net/ipv4/tcp_input.c
+++ b/net/ipv4/tcp_input.c
@@ -3907,14 +3907,16 @@ static bool tcp_parse_aligned_timestamp(
{
const __be32 *ptr = (const __be32 *)(th + 1);
- if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16)
- | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
+ if (net_hdr_word(ptr) ==
+ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
+ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
tp->rx_opt.saw_tstamp = 1;
++ptr;
- tp->rx_opt.rcv_tsval = ntohl(*ptr);
+ tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr);
++ptr;
- if (*ptr)
- tp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset;
+ if (net_hdr_word(ptr))
+ tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) -
+ tp->tsoffset;
else
tp->rx_opt.rcv_tsecr = 0;
return true;
--- a/include/uapi/linux/if_pppox.h
+++ b/include/uapi/linux/if_pppox.h
@@ -51,6 +51,7 @@ struct pppoe_addr {
*/
struct pptp_addr {
__u16 call_id;
+ __u16 pad;
struct in_addr sin_addr;
};
--- a/net/ipv6/netfilter/nf_log_ipv6.c
+++ b/net/ipv6/netfilter/nf_log_ipv6.c
@@ -66,9 +66,9 @@ static void dump_ipv6_packet(struct net
/* Max length: 44 "LEN=65535 TC=255 HOPLIMIT=255 FLOWLBL=FFFFF " */
nf_log_buf_add(m, "LEN=%zu TC=%u HOPLIMIT=%u FLOWLBL=%u ",
ntohs(ih->payload_len) + sizeof(struct ipv6hdr),
- (ntohl(*(__be32 *)ih) & 0x0ff00000) >> 20,
+ (ntohl(net_hdr_word(ih)) & 0x0ff00000) >> 20,
ih->hop_limit,
- (ntohl(*(__be32 *)ih) & 0x000fffff));
+ (ntohl(net_hdr_word(ih)) & 0x000fffff));
fragment = 0;
ptr = ip6hoff + sizeof(struct ipv6hdr);
--- a/include/net/neighbour.h
+++ b/include/net/neighbour.h
@@ -266,8 +266,10 @@ static inline bool neigh_key_eq128(const
const u32 *n32 = (const u32 *)n->primary_key;
const u32 *p32 = pkey;
- return ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) |
- (n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0;
+ return ((n32[0] ^ net_hdr_word(&p32[0])) |
+ (n32[1] ^ net_hdr_word(&p32[1])) |
+ (n32[2] ^ net_hdr_word(&p32[2])) |
+ (n32[3] ^ net_hdr_word(&p32[3]))) == 0;
}
static inline struct neighbour *___neigh_lookup_noref(
--- a/include/uapi/linux/netfilter_arp/arp_tables.h
+++ b/include/uapi/linux/netfilter_arp/arp_tables.h
@@ -70,7 +70,7 @@ struct arpt_arp {
__u8 flags;
/* Inverse flags */
__u16 invflags;
-};
+} __attribute__((aligned(4)));
/* Values for "flag" field in struct arpt_ip (general arp structure).
* No flags defined yet.
--- a/net/core/utils.c
+++ b/net/core/utils.c
@@ -464,8 +464,14 @@ void inet_proto_csum_replace16(__sum16 *
bool pseudohdr)
{
__be32 diff[] = {
- ~from[0], ~from[1], ~from[2], ~from[3],
- to[0], to[1], to[2], to[3],
+ ~net_hdr_word(&from[0]),
+ ~net_hdr_word(&from[1]),
+ ~net_hdr_word(&from[2]),
+ ~net_hdr_word(&from[3]),
+ net_hdr_word(&to[0]),
+ net_hdr_word(&to[1]),
+ net_hdr_word(&to[2]),
+ net_hdr_word(&to[3]),
};
if (skb->ip_summed != CHECKSUM_PARTIAL) {
*sum = csum_fold(csum_partial(diff, sizeof(diff),
--- a/include/linux/etherdevice.h
+++ b/include/linux/etherdevice.h
@@ -480,7 +480,7 @@ static inline bool is_etherdev_addr(cons
* @b: Pointer to Ethernet header
*
* Compare two Ethernet headers, returns 0 if equal.
- * This assumes that the network header (i.e., IP header) is 4-byte
+ * This assumes that the network header (i.e., IP header) is 2-byte
* aligned OR the platform can handle unaligned access. This is the
* case for all packets coming into netif_receive_skb or similar
* entry points.
@@ -503,11 +503,12 @@ static inline unsigned long compare_ethe
fold |= *(unsigned long *)(a + 6) ^ *(unsigned long *)(b + 6);
return fold;
#else
- u32 *a32 = (u32 *)((u8 *)a + 2);
- u32 *b32 = (u32 *)((u8 *)b + 2);
+ const u16 *a16 = a;
+ const u16 *b16 = b;
- return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) |
- (a32[1] ^ b32[1]) | (a32[2] ^ b32[2]);
+ return (a16[0] ^ b16[0]) | (a16[1] ^ b16[1]) | (a16[2] ^ b16[2]) |
+ (a16[3] ^ b16[3]) | (a16[4] ^ b16[4]) | (a16[5] ^ b16[5]) |
+ (a16[6] ^ b16[6]);
#endif
}
--- a/net/ipv4/tcp_offload.c
+++ b/net/ipv4/tcp_offload.c
@@ -226,7 +226,7 @@ struct sk_buff *tcp_gro_receive(struct l
th2 = tcp_hdr(p);
- if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
+ if (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) {
NAPI_GRO_CB(p)->same_flow = 0;
continue;
}
@@ -244,8 +244,8 @@ found:
~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH));
flush |= (__force int)(th->ack_seq ^ th2->ack_seq);
for (i = sizeof(*th); i < thlen; i += 4)
- flush |= *(u32 *)((u8 *)th + i) ^
- *(u32 *)((u8 *)th2 + i);
+ flush |= net_hdr_word((u8 *)th + i) ^
+ net_hdr_word((u8 *)th2 + i);
/* When we receive our second frame we can made a decision on if we
* continue this flow as an atomic flow with a fixed ID or if we use
--- a/net/ipv6/netfilter/ip6table_mangle.c
+++ b/net/ipv6/netfilter/ip6table_mangle.c
@@ -50,7 +50,7 @@ ip6t_mangle_out(struct sk_buff *skb, con
hop_limit = ipv6_hdr(skb)->hop_limit;
/* flowlabel and prio (includes version, which shouldn't change either */
- flowlabel = *((u_int32_t *)ipv6_hdr(skb));
+ flowlabel = net_hdr_word(ipv6_hdr(skb));
ret = ip6t_do_table(skb, state, state->net->ipv6.ip6table_mangle);
@@ -59,7 +59,7 @@ ip6t_mangle_out(struct sk_buff *skb, con
!ipv6_addr_equal(&ipv6_hdr(skb)->daddr, &daddr) ||
skb->mark != mark ||
ipv6_hdr(skb)->hop_limit != hop_limit ||
- flowlabel != *((u_int32_t *)ipv6_hdr(skb)))) {
+ flowlabel != net_hdr_word(ipv6_hdr(skb)))) {
err = ip6_route_me_harder(state->net, skb);
if (err < 0)
ret = NF_DROP_ERR(err);

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