802 lines
22 KiB
C++
802 lines
22 KiB
C++
//===== Copyright 1996-2005, Valve Corporation, All rights reserved. ======//
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//
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// Purpose: Implementation of our SIMD functions for the 360.
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//==============================================================//
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#ifndef DBG_H
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#include "tier0/dbg.h"
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#endif
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//---------------------------------------------------------------------
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// X360 implementation
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//---------------------------------------------------------------------
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FORCEINLINE float & FloatSIMD( fltx4 & a, int idx )
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{
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fltx4_union & a_union = (fltx4_union &)a;
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return a_union.m128_f32[idx];
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}
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FORCEINLINE unsigned int & UIntSIMD( fltx4 & a, int idx )
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{
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fltx4_union & a_union = (fltx4_union &)a;
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return a_union.m128_u32[idx];
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}
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FORCEINLINE fltx4 AddSIMD( const fltx4 & a, const fltx4 & b )
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{
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return __vaddfp( a, b );
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}
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FORCEINLINE fltx4 SubSIMD( const fltx4 & a, const fltx4 & b ) // a-b
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{
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return __vsubfp( a, b );
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}
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FORCEINLINE fltx4 MulSIMD( const fltx4 & a, const fltx4 & b ) // a*b
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{
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return __vmulfp( a, b );
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}
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FORCEINLINE fltx4 MaddSIMD( const fltx4 & a, const fltx4 & b, const fltx4 & c ) // a*b + c
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{
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return __vmaddfp( a, b, c );
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}
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FORCEINLINE fltx4 MsubSIMD( const fltx4 & a, const fltx4 & b, const fltx4 & c ) // c - a*b
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{
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return __vnmsubfp( a, b, c );
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};
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FORCEINLINE fltx4 Dot3SIMD( const fltx4 &a, const fltx4 &b )
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{
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return __vmsum3fp( a, b );
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}
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FORCEINLINE fltx4 Dot4SIMD( const fltx4 &a, const fltx4 &b )
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{
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return __vmsum4fp( a, b );
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}
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FORCEINLINE fltx4 SinSIMD( const fltx4 &radians )
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{
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return XMVectorSin( radians );
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}
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FORCEINLINE void SinCos3SIMD( fltx4 &sine, fltx4 &cosine, const fltx4 &radians )
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{
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XMVectorSinCos( &sine, &cosine, radians );
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}
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FORCEINLINE void SinCosSIMD( fltx4 &sine, fltx4 &cosine, const fltx4 &radians )
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{
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XMVectorSinCos( &sine, &cosine, radians );
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}
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FORCEINLINE void CosSIMD( fltx4 &cosine, const fltx4 &radians )
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{
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cosine = XMVectorCos( radians );
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}
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FORCEINLINE fltx4 ArcSinSIMD( const fltx4 &sine )
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{
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return XMVectorASin( sine );
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}
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FORCEINLINE fltx4 ArcCosSIMD( const fltx4 &cs )
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{
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return XMVectorACos( cs );
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}
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// tan^1(a/b) .. ie, pass sin in as a and cos in as b
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FORCEINLINE fltx4 ArcTan2SIMD( const fltx4 &a, const fltx4 &b )
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{
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return XMVectorATan2( a, b );
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}
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// DivSIMD defined further down, since it uses ReciprocalSIMD
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FORCEINLINE fltx4 MaxSIMD( const fltx4 & a, const fltx4 & b ) // max(a,b)
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{
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return __vmaxfp( a, b );
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}
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FORCEINLINE fltx4 MinSIMD( const fltx4 & a, const fltx4 & b ) // min(a,b)
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{
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return __vminfp( a, b );
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}
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FORCEINLINE fltx4 AndSIMD( const fltx4 & a, const fltx4 & b ) // a & b
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{
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return __vand( a, b );
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}
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FORCEINLINE fltx4 AndNotSIMD( const fltx4 & a, const fltx4 & b ) // ~a & b
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{
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// NOTE: a and b are swapped in the call: SSE complements the first argument, VMX the second
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return __vandc( b, a );
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}
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FORCEINLINE fltx4 XorSIMD( const fltx4 & a, const fltx4 & b ) // a ^ b
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{
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return __vxor( a, b );
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}
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FORCEINLINE fltx4 OrSIMD( const fltx4 & a, const fltx4 & b ) // a | b
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{
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return __vor( a, b );
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}
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FORCEINLINE fltx4 NegSIMD(const fltx4 &a) // negate: -a
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{
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return XMVectorNegate(a);
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}
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FORCEINLINE bool IsAllZeros( const fltx4 & a ) // all floats of a zero?
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{
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unsigned int equalFlags = 0;
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__vcmpeqfpR( a, Four_Zeros, &equalFlags );
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return XMComparisonAllTrue( equalFlags );
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}
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FORCEINLINE bool IsAnyZeros( const fltx4 & a ) // any floats are zero?
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{
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unsigned int conditionregister;
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XMVectorEqualR(&conditionregister, a, XMVectorZero());
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return XMComparisonAnyTrue(conditionregister);
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}
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FORCEINLINE bool IsAnyXYZZero( const fltx4 &a ) // are any of x,y,z zero?
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{
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// copy a's x component into w, in case w was zero.
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fltx4 temp = __vrlimi(a, a, 1, 1);
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unsigned int conditionregister;
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XMVectorEqualR(&conditionregister, temp, XMVectorZero());
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return XMComparisonAnyTrue(conditionregister);
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}
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/// for branching when a.xyzw > b.xyzw
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FORCEINLINE bool IsAllGreaterThan( const fltx4 &a, const fltx4 &b )
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{
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unsigned int cr;
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XMVectorGreaterR(&cr,a,b);
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return XMComparisonAllTrue(cr);
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}
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/// for branching when a.xyzw >= b.xyzw
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FORCEINLINE bool IsAllGreaterThanOrEq( const fltx4 &a, const fltx4 &b )
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{
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unsigned int cr;
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XMVectorGreaterOrEqualR(&cr,a,b);
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return XMComparisonAllTrue(cr);
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}
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/// for branching when a.xyzw > b.xyzw
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FORCEINLINE bool IsAnyGreaterThan( const fltx4 &a, const fltx4 &b )
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{
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unsigned int cr;
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XMVectorGreaterR(&cr,a,b);
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return XMComparisonAnyTrue(cr);
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}
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/// for branching when a.xyzw >= b.xyzw
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FORCEINLINE bool IsAnyGreaterThanOrEq( const fltx4 &a, const fltx4 &b )
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{
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unsigned int cr;
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XMVectorGreaterOrEqualR(&cr,a,b);
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return XMComparisonAnyTrue(cr);
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}
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// For branching if all a.xyzw == b.xyzw
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FORCEINLINE bool IsAllEqual( const fltx4 & a, const fltx4 & b )
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{
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unsigned int cr;
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XMVectorEqualR(&cr,a,b);
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return XMComparisonAllTrue(cr);
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}
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FORCEINLINE int TestSignSIMD( const fltx4 & a ) // mask of which floats have the high bit set
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{
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// NOTE: this maps to SSE way better than it does to VMX (most code uses IsAnyNegative(), though)
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int nRet = 0;
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const fltx4_union & a_union = (const fltx4_union &)a;
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nRet |= ( a_union.m128_u32[0] & 0x80000000 ) >> 31; // sign(x) -> bit 0
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nRet |= ( a_union.m128_u32[1] & 0x80000000 ) >> 30; // sign(y) -> bit 1
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nRet |= ( a_union.m128_u32[2] & 0x80000000 ) >> 29; // sign(z) -> bit 2
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nRet |= ( a_union.m128_u32[3] & 0x80000000 ) >> 28; // sign(w) -> bit 3
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return nRet;
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}
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// Squelch the w component of a vector to +0.0.
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// Most efficient when you say a = SetWToZeroSIMD(a) (avoids a copy)
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FORCEINLINE fltx4 SetWToZeroSIMD( const fltx4 & a )
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{
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return __vrlimi( a, __vzero(), 1, 0 );
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}
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FORCEINLINE bool IsAnyNegative( const fltx4 & a ) // (a.x < 0) || (a.y < 0) || (a.z < 0) || (a.w < 0)
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{
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// NOTE: this tests the top bits of each vector element using integer math
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// (so it ignores NaNs - it will return true for "-NaN")
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unsigned int equalFlags = 0;
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fltx4 signMask = __vspltisw( -1 ); // 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF (low order 5 bits of each element = 31)
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signMask = __vslw( signMask, signMask ); // 0x80000000 0x80000000 0x80000000 0x80000000
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__vcmpequwR( Four_Zeros, __vand( signMask, a ), &equalFlags );
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return !XMComparisonAllTrue( equalFlags );
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}
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FORCEINLINE fltx4 CmpEqSIMD( const fltx4 & a, const fltx4 & b ) // (a==b) ? ~0:0
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{
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return __vcmpeqfp( a, b );
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}
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FORCEINLINE fltx4 CmpGtSIMD( const fltx4 & a, const fltx4 & b ) // (a>b) ? ~0:0
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{
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return __vcmpgtfp( a, b );
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}
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FORCEINLINE fltx4 CmpGeSIMD( const fltx4 & a, const fltx4 & b ) // (a>=b) ? ~0:0
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{
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return __vcmpgefp( a, b );
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}
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FORCEINLINE fltx4 CmpLtSIMD( const fltx4 & a, const fltx4 & b ) // (a<b) ? ~0:0
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{
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return __vcmpgtfp( b, a );
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}
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FORCEINLINE fltx4 CmpLeSIMD( const fltx4 & a, const fltx4 & b ) // (a<=b) ? ~0:0
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{
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return __vcmpgefp( b, a );
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}
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FORCEINLINE fltx4 CmpInBoundsSIMD( const fltx4 & a, const fltx4 & b ) // (a <= b && a >= -b) ? ~0 : 0
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{
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return XMVectorInBounds( a, b );
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}
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FORCEINLINE fltx4 Cmp01EqSIMD( const fltx4 & a, const fltx4 & b ) // (a==b) ? 1.0:0
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{
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return AndSIMD( Four_Ones, __vcmpeqfp( a, b ) );
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}
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FORCEINLINE fltx4 Cmp01GtSIMD( const fltx4 & a, const fltx4 & b ) // (a>b) ? 1.0:0
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{
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return AndSIMD( Four_Ones, __vcmpgtfp( a, b ) );
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}
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FORCEINLINE fltx4 Cmp01GeSIMD( const fltx4 & a, const fltx4 & b ) // (a>=b) ? 1.0:0
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{
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return AndSIMD( Four_Ones, __vcmpgefp( a, b ) );
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}
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FORCEINLINE fltx4 Cmp01LtSIMD( const fltx4 & a, const fltx4 & b ) // (a<b) ? 1.0:0
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{
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return AndSIMD( Four_Ones, __vcmpgtfp( b, a ) );
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}
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FORCEINLINE fltx4 Cmp01LeSIMD( const fltx4 & a, const fltx4 & b ) // (a<=b) ? 1.0:0
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{
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return AndSIMD( Four_Ones, __vcmpgefp( b, a ) );
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}
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FORCEINLINE fltx4 Cmp01InBoundsSIMD( const fltx4 & a, const fltx4 & b ) // (a <= b && a >= -b) ? 1.0 : 0
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{
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return AndSIMD( Four_Ones, XMVectorInBounds( a, b ) );
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}
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// returned[i] = ReplacementMask[i] == 0 ? OldValue : NewValue
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FORCEINLINE fltx4 MaskedAssign( const fltx4 & ReplacementMask, const fltx4 & NewValue, const fltx4 & OldValue )
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{
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return __vsel( OldValue, NewValue, ReplacementMask );
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}
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// AKA "Broadcast", "Splat"
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FORCEINLINE fltx4 ReplicateX4( float flValue ) // a,a,a,a
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{
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// NOTE: if flValue comes from a register, this causes a Load-Hit-Store stall (don't mix fpu/vpu math!)
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float * pValue = &flValue;
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Assert( pValue );
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Assert( ((unsigned int)pValue & 3) == 0);
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return __vspltw( __lvlx( pValue, 0 ), 0 );
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}
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FORCEINLINE fltx4 ReplicateX4( const float *pValue ) // a,a,a,a
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{
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Assert( pValue );
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return __vspltw( __lvlx( pValue, 0 ), 0 );
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}
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/// replicate a single 32 bit integer value to all 4 components of an m128
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FORCEINLINE fltx4 ReplicateIX4( int nValue )
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{
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// NOTE: if nValue comes from a register, this causes a Load-Hit-Store stall (should not mix ints with fltx4s!)
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int * pValue = &nValue;
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Assert( pValue );
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Assert( ((unsigned int)pValue & 3) == 0);
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return __vspltw( __lvlx( pValue, 0 ), 0 );
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}
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// Round towards positive infinity
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FORCEINLINE fltx4 CeilSIMD( const fltx4 &a )
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{
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return __vrfip(a);
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}
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// Round towards nearest integer
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FORCEINLINE fltx4 RoundSIMD( const fltx4 &a )
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{
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return __vrfin(a);
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}
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// Round towards negative infinity
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FORCEINLINE fltx4 FloorSIMD( const fltx4 &a )
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{
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return __vrfim(a);
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}
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FORCEINLINE fltx4 SqrtEstSIMD( const fltx4 & a ) // sqrt(a), more or less
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{
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// This is emulated from rsqrt
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return XMVectorSqrtEst( a );
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}
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FORCEINLINE fltx4 SqrtSIMD( const fltx4 & a ) // sqrt(a)
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{
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// This is emulated from rsqrt
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return XMVectorSqrt( a );
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}
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FORCEINLINE fltx4 ReciprocalSqrtEstSIMD( const fltx4 & a ) // 1/sqrt(a), more or less
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{
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return __vrsqrtefp( a );
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}
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FORCEINLINE fltx4 ReciprocalSqrtEstSaturateSIMD( const fltx4 & a )
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{
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// Convert zeros to epsilons
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fltx4 zero_mask = CmpEqSIMD( a, Four_Zeros );
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fltx4 a_safe = OrSIMD( a, AndSIMD( Four_Epsilons, zero_mask ) );
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return ReciprocalSqrtEstSIMD( a_safe );
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}
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FORCEINLINE fltx4 ReciprocalSqrtSIMD( const fltx4 & a ) // 1/sqrt(a)
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{
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// This uses Newton-Raphson to improve the HW result
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return XMVectorReciprocalSqrt( a );
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}
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FORCEINLINE fltx4 ReciprocalEstSIMD( const fltx4 & a ) // 1/a, more or less
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{
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return __vrefp( a );
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}
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/// 1/x for all 4 values. uses reciprocal approximation instruction plus newton iteration.
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/// No error checking!
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FORCEINLINE fltx4 ReciprocalSIMD( const fltx4 & a ) // 1/a
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{
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// This uses Newton-Raphson to improve the HW result
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return XMVectorReciprocal( a );
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}
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// FIXME: on 360, this is very slow, since it uses ReciprocalSIMD (do we need DivEstSIMD?)
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FORCEINLINE fltx4 DivSIMD( const fltx4 & a, const fltx4 & b ) // a/b
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{
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return MulSIMD( ReciprocalSIMD( b ), a );
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}
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// CHRISG: is it worth doing integer bitfiddling for this?
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// 2^x for all values (the antilog)
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FORCEINLINE fltx4 PowerOfTwoSIMD( const fltx4 &toPower )
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{
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return XMVectorExp(toPower);
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}
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// Clamps the components of a vector to a specified minimum and maximum range.
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FORCEINLINE fltx4 ClampVectorSIMD( FLTX4 in, FLTX4 min, FLTX4 max)
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{
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return XMVectorClamp(in, min, max);
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}
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FORCEINLINE fltx4 LoadUnalignedSIMD( const void *pSIMD )
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{
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return XMLoadVector4( pSIMD );
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}
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// load a 3-vector (as opposed to LoadUnalignedSIMD, which loads a 4-vec).
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FORCEINLINE fltx4 LoadUnaligned3SIMD( const void *pSIMD )
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{
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return XMLoadVector3( pSIMD );
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}
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// load a single unaligned float into the x component of a SIMD word
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FORCEINLINE fltx4 LoadUnalignedFloatSIMD( const float *pFlt )
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{
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return __lvlx( pFlt, 0 );
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}
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FORCEINLINE fltx4 LoadAlignedSIMD( const void *pSIMD )
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{
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return *( reinterpret_cast< const fltx4 *> ( pSIMD ) );
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}
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FORCEINLINE shortx8 LoadAlignedShortSIMD( const void *pSIMD )
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{
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return XMLoadVector4A( pSIMD );
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}
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FORCEINLINE shortx8 LoadUnalignedShortSIMD( const void *pSIMD )
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{
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return XMLoadVector4( pSIMD );
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}
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FORCEINLINE void StoreAlignedSIMD( float *pSIMD, const fltx4 & a )
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{
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*( reinterpret_cast< fltx4 *> ( pSIMD ) ) = a;
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}
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FORCEINLINE void StoreUnalignedSIMD( float *pSIMD, const fltx4 & a )
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{
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XMStoreVector4( pSIMD, a );
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}
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FORCEINLINE void StoreUnaligned3SIMD( float *pSIMD, const fltx4 & a )
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{
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XMStoreVector3( pSIMD, a );
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}
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// Fixed-point conversion and save as SIGNED INTS.
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// pDest->x = Int (vSrc.x)
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// note: some architectures have means of doing
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// fixed point conversion when the fix depth is
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// specified as an immediate.. but there is no way
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// to guarantee an immediate as a parameter to function
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// like this.
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FORCEINLINE void ConvertStoreAsIntsSIMD(intx4 * RESTRICT pDest, const fltx4 &vSrc)
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{
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fltx4 asInt = __vctsxs( vSrc, 0 );
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XMStoreVector4A(pDest->Base(), asInt);
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}
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FORCEINLINE void TransposeSIMD( fltx4 & x, fltx4 & y, fltx4 & z, fltx4 & w )
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{
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XMMATRIX xyzwMatrix = _XMMATRIX( x, y, z, w );
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xyzwMatrix = XMMatrixTranspose( xyzwMatrix );
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x = xyzwMatrix.r[0];
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y = xyzwMatrix.r[1];
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z = xyzwMatrix.r[2];
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w = xyzwMatrix.r[3];
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}
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// Return one in the fastest way -- faster even than loading.
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FORCEINLINE fltx4 LoadZeroSIMD( void )
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{
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return XMVectorZero();
|
|
}
|
|
|
|
// Return one in the fastest way -- faster even than loading.
|
|
FORCEINLINE fltx4 LoadOneSIMD( void )
|
|
{
|
|
return XMVectorSplatOne();
|
|
}
|
|
|
|
FORCEINLINE fltx4 SplatXSIMD( fltx4 a )
|
|
{
|
|
return XMVectorSplatX( a );
|
|
}
|
|
|
|
FORCEINLINE fltx4 SplatYSIMD( fltx4 a )
|
|
{
|
|
return XMVectorSplatY( a );
|
|
}
|
|
|
|
FORCEINLINE fltx4 SplatZSIMD( fltx4 a )
|
|
{
|
|
return XMVectorSplatZ( a );
|
|
}
|
|
|
|
FORCEINLINE fltx4 SplatWSIMD( fltx4 a )
|
|
{
|
|
return XMVectorSplatW( a );
|
|
}
|
|
|
|
FORCEINLINE fltx4 SetXSIMD( const fltx4& a, const fltx4& x )
|
|
{
|
|
fltx4 result = __vrlimi(a, x, 8, 0);
|
|
return result;
|
|
}
|
|
|
|
FORCEINLINE fltx4 SetYSIMD( const fltx4& a, const fltx4& y )
|
|
{
|
|
fltx4 result = __vrlimi(a, y, 4, 0);
|
|
return result;
|
|
}
|
|
|
|
FORCEINLINE fltx4 SetZSIMD( const fltx4& a, const fltx4& z )
|
|
{
|
|
fltx4 result = __vrlimi(a, z, 2, 0);
|
|
return result;
|
|
}
|
|
|
|
FORCEINLINE fltx4 SetWSIMD( const fltx4& a, const fltx4& w )
|
|
{
|
|
fltx4 result = __vrlimi(a, w, 1, 0);
|
|
return result;
|
|
}
|
|
|
|
|
|
FORCEINLINE fltx4 RotateLeft( const fltx4 & a )
|
|
{
|
|
fltx4 compareOne = a;
|
|
return __vrlimi( compareOne, a, 8 | 4 | 2 | 1, 1 );
|
|
}
|
|
|
|
FORCEINLINE fltx4 RotateLeft2( const fltx4 & a )
|
|
{
|
|
fltx4 compareOne = a;
|
|
return __vrlimi( compareOne, a, 8 | 4 | 2 | 1, 2 );
|
|
}
|
|
|
|
FORCEINLINE fltx4 RotateRight( const fltx4 & a )
|
|
{
|
|
fltx4 compareOne = a;
|
|
return __vrlimi( compareOne, a, 8 | 4 | 2 | 1, 3 );
|
|
}
|
|
|
|
FORCEINLINE fltx4 RotateRight2( const fltx4 & a )
|
|
{
|
|
fltx4 compareOne = a;
|
|
return __vrlimi( compareOne, a, 8 | 4 | 2 | 1, 2 );
|
|
}
|
|
|
|
|
|
|
|
|
|
// find the lowest component of a.x, a.y, a.z,
|
|
// and replicate it to the whole return value.
|
|
// ignores a.w.
|
|
// Though this is only five instructions long,
|
|
// they are all dependent, making this stall city.
|
|
// Forcing this inline should hopefully help with scheduling.
|
|
FORCEINLINE fltx4 FindLowestSIMD3( const fltx4 & a )
|
|
{
|
|
// a is [x,y,z,G] (where G is garbage)
|
|
// rotate left by one
|
|
fltx4 compareOne = a ;
|
|
compareOne = __vrlimi( compareOne, a, 8 | 4 , 1 );
|
|
// compareOne is [y,z,G,G]
|
|
fltx4 retval = MinSIMD( a, compareOne );
|
|
// retVal is [min(x,y), min(y,z), G, G]
|
|
compareOne = __vrlimi( compareOne, a, 8 , 2);
|
|
// compareOne is [z, G, G, G]
|
|
retval = MinSIMD( retval, compareOne );
|
|
// retVal = [ min(min(x,y),z), G, G, G ]
|
|
|
|
// splat the x component out to the whole vector and return
|
|
return SplatXSIMD( retval );
|
|
}
|
|
|
|
// find the highest component of a.x, a.y, a.z,
|
|
// and replicate it to the whole return value.
|
|
// ignores a.w.
|
|
// Though this is only five instructions long,
|
|
// they are all dependent, making this stall city.
|
|
// Forcing this inline should hopefully help with scheduling.
|
|
FORCEINLINE fltx4 FindHighestSIMD3( const fltx4 & a )
|
|
{
|
|
// a is [x,y,z,G] (where G is garbage)
|
|
// rotate left by one
|
|
fltx4 compareOne = a ;
|
|
compareOne = __vrlimi( compareOne, a, 8 | 4 , 1 );
|
|
// compareOne is [y,z,G,G]
|
|
fltx4 retval = MaxSIMD( a, compareOne );
|
|
// retVal is [max(x,y), max(y,z), G, G]
|
|
compareOne = __vrlimi( compareOne, a, 8 , 2);
|
|
// compareOne is [z, G, G, G]
|
|
retval = MaxSIMD( retval, compareOne );
|
|
// retVal = [ max(max(x,y),z), G, G, G ]
|
|
|
|
// splat the x component out to the whole vector and return
|
|
return SplatXSIMD( retval );
|
|
}
|
|
|
|
|
|
|
|
// ------------------------------------
|
|
// INTEGER SIMD OPERATIONS.
|
|
// ------------------------------------
|
|
|
|
// Load 4 aligned words into a SIMD register
|
|
FORCEINLINE i32x4 LoadAlignedIntSIMD( const void * RESTRICT pSIMD)
|
|
{
|
|
return XMLoadVector4A(pSIMD);
|
|
}
|
|
|
|
// Load 4 unaligned words into a SIMD register
|
|
FORCEINLINE i32x4 LoadUnalignedIntSIMD(const void * RESTRICT pSIMD)
|
|
{
|
|
return XMLoadVector4( pSIMD );
|
|
}
|
|
|
|
// save into four words, 16-byte aligned
|
|
FORCEINLINE void StoreAlignedIntSIMD( int32 *pSIMD, const fltx4 & a )
|
|
{
|
|
*( reinterpret_cast< i32x4 *> ( pSIMD ) ) = a;
|
|
}
|
|
|
|
FORCEINLINE void StoreAlignedIntSIMD( intx4 &pSIMD, const fltx4 & a )
|
|
{
|
|
*( reinterpret_cast< i32x4 *> ( pSIMD.Base() ) ) = a;
|
|
}
|
|
|
|
FORCEINLINE void StoreUnalignedIntSIMD( int32 *pSIMD, const fltx4 & a )
|
|
{
|
|
XMStoreVector4(pSIMD, a);
|
|
}
|
|
|
|
// Load four consecutive uint16's, and turn them into floating point numbers.
|
|
// This function isn't especially fast and could be made faster if anyone is
|
|
// using it heavily.
|
|
FORCEINLINE fltx4 LoadAndConvertUint16SIMD( const uint16 *pInts )
|
|
{
|
|
return XMLoadUShort4(reinterpret_cast<const XMUSHORT4 *>(pInts));
|
|
}
|
|
|
|
// a={ a.x, a.z, b.x, b.z }
|
|
// combine two fltx4s by throwing away every other field.
|
|
FORCEINLINE fltx4 CompressSIMD( fltx4 const & a, fltx4 const &b )
|
|
{
|
|
return XMVectorPermute( a, b, XMVectorPermuteControl( 0, 2, 4, 6 ) );
|
|
}
|
|
|
|
// a={ a.x, b.x, c.x, d.x }
|
|
// combine 4 fltx4s by throwing away 3/4s of the fields
|
|
// TODO: make more efficient by doing this in a parallel way at the caller
|
|
// Compress4SIMD(FourVectors.. )
|
|
FORCEINLINE fltx4 Compress4SIMD( fltx4 const a, fltx4 const &b, fltx4 const &c, fltx4 const &d )
|
|
{
|
|
fltx4 abcd = __vrlimi( a, b, 4, 3 ); // a.x, b.x, a.z, a.w
|
|
abcd = __vrlimi( abcd, c, 2, 2 ); // ax, bx, cx, aw
|
|
abcd = __vrlimi( abcd, d, 1, 1 ); // ax, bx, cx, dx
|
|
|
|
return abcd;
|
|
}
|
|
|
|
// Take a fltx4 containing fixed-point uints and
|
|
// return them as single precision floats. No
|
|
// fixed point conversion is done.
|
|
FORCEINLINE fltx4 UnsignedIntConvertToFltSIMD( const i32x4 &vSrcA )
|
|
{
|
|
return __vcfux( vSrcA, 0 );
|
|
}
|
|
|
|
// Take a fltx4 containing fixed-point sints and
|
|
// return them as single precision floats. No
|
|
// fixed point conversion is done.
|
|
FORCEINLINE fltx4 SignedIntConvertToFltSIMD( const i32x4 &vSrcA )
|
|
{
|
|
return __vcfsx( vSrcA, 0 );
|
|
}
|
|
|
|
// Take a fltx4 containing fixed-point uints and
|
|
// return them as single precision floats. Each uint
|
|
// will be divided by 2^immed after conversion
|
|
// (eg, this is fixed point math).
|
|
/* as if:
|
|
FORCEINLINE fltx4 UnsignedIntConvertToFltSIMD( const i32x4 &vSrcA, unsigned int uImmed )
|
|
{
|
|
return __vcfux( vSrcA, uImmed );
|
|
}
|
|
*/
|
|
#define UnsignedFixedIntConvertToFltSIMD(vSrcA, uImmed) (__vcfux( (vSrcA), (uImmed) ))
|
|
|
|
// Take a fltx4 containing fixed-point sints and
|
|
// return them as single precision floats. Each int
|
|
// will be divided by 2^immed (eg, this is fixed point
|
|
// math).
|
|
/* as if:
|
|
FORCEINLINE fltx4 SignedIntConvertToFltSIMD( const i32x4 &vSrcA, unsigned int uImmed )
|
|
{
|
|
return __vcfsx( vSrcA, uImmed );
|
|
}
|
|
*/
|
|
#define SignedFixedIntConvertToFltSIMD(vSrcA, uImmed) (__vcfsx( (vSrcA), (uImmed) ))
|
|
|
|
// set all components of a vector to a signed immediate int number.
|
|
/* as if:
|
|
FORCEINLINE fltx4 IntSetImmediateSIMD(int toImmediate)
|
|
{
|
|
return __vspltisw( toImmediate );
|
|
}
|
|
*/
|
|
#define IntSetImmediateSIMD(x) (__vspltisw(x))
|
|
|
|
/*
|
|
works on fltx4's as if they are four uints.
|
|
the first parameter contains the words to be shifted,
|
|
the second contains the amount to shift by AS INTS
|
|
|
|
for i = 0 to 3
|
|
shift = vSrcB_i*32:(i*32)+4
|
|
vReturned_i*32:(i*32)+31 = vSrcA_i*32:(i*32)+31 << shift
|
|
*/
|
|
FORCEINLINE fltx4 IntShiftLeftWordSIMD(fltx4 vSrcA, fltx4 vSrcB)
|
|
{
|
|
return __vslw(vSrcA, vSrcB);
|
|
}
|
|
|
|
FORCEINLINE float SubFloat( const fltx4 & a, int idx )
|
|
{
|
|
// NOTE: if the output goes into a register, this causes a Load-Hit-Store stall (don't mix fpu/vpu math!)
|
|
const fltx4_union & a_union = (const fltx4_union &)a;
|
|
return a_union.m128_f32[ idx ];
|
|
}
|
|
|
|
FORCEINLINE float & SubFloat( fltx4 & a, int idx )
|
|
{
|
|
fltx4_union & a_union = (fltx4_union &)a;
|
|
return a_union.m128_f32[idx];
|
|
}
|
|
|
|
/// Set one component of a SIMD word with the given float value.
|
|
/// This function is a template because the native implementation of
|
|
/// this on PPC platforms requires that the component be given as a
|
|
/// compiler immediate -- not a function parameter, not a const function
|
|
/// parameter, not even a load from a const static array. It has to be
|
|
/// a real immediate.
|
|
/// \param NCOMPONENT 0 is x, 1 is y, 2 is z, 3 is w.
|
|
/// \note This function is not particularly performant on any platform (because of
|
|
/// the load from float), so prefer a masked assign from a fltx4 wherever
|
|
/// possible.
|
|
template < unsigned int NCOMPONENT >
|
|
FORCEINLINE fltx4 SetComponentSIMD( const fltx4& a, float flValue )
|
|
{
|
|
// vrlimi can only take an immediate opcode -- that is a constant
|
|
// passed in from the compiler, not a function parameter, nor an
|
|
// element loaded from an array, not even a const static array.
|
|
#define SETCOMPONENTSIMD_MASK_IMMEDIATE ( NCOMPONENT == 0 ) ? 8 :\
|
|
( NCOMPONENT == 1 ) ? 4 :\
|
|
( NCOMPONENT == 2 ) ? 2 :\
|
|
( NCOMPONENT == 3 ) ? 1 :\
|
|
17 //< a meaningless immediate intended to make the compiler angry
|
|
|
|
fltx4 val = ReplicateX4( flValue );
|
|
fltx4 result = __vrlimi(a, val, SETCOMPONENTSIMD_MASK_IMMEDIATE, 0);
|
|
return result;
|
|
|
|
#undef SETCOMPONENTSIMD_MASK_IMMEDIATE
|
|
}
|
|
|
|
|
|
FORCEINLINE uint32 SubFloatConvertToInt( const fltx4 & a, int idx )
|
|
{
|
|
fltx4 t = __vctuxs( a, 0 );
|
|
const fltx4_union & a_union = (const fltx4_union &)t;
|
|
return a_union.m128_u32[idx];
|
|
}
|
|
|
|
|
|
FORCEINLINE uint32 SubInt( const fltx4 & a, int idx )
|
|
{
|
|
const fltx4_union & a_union = (const fltx4_union &)a;
|
|
return a_union.m128_u32[idx];
|
|
}
|
|
|
|
FORCEINLINE uint32 & SubInt( fltx4 & a, int idx )
|
|
{
|
|
fltx4_union & a_union = (fltx4_union &)a;
|
|
return a_union.m128_u32[idx];
|
|
}
|